CN101860408B - Synchronous digital hierarchy signal transmission method - Google Patents
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Abstract
The invention provides a synchronous digital hierarchy signal transmission method. In the method, a block frame consisting of 9 rows of bytes and 270 columns of bytes is adopted to bear E1 signals, wherein only 30 bytes in the block frame are occupied by fields used for channel management and multiplexing control, while the other 2,400 bytes are all used for bearing the E1 signals. The method hasthe advantages that: the block frame adopted in the method has a structure, similar to that of an STM-1 frame, consisting of 9 rows of bytes and the 270 columns of bytes; the transmission can be realized in transmission channels with an STM-1 rate by adopting a conventional SDH signal transmission mode; bandwidth utilization rate can maximally reach 98.77 percent; and the method is applied to microwave communication transmission.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a transmission method of synchronous digital series signals.
Background
In digital communication systems, the transmitted signal is a sequence of digitized pulses. In a Digital transmission system, there are two Digital transmission series, one is called "Plesiochronous Digital Hierarchy" (PDH for short); the other is called "Synchronous Digital Hierarchy" (SDH for short).
In a system using Plesiochronous Digital Hierarchy (PDH), high-precision clocks are respectively set at each node of a digital communication network, and signals of the clocks have uniform standard rates. Although the accuracy of each clock is high, there are always some minor differences. In order to ensure the quality of communication, it is required that the difference between these clocks does not exceed a prescribed range. Therefore, this synchronization method is not truly synchronous in a strict sense, and is called "quasi-synchronization". With the rapid development of digital communication, direct point-to-point transmission is less and less, and most of digital transmission is switched, so the PDH series cannot meet the requirements of modern telecommunication service development and modern telecommunication network management.
Synchronous Digital Hierarchy (SDH) is an integrated information transmission network that integrates multiplexing, line transmission, and switching functions and is operated by a unified network management system. The system can realize multiple functions of effective network management, real-time service monitoring, dynamic network maintenance, intercommunication among equipment of different manufacturers and the like, can greatly improve the utilization rate of network resources, reduce the management and maintenance cost, realize flexible, reliable and efficient network operation and maintenance, is suitable for optical fibers and is also suitable for microwave and satellite transmission, thereby being a hotspot for development and application in the transmission technology in the world information field at present and being widely valued by people.
The information structure level adopted by the SDH is called a Synchronous Transport Module STM-N (N is 1, 4, 16, 64), the most basic Module is STM-1, four STM-1 Synchronous multiplexes form STM-4, 16 STM-1 or four STM-4 Synchronous multiplexes form STM-16. The SDH uses a block-like frame structure to carry information, each frame is composed of 9 vertical lines and 270 × N horizontal columns of bytes (where N is identical to N of STM-N, indicating that the signal is formed by N STM-1 through byte interleave multiplexing), each byte is 8 bits, and the frame period is 125 μ s, i.e., 8000 frames are transmitted per second. Taking an STM-1 signal as an example, as shown in fig. 1, the whole STM-1 frame structure is divided into three regions, i.e., a Section OverHead (SOH) region, an AU-PTR (AU-PTR) region and a Payload (Payload) region, where the Section OverHead region is mainly used for operation, management, maintenance and assignment of a network to ensure that information can be transmitted normally and flexibly, and is further divided into a Regeneration Section OverHead (RSOH) and a Multiplex Section OverHead (MSOH). The position of the regeneration section overhead in an STM-1 frame is 1 st to 9 th columns of 1 st to 3 rd rows, and 3 x 9 bytes in total, and the position of the multiplexing section overhead in the STM-1 frame is 1 st to 9 th columns of 5 th to 9 th rows, and 5 x 9 bytes in total; the management unit pointer is located in the 1 st to 9 th columns of the 4 th row in the STM-1 frame, and is 9 bytes in total, and is used for indicating the accurate position of the information first byte in the payload area in the STM-1 frame so as to correctly separate the payload when receiving. The byte definitions in the Regenerated Section Overhead (RSOH), the Multiplex Section Overhead (MSOH) and the management unit pointer (AU-PTR) in the STM-1 frame are as shown in fig. 2, all defined according to the standard specification of SDH. The payload area is used to store the bits actually used for information services and a small number of channel overhead bytes used for channel maintenance management. The STM-1 frame is transmitted in the frame structure sequence from top to bottom row by row and from left to right row by row, and the transmission rate is 9 multiplied by 270 multiplied by 8bit multiplied by 8000 which is 155.520 Mb/s.
Because the pulse coding of the digital communication system in China adopts the European E1 standard, an STM-1 module is equivalent to a multi-channel E1 signal module. An E1 signal contains 32 slots, each slot carrying 8 bits of data, for a total of 256 bits, with 8000 frames transmitted per second, so that the transmission rate of the E1 signal is 256 bits × 8000 ═ 2.048 Mb/s. In the traditional synchronous digital series signal transmission, as the overhead and the management unit pointer in the middle section of the STM-1 frame consume 81 bytes, the actual payload area for carrying the E1 signal only has 2349 bytes, and after the E1 signal is packed and multiplexed according to the SDH standard virtual container, one STM-1 frame can only carry 63E 1 signals at most, and the bandwidth utilization rate is only (2.048 × 63)/155.520 ≈ 82.96%. The defect of low bandwidth utilization rate in the traditional synchronous digital series signal transmission is not obvious in the common optical fiber transmission medium, but the utilization of the transmission bandwidth is very important when the SDH is used for microwave transmission.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for transmitting synchronous digital serial signals, which utilizes multiplexing technology to multiplex a plurality of E1 signals to an STM-1 rate transmission channel to improve bandwidth utilization.
The purpose of the invention is realized as follows: a transmission method of synchronous digital series signal includes using block frame composed of 9 rows and 270 columns of bytes to carry E1 signal, multiplexing multiple block frames into multiframe and sending to transmission channel of STM-1 rate for transmission; the block frame comprises a management overhead field, a multiplexing additional field and a net load field; the management overhead field occupies 27 bytes in the block frame and is used for comprehensively monitoring and managing the transmission channel; the multiplexing additional field occupies 3 bytes in the block frame and is used for indicating sequence information of the multiframe, a code rate adjusting position pointer, adjusting control information, parity check information and alarm information returned by a receiving end; the payload field occupies the remaining 2400 bytes in the block frame for carrying the E1 signal. The multiframe is formed by multiplexing 75 block-shaped frames.
Specifically, the byte definition in the management overhead field is the same as the byte definition in the RSOH area of the STM-1 frame, including: framing bytes A1 and A2 for frame header indication and positioning of the blocky frame; a regeneration section tracking byte J0 for ensuring the correct butt joint of the receiving end and the transmitting end; bit-interleaved parity byte B1 for bit error monitoring of the regeneration section overhead; a official transmission byte E1 for official contact of the reclaim section overhead; a user path byte F1 for transferring user-specific usage maintenance information; data communication channel bytes D1-D3 are used for transmitting maintenance management information.
Specifically, the multiplexing additional field is composed of a multiframe indication byte A3 and adjustment control bytes a4 and a 5; the multiframe indication byte A3 is used for indicating a parity type, sequence information of a multiframe and a code rate adjustment position pointer, wherein the most significant bit of the multiframe indication byte A3 is used for indicating the parity type of the multiframe, and other bits are used for indicating the sequence information of the multiframe and the code rate adjustment position pointer; the justification control byte a4 is used to indicate the first justification control information and parity information of the multiframe, wherein the most significant bit of justification control byte a4 is used to indicate parity information of the multiframe, the least significant bit is the first negative justification bit, and the other bits are used to indicate the first justification control instruction; the justification control byte a5 is used to indicate the second justification control information and the alarm information returned by the receiving end, wherein the most significant bit of the justification control byte a5 is used to indicate the alarm information returned by the receiving end, the least significant bit is the second negative justification bit, and the other bits are used to indicate the second justification control command. The justification bit for justification is located at the highest bit of the first 75 bytes in the payload field, and the two justification bits in each block frame are valid, with the specific location of the valid justification bits being specified by the justification location pointer.
Parity check information of the multiframe and alarm information returned by a receiving end are distributed to corresponding bytes of a plurality of block frames in the multiframe and are transmitted respectively; wherein, the parity check information of the multiframe is distributed to the adjustment control bytes A4 of the 1 st to 8 th block frames in the multiframe for transmission respectively; the alarm information returned by the receiving end is distributed to the adjustment control bytes A5 of the 1 st to 5 th block frames in the multiframe for transmission respectively, the adjustment control byte A5 of the 1 st block frame in the multiframe transmits MS-RDI alarm information, and the adjustment control byte A5 of the 2 nd to 5 th block frames in the multiframe transmits MS-REI alarm information.
Compared with the prior art that the STM-1 frame is adopted to carry the E1 signal, the transmission method of the synchronous digital series signal has the advantages that: the E1 signal is carried by adopting a unique block frame structure, the section overhead and multiplexing additional field in the block frame only occupy 30 bytes in the frame totally, the net load field actually used for carrying the E1 signal can reach 2400 bytes, the E1 signal does not need to be packed according to SDH standard virtual containers, the block frame can carry 75E 1 signals at most, the bandwidth utilization rate reaches (2.048 × 75)/155.520 ≈ 98.77%, the bandwidth utilization rate is greatly improved, and the method is suitable for microwave communication transmission.
Drawings
FIG. 1 is a STM-1 frame structure diagram;
FIG. 2 is a schematic diagram of byte definitions of overhead and management unit pointers in an STM-1 frame;
FIG. 3 is a block frame structure of an embodiment of the present invention;
FIG. 4 is a diagram illustrating byte definitions for management overhead fields according to one embodiment of the invention;
FIG. 5 is a schematic diagram of the bit structure of the multiframe indication byte A3;
FIG. 6 is a diagram illustrating a bit structure of the adjustment control byte A4;
FIG. 7 is a diagram illustrating a bit structure of the adjustment control byte A5;
FIG. 8 is a schematic diagram of the bit structure of any of the first 75 bytes in the payload field;
FIG. 9 is a block frame structure according to another embodiment of the present invention;
fig. 10 is a block frame structure diagram according to still another embodiment of the invention.
Detailed Description
The technical scheme of the invention is further explained by combining the drawings and the embodiment as follows:
example (b):
the invention provides a transmission method of synchronous digital series signals, which still adopts a block frame composed of 9 rows and 270 columns of bytes to bear an E1 signal, and multiplexes a plurality of block frames into a multiframe by a multiplexing technology. However, unlike the existing SDH standard, the block frame used in the present invention has a unique intra frame structure, and the present invention is directed to improving the actual utilization of the transmission bandwidth by means of the block frame structure. As shown in fig. 3, the blocky frame used in the present invention includes an overhead field for management (ASOH), additional fields for multiplexing (A3, a4, and a5), and a Payload field (Payload). When in transmission, every 75 blocky frames are multiplexed into a multiframe, and the blocky frame adopted by the invention has the same structure of 9 rows and 270 columns of bytes as the STM-1 frame, so the multiframe transmission can adopt the existing SDH signal transmission mode to send the multiframe to a transmission channel with the STM-1 rate for transmission.
The overhead field of Administration (ASOH) occupies 27 bytes within the block frame for comprehensive monitoring and management of the transmission channel. The specific definition of these 27 bytes can be self-defined as desired. However, particularly in the present embodiment, for design convenience, the byte definition of the management overhead field is the same as that of the playback-section overhead RSOH in the STM-1 frame, and the byte arrangement structure also remains the same as that of the playback-section overhead RSOH in the STM-1 frame, see fig. 4. In the embodiment, the 1 st to 6 th bytes of the 1 st row of the management overhead field are still framing bytes A1 and A2, which are used for frame header indication and positioning of a blocky frame, and the number of the A1 bytes and the number of the A2 bytes are 3 respectively; byte 7 is a playback segment tracking byte J0 to ensure proper interfacing between the receiving and transmitting ends. B1 on line 2 of the overhead field is a bit interleaved parity byte for error detection of the section overhead; e1 is still the official transport byte for the official contact of the reclaim section overhead; f1 is a user path byte for conveying user specific usage maintenance information. The D1-D3 bytes of row 3 of the overhead field are still data traffic channel bytes used to convey maintenance management information. Other byte definitions are also consistent, "×" reserved bytes, "×" unscrambled bytes, "Δ" bytes associated with the transmission medium, untagged bytes as spare bytes for future standards. These byte definitions are defined in accordance with the SDH standard specification.
The multiplexing additional field occupies 3 bytes in the block frame, and is composed of a multiframe indication byte A3 and adjustment control bytes A4 and A5, and is used for indicating the sequence information, the code rate adjustment position pointer, the adjustment control information, the parity check information and the alarm information returned by the receiving end of the multiframe. The multiframe indication byte A3 is used for indicating parity check type, sequence information of the multiframe and a code rate adjustment position pointer, the adjustment control byte A4 is used for indicating first adjustment control information and parity check information of the multiframe, and the adjustment control byte A5 is used for indicating second adjustment control information of the multiframe and alarm information returned by the receiving end. In addition, the most significant bits of the first 75 bytes in the payload field are all positive justification bits, but only two positive justification bits are valid in each block frame (the first positive justification bit and the second positive justification bit), and the specific location of the valid positive justification bits is specified by the justification position pointer. With the A3, a4, a5 bytes and the positive justification bits, 1 bit positive/negative justification can be made for each of the two E1 signals in each block frame. The bit structures of the A3, a4, a5 bytes are described in detail below.
The bit structure diagram of the multiframe indication byte a3 is shown in fig. 5. 8 bits (bit) of the A3 byte are bit0 bit7 from low bit to high bit, and the most significant bit7 bit is a BIP bit for indicating the parity type to determine whether parity check is odd check or even check. bits 0-6 are Q bits for indicating multiframe sequence information, and 7Q bits represent the sequence number of the current frame in the multiframe in binary form, and represent the range from "0000000" (i.e., "0" in decimal, indicating that the current frame is the 1 st frame in the multiframe) to "1001010" (i.e., "74" in decimal, indicating that the current frame is the 75 th frame in the multiframe). Meanwhile, the Q bit is also used as a code rate adjusting position pointer in a block, positive/negative code rate adjustment of 1 bit can be respectively carried out on two adjacent E1 signals in each block frame, and the code rate adjusting position pointer indicates the position of the previous E1 signal in two adjacent E1 signals; that is, the current frame is the second frame in the multiframe, which indicates that the corresponding second E1 signal of the 75E 1 signals carried by the current block frame and the adjacent E1 signal after the current block frame are positive/negative justified. For example, the Q bit in the a3 byte is "0000000", indicating that the justification is performed on the 1 st and 2 nd E1 signals in the payload field of the current frame; the Q bit is '0000001', indicating the code rate adjustment of the 2 nd and 3 rd E1 signals of the net load field in the current frame; … … and so on, the Q bit is "1001001", which indicates that the code rate adjustment is performed on the 74 th and 75 th E1 signals in the payload field of the current frame; the Q bit is "1001010," indicating that the 75 th and 1 st E1 signals in the current frame payload field are justified (consider the 1 st E1 signal as the next adjacent signal to the 75 th E1 signal). The adjustment directions of the two E1 signals for adjusting the code rate are controlled by a4 bytes and a5 bytes, respectively.
The schematic diagram of the bit structure of the adjustment control byte a4 is shown in fig. 6, and the bits from the low bit to the high bit are bit 0-bit 7. The most significant bit7 of the a4 byte is a P bit for indicating parity information of the previous multiframe. However, the parity check information of the previous multiframe has 8 bits, and the parity check information of the previous multiframe is not transmitted by only using 1P bit, so the transmission mode of frame allocation is adopted, and the P bits of the 1 st to 8 th block frames in the multiframe are used for respectively transmitting the 8-bit parity check information of the previous multiframe. The bits 1-bit 6 of A4 bytes are used for indicating a first adjusting control command, and controlling the E1 signal of the position pointed by the code rate adjusting position pointer to perform positive or negative code rate adjustment. Wherein, bit 1-bit 3 are C11A bit to indicate a first negative justification control instruction; bit0 is S11The bit is used as the first negative adjustment bit. When 3C 11When the bits are all "1", S1 is indicated1The bits are not loaded with valid information, and the first negative regulation bit is not used; when 3C 11When the bits are all "0", S1 is indicated1The bits are loaded with valid information and a negative justification is performed on the E1 signal for the position pointed by the justification position pointer. Bit 4-bit 6 of A4 bytes is C21A bit to indicate a first positive adjustment control command corresponding to a first positive adjustment bit within the block frame. When 3C 21When the bits are all "1", it is indicated that the first positive justification bit is loaded with valid bitsInformation, no corresponding forward justification is performed; when 3C 21If the bits are all "0", it indicates that no valid information is loaded in the first positive adjustment bit, and the E1 signal at the position pointed by the symbol rate adjustment position pointer is forward symbol rate adjusted.
The schematic diagram of the bit structure of the adjustment control byte a5 is shown in fig. 7, and the bits from the low bit to the high bit are bit 0-bit 7. The most significant bit7 of the a5 byte is an S bit to indicate the alarm information returned by the receiving end. There are two types of alarm information sent back from the receiving end: one is MS-RDI alarm information which indicates that the receiving end detects an incoming call fault or a multiplexing section is invalid; the other is MS-REI alarm information, which is used to transmit the number of error blocks detected by the receiving end, so that the transmitting end can know the receiving error condition of the receiving end according to the number. The transmission of the alarm information still adopts a frame distribution transmission mode, the S bit of the 1 st block frame in the multiframe is used for transmitting MS-RDI alarm information, and the S bit of the 2 nd to 5 th block frames in the multiframe is used for transmitting MS-REI alarm information. Bits 1-bit 6 of A5 bytes are used for indicating a second adjustment control command to control the next adjacent E1 signal at the position pointed by the justification position pointer to make positive or negative justification. Wherein, bit 1-bit 3 are C12A bit to indicate a second negative justification control instruction; bit0 is S12A bit is used as the second negative adjustment bit. When 3C 12When the bits are all "1", S1 is indicated2The bits are not loaded with valid information, and the second negative regulation bits are not used; when 3C 12When the bits are all "0", S1 is indicated2The bits are loaded with valid information and a negative justification is performed on the next adjacent E1 signal to the position pointed by the justification position pointer. Bit 4-bit 6 of A5 bytes is C22A bit to indicate a second positive adjustment control command corresponding to a second positive adjustment bit within the block frame. When 3C 22When the bits are all '1', indicating that the second positive adjustment bit is loaded with effective information and does not carry out corresponding positive code speed adjustment; when 3C 22When the bits are all '0', indicating that the second positive adjustment bit does not load effective information, and carrying out positive code speed adjustment on the E1 signal which is adjacent to the position pointed by the code speed adjustment position pointerAnd (6) finishing.
In addition to the overhead field and multiplexing additional field, the remaining 2400 bytes in the block frame are used as payload field for storing E1 signal data. Since a multiframe with 75-frame multiplexing is adopted, each frame in the multiframe needs to transmit 75E 1 signals, each E1 signal contains 32 time slots, each time slot occupies 1 byte, and therefore 75 × 32 ═ 2400 bytes in the payload field are occupied by the 75E 1 signals. The 75E 1 signals are arranged in the payload field in a time slot interleaving mode, namely 1 st to 75 th bytes in the payload field respectively carry the 1 st time slot of the 75E 1 signals, 76 nd to 150 th bytes respectively carry the 2 nd time slot, … … th and 2326 th to 2400 th bytes respectively carry the 32 nd time slot of the 75E 1 signals. In the payload field, the first 75 bytes (i.e., bytes 1-75) are slightly different from the other bytes in structure, and the bit structure of a single byte is schematically shown in fig. 8, and from low to high, bits 0-7 are respectively. Each bit of the 76 th-2400 th bytes of the payload field is an I bit, namely an E1 signaling bit. In bytes 1-75 of the payload field, the most significant bit7 of each byte is the positive adjustment bit S2/I, and bits 0-6 are I bits; however, only two positive justification bits are valid for each block frame corresponding to the two E1 signals for justification, and the specific positions of the valid positive justification bits are also designated by the justification position pointer. For example, the Q bit in the A3 byte is "0000000", indicating that the justification is performed on the 1 st and 2 nd E1 signals in the current blocky frame, at which time the S2/I bit in the 1 st byte in the payload field is the first positive justification bit, represented by C2 in the A4 byte1Controlling bits; the S2/I bit of byte 2 in the payload field is the second positive justification bit consisting of C2 in byte A52Controlling bits; the other E1 signals are not justified, and their corresponding S2/I bits are actually used as I bits. By analogy, the Q bit in the A3 byte is "0000001", and the S2/I bit in the 2 nd byte of the payload field of the blocky frame is the first positive justification bit, represented by C2 in the A4 byte1Controlling bits; the 3 rd byte of the payload field, the S2/I bit, is the second positive justification bit, consisting of C2 in the A5 byte2And (5) controlling bits. … …The Q bit in the A3 byte is "1001010", then the S2/I bit in the 75 th byte of the payload field of the blocky frame is the first positive justification bit, composed of C2 in the A4 byte1Controlling bits; the S2/I bit of byte 1 in the payload field is the second positive justification bit (consider the 1 st E1 signal as the next adjacent signal to the 75 th E1 signal), represented by C2 in byte A52And (5) controlling bits.
The whole block frame structure has a structure of 9 rows and 270 columns of bytes which are the same as the STM-1 frame, and can adopt the transmission mode of SDH signals to transmit the bytes in the block frame one byte from left to right and from top to bottom, transmit one row and then transmit the next row, transmit one frame and then transmit the next frame. Because 75E 1 signals are carried in the block frame, the bandwidth utilization rate reaches 98.77%, and compared with the bandwidth utilization rate 82.96% of the STM-1 frame carrying the E1 signals, the bandwidth utilization rate is greatly improved, and the method is suitable for microwave communication transmission.
The block frame structure adopted by the present invention is not limited to the encapsulation arrangement in the above embodiments, but the encapsulation arrangement of the overhead field and the multiplexing additional field is managed. For example, as long as the framing byte A1 is guaranteed to be located in the frame header of the block frame, the overhead field may be encapsulated in columns 1 to 3 of rows 1 to 9 in the block frame (as shown in FIG. 9), or the overhead field may be encapsulated in columns 1 to 27 of row 1 in the block frame (as shown in FIG. 10), and so on. The 2400 bytes of the payload field are not necessarily all used to carry the 75E 1 signals, and valid information bytes within 2400 bytes may be carried according to the requirement of the actual application.
Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.
Claims (6)
1. A transmission method of synchronous digital series signals comprises using a block frame composed of 9 rows and 270 columns of bytes to carry an E1 signal, multiplexing a plurality of block frames into a multiframe, and sending the multiframe to a transmission channel of an STM-1 rate for transmission, and is characterized in that: the block frame comprises a management overhead field, a multiplexing additional field and a net load field; wherein,
the management overhead field occupies 27 bytes in the block frame and is used for comprehensively monitoring and managing the transmission channel;
the multiplexing additional field occupies 3 bytes in the block frame and is used for indicating sequence information of the multiframe, a code rate adjusting position pointer, adjusting control information, parity check information and alarm information returned by a receiving end;
the payload field occupies the remaining 2400 bytes in the block frame and is used for carrying an E1 signal;
the byte definition in the management overhead field is the same as the byte definition in the RSOH area of the STM-1 frame, including: framing bytes A1 and A2 for frame header indication and positioning of the blocky frame; a regeneration section tracking byte J0 for ensuring the correct butt joint of the receiving end and the transmitting end; bit-interleaved parity byte B1 for bit error monitoring of the regeneration section overhead; a official transmission byte E1 for official contact of the reclaim section overhead; a user path byte F1 for transferring user-specific usage maintenance information; the data communication channel bytes D1-D3 are used for transmitting maintenance management information;
the multiplexing additional field is composed of a multiframe indication byte A3 and adjustment control bytes A4 and A5; the multiframe indication byte A3 is used for indicating a parity check type, sequence information of a multiframe and a code rate adjustment position pointer; the adjustment control byte a4 is used to indicate the first adjustment control information and the parity information of the previous multiframe; the adjustment control byte A5 is used for indicating second adjustment control information and alarm information returned by a receiving end; the parity check information of the previous multiframe and the alarm information returned by the receiving end are distributed to corresponding bytes of a plurality of block frames in the multiframe and are transmitted respectively; wherein, the parity check information of the previous multiframe is distributed to the adjustment control bytes A4 of the 1 st to 8 th block frames in the multiframe for transmission respectively; the alarm information returned by the receiving end is distributed to the adjustment control bytes A5 of the 1 st to 5 th block frames in the multiframe for transmission respectively, the adjustment control byte A5 of the 1 st block frame in the multiframe transmits MS-RDI alarm information, and the adjustment control byte A5 of the 2 nd to 5 th block frames in the multiframe transmits MS-REI alarm information.
2. The method for transmitting a synchronous digital series signal according to claim 1, wherein: the multiframe is formed by multiplexing 75 block-shaped frames.
3. The method for transmitting a synchronous digital series signal according to claim 1 or 2, wherein: the most significant bit of the multiframe indication byte a3 is used to indicate the parity type of the multiframe, and the other bits are used to indicate the sequence information and the justification location pointer of the multiframe.
4. The method for transmitting a synchronous digital series signal according to claim 1 or 2, wherein: the most significant bit of the justification control byte a4 is used to indicate parity information for a previous multiframe, the least significant bit is the first negative justification bit, and the other bits are used to indicate the first justification control command.
5. The method for transmitting a synchronous digital series signal according to claim 1 or 2, wherein: the most significant bit of the justification control byte a5 is used to indicate the alarm information returned by the receiving end, the least significant bit is the second negative justification bit, and the other bits are used to indicate the second justification control command.
6. The method for transmitting a synchronous digital series signal according to claim 1 or 2, wherein: in the first 75 bytes of the payload field, the highest bit of each byte is a positive adjustment bit, two of the positive adjustment bits are valid, and the position of the valid positive adjustment bits is specified by the justification position pointer.
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