CN101859365A - Bar code decoding chip - Google Patents
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- CN101859365A CN101859365A CN 201010181898 CN201010181898A CN101859365A CN 101859365 A CN101859365 A CN 101859365A CN 201010181898 CN201010181898 CN 201010181898 CN 201010181898 A CN201010181898 A CN 201010181898A CN 101859365 A CN101859365 A CN 101859365A
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Abstract
The invention provides a bar code decoding chip. The bar code decoding chip comprises a data memory, at least two bar code arithmetic logics and a gating logic gate, wherein the data memory is used for storing a bar code image; the at least two bar code arithmetic logics are used for performing parallel processing on the bar code image stored in the data memory; and the gating logic gate is arranged between the data memory and the at least two bar code arithmetic logics. The gating logic gate makes the at least two bar code arithmetic logics call the bar code image in the data memory sequentially. By using the method, the paralleling of an identifying process for the bar code image is realized, so that the identifying speed of the bar code image is increased.
Description
[technical field]
The present invention relates to a kind of bar code decoding chip, particularly a kind of bar code decoding chip of supporting image Parallel Processing.
[background technology]
Barcode technology is an appearance coding, printing, identification, the data acquisition and processing (DAP) emerging technology that grows up on computer technology and infotech basis.Barcode technology is because its identification is quick, accurate, reliable and low cost and other advantages, be widely used in fields such as commerce, taking care of books, storage, post and telecommunications, traffic and Industry Control, and certainly will in " Internet of Things " that rise gradually used, bring into play great function.
The bar code that is widely used at present comprises bar code and two-dimensional bar code.Bar code claims that again form by the unit by a plurality of " bars " that are arranged in parallel and " sky " for linear bar code, and bar code information is expressed by bar and empty different in width and position.Bar code is not then expressed any information just in a direction (generally being horizontal direction) expressing information in vertical direction, so information capacity and space availability ratio are lower, and promptly can't discern after bar code is damaged.
Two-dimensional bar code is made up of the chequered with black and white particular geometric figure that distributes on two-dimensional directional according to certain rules, its can be on two-dimensional directional expressing information, so information capacity and space availability ratio are lower, and have certain verifying function.Two-dimensional bar code can be divided into stack two-dimensional bar code and matrix two-dimensional barcode.The stack two-dimensional bar code is that the bar code by the multirow cutting back piles up and forms, and representational stack two-dimensional bar code comprises PDF417, Code 49, Code 16K etc.Matrix two-dimensional barcode is made up of black, the white module that is distributed in by pre-defined rule in the matrix, and representational matrix two-dimensional barcode comprises Codeone, Aztec, Date MatriX, QR sign indicating number etc.
At present, the decode procedure to bar code image substantially all is to adopt serial mode to carry out.For example, discern at the bar code image to unknown code system, bar code image especially is when discerning, generally scanning result is stored into a storage unit, then the information in the storage unit is discerned successively by the recognition methods of various different code systems.When the recognition methods of a code system did not have identification not finish, the recognition methods of all the other code systems was in the free time.Like this, just cause temporal waste, reduced the speed of decoding.
[summary of the invention]
In order to overcome the above problems, the invention provides a kind of bar code decoding chip of supporting the bar code image parallel processing, improve the recognition speed of bar code image thus.
The invention provides a kind of bar code decoding chip, this bar code decoding chip comprises: data-carrier store is used to store bar code image; At least two bar code arithmetic logics are used for the bar code image of data store memory storage is carried out parallel processing; Gating logic gate is arranged between data-carrier store and two the bar code arithmetic logics at least, makes at least two bar code arithmetic logics call bar code image in the data-carrier store successively.
According to one preferred embodiment of the present invention, at least two bar code arithmetic logics are the recognition unit corresponding to different recognition rules.
According to one preferred embodiment of the present invention, bar code decoding chip further comprises state machine, is used to control the duty of at least two bar code arithmetic logics.
According to one preferred embodiment of the present invention, state machine is further controlled the connection of gating logic gate selectivity data-carrier store and corresponding bar code arithmetic logic.
According to one preferred embodiment of the present invention, gating logic gate comprises an input port, a plurality of output port and at least one control port, the input port of gating logic gate connects the output port of data-carrier store, a plurality of output ports of gating logic gate connect the input port of corresponding bar code arithmetic logic respectively, the control port connect state machine of gating logic gate is communicated with the input port of gating logic gate and the corresponding output port of gating logic gate with selectivity under the control of state machine.
According to one preferred embodiment of the present invention, after bar code image was transferred to data-carrier store, the data-carrier store transmit status was instructed state machine.
According to one preferred embodiment of the present invention, after state machine received status command, state machine control gating logic gate selectivity was connected data-carrier store and corresponding bar code arithmetic logic, made the bar code arithmetic logic of correspondence call bar code image in the data-carrier store.
According to one preferred embodiment of the present invention, when a bar code arithmetic logic at least two bar code arithmetic logics correctly identifies bar code information, when then follow-up bar code image being discerned, state machine can be controlled a bar code arithmetic logic and preferentially call follow-up bar code image.
According to one preferred embodiment of the present invention, bar code image is the bar code image fragment that data-carrier store is stored.
According to one preferred embodiment of the present invention, each at least two bar code arithmetic logic comprises a plurality of processing units corresponding to the different identification steps of same bar-code identification rule.
By said method, realized the parallel of bar code image identifying, improved the recognition speed of bar code image thus.
[description of drawings]
Fig. 1 is the schematic block diagram of first embodiment of the invention.
Fig. 2 is the schematic block diagram of second embodiment of the invention.
Fig. 3 is the schematic block diagram of third embodiment of the invention.
Fig. 4 is the schematic block diagram of fourth embodiment of the invention.
Fig. 5 is the schematic block diagram of fifth embodiment of the invention.
Fig. 6 is the schematic block diagram of the hardware logic framework of realization the present invention first to the 5th embodiment.
Fig. 7 is the schematic block diagram of the data management system in the hardware logic framework shown in Figure 6.
Fig. 8 is the schematic block diagram of the software architecture of realization the present invention first to the 5th embodiment.
Fig. 9 is first duty of software architecture shown in Figure 8.
Figure 10 is second duty of software architecture shown in Figure 8.
[embodiment]
The present invention is described in detail below in conjunction with drawings and Examples.
As shown in Figure 1, Fig. 1 is the synoptic diagram of the bar code image parallel processing framework of first embodiment of the invention.In the first embodiment of the present invention, at least two processing units 101,102 are set in the bar-code decoder 100.Processing unit the 101, the 102nd, corresponding to the recognition unit of different code systems, promptly processing unit 101,102 can utilize the recognition rule of different code systems to carry out bar-code identification respectively.For example, processing unit 101 is the bar code recognition unit, and processing unit 102 is PDF417 bar-code identification unit.In addition, bar-code decoder 100 can also further be provided with a plurality of processing units, to correspond respectively to the bar-code identification process of other code systems, and for example Code 49 bar codes, Code 16K bar code, Supercode bar code etc.
In the first embodiment of the present invention, after bar code image was input to bar-code decoder 100, processing unit 101,102 utilized the recognition rule at different code systems that this bar code image is carried out parallel decoding respectively.For example, utilize bar code recognition rule and PDF417 bar-code identification rule simultaneously this bar code image to be discerned respectively by processing unit 101,102.If the bar code image of input is the PDF417 bar code image, then by the correct recognition result of processing unit 102 outputs.In a preferred embodiment, if processing unit 102 has been exported correct recognition result, and processing unit 101 is still being carried out identification maneuver, then stops the identification maneuver of processing unit 101.
By said method, utilize a plurality of processing units respectively with different recognition rules to the identification that walks abreast of same bar code image, improved the recognition speed of bar code image thus.
As shown in Figure 2, Fig. 2 is the synoptic diagram of the bar code image parallel processing framework of second embodiment of the invention.In the present embodiment, after camera (not shown) photographs bar code image and carries out suitable pre-service, bar code image need be transferred to the data-carrier store 201 of bar-code decoder 200.In the prior art, need are waited for after bar code image all is transferred to data-carrier store 201 and are just carried out bar-code identification.Yet, after acquiring a certain degree, the image segments of considering in the data-carrier store 201 bar code image of storage can carry out all or part of bar-code identification process, and therefore the transmission course of bar code image walks abreast with identifying and carries out in the present embodiment.
Specifically, for bar code, because bar code expressing information is not in the horizontal direction only then expressed any information in vertical direction, a horizontal bar code image segments that therefore in fact only needs to obtain certain altitude can be discerned bar code.For two-dimensional bar code, equally obtaining to carry out part bar-code identification process after the enough big or small barcode fragment, for example boundary search etc.
Therefore, in the present embodiment, in the transmission course of the data-carrier store 201 of bar-code decoder 200, judge whether the bar code image fragment of having transmitted satisfies condition for identification at bar code image.So-called condition for identification can be whether bar code image fragment that data-carrier store 201 has received reaches predetermined pixel column or/and number of columns, and can set various criterions according to different code systems.When processing unit 202 is judged bar code image fragment that data-carrier store 201 received and satisfied condition for identification, just begin the bar code image fragment that has received is discerned.In the process that the bar code image fragment that 202 pairs of processing units have received is discerned, bar code image continues to the data-carrier store transmission and forms new barcode fragment.Finish the identification of bar code image fragment when processing unit 202 after, processing unit 202 can wait for that the new bar code image fragment that is received up to data-carrier store 201 satisfies the condition of identification next time.Processing unit 202 can continue the bar code image fragment is discerned after the bar code image fragment that judgment data storer 201 receives has satisfied the condition of identification next time.
By said method, realized the parallel of bar code image transmission and bar-code identification process, improved the recognition speed of bar code image thus.
In addition, described as first embodiment, also a plurality of processing units can be set in the bar-code decoder 200 of present embodiment, these a plurality of processing units utilize respectively at the recognition rule of different code systems the image segments identification that walks abreast.
As shown in Figure 3, Fig. 3 is the synoptic diagram of the bar code image parallel processing framework of third embodiment of the invention.In the bar-code identification process, in order to guarantee to discern the multiframe bar code image to the correctness of bar code image identification.Yet in the prior art, need are waited for after the identifying of 300 pairs of these frame bar sign indicating number images of bar-code decoder is finished and just can be transmitted the next frame bar code image after image unit is transferred to bar-code decoder 300 with a frame bar sign indicating number image.
In the present embodiment, the multiframe bar code image that will take continuously of image unit (not shown) sequentially is transferred to the data-carrier store 301 of bar-code decoder 300.And, after having transmitted a frame bar sign indicating number image, discern by 302 pairs of these frame bar sign indicating number images of processing unit.When 302 pairs of these frame bar sign indicating number images of processing unit were discerned, image unit continued transmission next frame bar code image to data-carrier store 301.After the identification of 302 pairs of present frame bar code images of processing unit was finished, if the next frame bar code image has been finished the transmission to data-carrier store 301, then processing unit 302 began the next frame bar code image is discerned.After the identification of 302 pairs of present frame bar code images of processing unit is finished, if the next frame bar code image is not finished the transmission to data-carrier store 301, then processing unit 302 is waited for the transmission of next frame bar code image, until next frame bar code image end of transmission, processing unit 302 begins the next frame bar code image is discerned.
By said method, realized the parallel of bar code image transmission and bar-code identification process, improved the recognition speed of bar code image thus.
In addition, described as first embodiment, also a plurality of processing units can be set in the bar-code decoder 300 of present embodiment, these a plurality of processing units utilize respectively at the recognition rule of different code systems the bar code image identification that walks abreast.
As shown in Figure 4, Fig. 4 is the synoptic diagram of the bar code image parallel processing framework of fourth embodiment of the invention.In the fourth embodiment of the present invention, one group of at least two processing unit 401,402,403 are set in the bar-code decoder 400.Wherein, the different identification steps of each processing unit 401,402,403 corresponding same bar-code identification rule.After these at least two processing units are serially connected, can realize a complete identifying.With the bar code is example, and processing unit 401,402,403 can correspond respectively to bar code search step, code value extraction step and the error-correcting decoding step of bar code.Thus, for the two frame bar sign indicating number images that are input to bar-code decoder 400 continuously, processing unit 401 is by at first carrying out the bar code searching to the first frame bar sign indicating number image, to determine barcode position and correlation parameter.After 401 pairs first frame bar sign indicating numbers of processing unit image is handled, Search Results is input to processing unit 402 carries out the code value extraction.Processing unit 401 then further carries out the bar code searching to the second frame bar sign indicating number image.Finishing code value at 402 pairs first frame bar sign indicating numbers of processing unit image extracts, and will extract the result and be input to after processing unit 403 carries out error-correcting decoding, by processing unit 401 Search Results of the second frame bar sign indicating number image further is input to processing unit 402 and carries out code value and extract.
By the way, can realize each identification step parallel of bar code image, improve the recognition speed of bar code image thus by pipelined architecture design.
In addition, many group processing units can be set in bar-code decoder 400 equally, the processing unit that comprises a plurality of different identification steps at same bar-code identification rule in every group of processing unit, and every group of processing unit corresponds respectively to the recognition rule of different code systems, can be utilized respectively at the recognition rule of different code systems the bar code image identification that walks abreast by these many group processing units thus.
Further, fourth embodiment of the invention can combine with first to the 3rd embodiment, promptly utilizes the The pipeline design of the processing unit 401,402,403 of the 4th embodiment to realize processing unit 101,102,202,302 among first to the 3rd embodiment.At this moment, the processing unit 401,402,403 of the 4th embodiment can be used as the sub-processing unit in the processing unit 101,102,202,302 among first to the 3rd embodiment.
As shown in Figure 5, Fig. 5 is the synoptic diagram of the bar code image parallel processing framework of fifth embodiment of the invention.In the fifth embodiment of the present invention, be provided with scan module 501 and at least two border judge modules 502,503,504,505 that bar code image is scanned in the processing unit of bar-code decoder 500.Border judge module 502,503,504,505 can utilize different border judgment rules to come the bar code border that the scans border that walks abreast is judged respectively.Each border judge module 502,503,504,505 is preferably corresponding border judgment rule.
In a preferred embodiment, bar code image is the bar code image of PDF417 sign indicating number, border judge module 502 corresponding 81111113 border judgment rules, border judge module 503 corresponding 31111118 border judgment rules, border judge module 504 corresponding 71111113 border judgment rules, border judge module 505 corresponding 31111117 border judgment rules.When 501 pairs of bar code images of scan module scan, if scan module 501 scans an empty border, be that benchmark continues to scan the empty border of 8 bars forward then with this empty border, and each bar that will be therebetween or empty number of modules send to this four border judge modules 502,503,504,505, judges by this four border judge modules 502,503,504,505 are parallel whether above-mentioned sky satisfies the border judgment rule of correspondence.For example, if border judge module 503 is correctly judged bar code border, then the border of this bar code image is 31111118 borders.If this moment, other border judge module 502,504,505 still carried out the border judgement, then stop the judgement action of border judge module 502,504,505.If all judging above-mentioned sky, these four border judge modules 502,503,504,505 do not satisfy corresponding border judgment rule, then scan module 501 is searched for the empty border of next bar forward, and be that benchmark repeats above-mentioned deterministic process with this next empty border of bar, up to determining correct bar code border or scanning complete bar code image.
In addition, fifth embodiment of the invention can combine with first to fourth embodiment, is about to scan module 501 and border judge module 502,503,504,505 part as the processing unit of the foregoing description.
Fig. 6 is the schematic block diagram of the hardware logic framework of realization the present invention first to the 5th embodiment.In the present embodiment, above-mentioned bar-code decoder can all be realized by hardware logic, and be integrated in the integrated chip.This integrating bar code decoding chip comprises data-carrier store 603, master control logic module 602, registers group 605, external interface 606 and at least one bar code arithmetic logic 601.Registers group 605 is with data-carrier store 603, master control logic module 602 and bar code arithmetic logic 601 and external isolation.Wherein, bar code arithmetic logic 601 can be corresponding to the processing unit among the present invention first to fourth embodiment 101,102,202,302,401,402,403, or scan module among the 5th embodiment 501 and border judge module 502,503,504,505.Further image sensing array 604 and exposure control module 607 in this integrating bar code decoding chip, exposure control module 607 is passed through I
2C bus control chart is as sensor array 604, with the duty of control chart as sensor array 604.In addition, the monochrome information of image sensing array 604 can be passed to exposure control module 607, exposure control module 607 can be placed into registers group 605 with corresponding steering logic according to the monochrome information of being obtained, master control logic module 602 is obtained this steering logic from registers group 605, and according to the work of this steering logic control bar code arithmetic logic 601, as opening or close its duty.
Master control logic module 602 has corresponding control logic corresponding to required state of a control, can choose required state of a control by triggering the switch that is electrically connected with master control logic module 602, as open bar code arithmetic logic 601, obtain bar code image from data-carrier store 603, and transmit it to bar code arithmetic logic 601 or the like.In addition, master control logic module 602 also can provide data transmission channel, as the bar code image of storage in the data-carrier store 603 can being transferred to bar code arithmetic logic 601 by master control logic module 602, and the duty of control bar code arithmetic logic 601.This master control logic module 602 does not possess calculation function, but can trigger corresponding event according to certain condition, specifically can utilize known state machine to realize.Various calculating processes at bar code image are realized by the bar code arithmetic logic fully, and master control logic module or state machine 602 are coordinated control action.
As shown in Figure 7, Fig. 7 is the specific embodiment of data management system in the hardware logic framework shown in Figure 6.In the present embodiment, data-carrier store 701 is used to store bar code image or image segments, bar code arithmetic logic 705,706 and 707 then can correspond respectively to various processing units or the module among first embodiment of the invention to the five embodiment, and bar code arithmetic logic 705,706 and 707 is used for the bar code image of data storer 701 stored or image segments are carried out parallel processing.For example, in the present embodiment, what data-carrier store 701 was stored is the bar code image, and bar code arithmetic logic 705,706 and 707 then is the recognition unit corresponding to different bar code recognition rules.In the present embodiment, gating logic gate 703 is arranged between data-carrier store 701 and bar code arithmetic logic 705,706 and 707, and under the control of state machine (master control logic module) 702, make bar code arithmetic logic 705,706 and 707 call bar code image or the image segments in the data-carrier store 701 successively, promptly gating logic gate 703 can selectivity be communicated with data-carrier store 701 and corresponding bar code arithmetic logic 705,706 and 707 under the control of state machine 702.
Specifically, gating logic gate 703 comprises an input port, a plurality of output port and at least one control port.The input port of gating logic gate 703 is connected with the output port of data-carrier store 701, and the output port of gating logic gate 703 is connected with the input port of bar code arithmetic logic 705,706 and 707 respectively.The control port of gating logic gate 703 is connected with state machine 702, and selectivity is communicated with the input port and corresponding output port of gating logic gate 703 under the control of the different steering orders of state machine 702 output, make bar code image or the image segments imported via the input port of gating logic gate 703 be delivered to the output port of corresponding gating logic gate 703, and then output to corresponding bar code arithmetic logic 705,706 and 707.Gating logic gate 703 can be realized by existing various logic gates according to actual needs.
After bar code image or the image segments that satisfies condition for identification were transferred to data-carrier store 701, data-carrier store 701 can send these states to state machine 702.After state machine 702 is received this state, can control bar code arithmetic logic 705 and go to call bar code image or image segments in the data-carrier store 701.At this moment, state machine 702 can control gating logic gate 703 be connected data-carrier stores 701 and bar code arithmetic logics 705, makes bar code arithmetic logic 705 call bar code image or image segments in the data-carrier store 701.After bar code arithmetic logic 705 calls finish this bar code image or image segments, begin this bar code image or image segments are discerned or handled.At this moment, state machine 702 control gating logic gate 703 are communicated with data-carrier store 701 and bar code arithmetic logic 706, and control bar code image or image segments that bar code arithmetic logic 706 calls in the data-carrier store 701.Because time of discerning is compared the time of calling bar code image or image segments and will grow a lot, so bar code arithmetic logic 705 and bar code arithmetic logic 706 walk abreast to this bar code image or image segments simultaneously and discern or processing.After bar code arithmetic logic 706 had called bar code image or image segments, 702 may command bar codes of state machine arithmetic logic 707 continued to call this bar code image or image segments.
If one in the bar code arithmetic logic 705,706 and 707 is correctly identified bar code information, then stop identification maneuver by state machine 702 other bar code arithmetic logics of control.In the process of identification, if continue to data-carrier store 701 follow-up bar code image of transmission or image segments, then after 705,706 and 707 pairs of last bar code images of bar code arithmetic logic or image segments identification or disposing, further call follow-up bar code image or the image segments that receives in the data-carrier store 701 by state machine 702 control bar code arithmetic logics 705,706 and 707 by gating logic gate 703, discern or handle.
At preferred embodiment, if the bar code arithmetic logic in the bar code arithmetic logic 705,706 and 707 correctly identifies bar code information in the identification of bar code image last time, when then follow-up bar code image being discerned, state machine 702 can preferentially call bar code image by this bar code arithmetic logic of control.
As shown in Figure 8, Fig. 8 is a synoptic diagram of realizing the software architecture of the present invention first to the 5th embodiment.In the present embodiment, bar-code decoder 800 comprises at least two the processor core 801-804 and program storages 810 that can call the nonidentity operation program.The a plurality of operation program 811-817 of program storage 810 storages.Each operation program 811-817 can be corresponding to the concrete operation process of scan module 501 among processing unit among the present invention first to fourth embodiment 101,102,202,302,401,402,403 or the 5th embodiment and border judge module 502,503,504,505.Each processor core 801-804 can realize the various recognition units described among the present invention first to the 5th embodiment and the corresponding function of module by calling above-mentioned operation program 811-817.
With first embodiment is example, and operation program 811-817 corresponds respectively to the recognizer of different code systems.When bar code image was input to this bar-code decoder 800, processor core 801-804 called different operation program 811-817 respectively, with the recognition rule that utilizes different code systems this bar code image was carried out bar-code identification.In a preferred embodiment, the quantity of the operation program 811-817 that stored of program storage 810 is greater than the quantity of processor core 801-804.Thus, after one of them processor core executes corresponding processing procedure, can continue not invoked operation program in the calling program storer 810, until having called all operation programs or having obtained corresponding result.
Specifically, be example with first embodiment, comprise four processor core 801-804 in the bar-code decoder of present embodiment, and program storage 810 stores seven operation program 811-817.When bar code image was discerned, processor core 801-804 four nonidentity operation program 811-814 in the calling program storer 810 respectively discerned simultaneously to bar code image.As shown in Figure 9, processor core 801 calls operation program 811, and processor core 802 calls operation program 812, and processor core 803 calls operation program 813, and processor core 804 calls operation program 814.As shown in figure 10, when utilizing operation program 811, processor core 801 finishes identification to bar code image, but do not draw correct bar code image, but other processor cores 802-804 is still when discerning bar code image, 801 of processor cores continue to call 815 pairs of bar code images of operation program and continue identification, until there being a processor core 801-804 to identify correct bar code information, or all operation program 811-817 all were called, unidentified when going out correct bar code information, the end of identification of 800 pairs of bar code images of bar-code decoder.If this is during to the identification of bar code image, processor core 803 calls operation program 816 and identifies correct bar code information, when then discerned follow-up bar code image next time, processor core 803 preferentially called operation program 816 and comes follow-up bar code image is discerned.
By above-mentioned framework, can fully realize Resource allocation and smoothing according to the processing progress of handling core, further accelerate the travelling speed of bar code image parallel processing framework.
In the above-described embodiments, only the present invention has been carried out exemplary description, but those skilled in the art can carry out various modifications to the present invention after reading present patent application under the situation that does not break away from the spirit and scope of the present invention.
Claims (10)
1. bar code decoding chip, it is characterized in that: described bar code decoding chip comprises:
Data-carrier store is used to store bar code image;
At least two bar code arithmetic logics are used for the described bar code image of described data-carrier store stored is carried out parallel processing;
Gating logic gate is arranged between described data-carrier store and described two the bar code arithmetic logics at least, makes described at least two bar code arithmetic logics call described bar code image in the described data-carrier store successively.
2. bar code decoding chip according to claim 1 is characterized in that: described at least two bar code arithmetic logics are the recognition unit corresponding to different recognition rules.
3. bar code decoding chip according to claim 1 is characterized in that: described bar code decoding chip further comprises state machine, is used to control the duty of described at least two bar code arithmetic logics.
4. bar code decoding chip according to claim 3 is characterized in that: the described state machine further described gating logic gate selectivity of control is communicated with described data-carrier store and corresponding described bar code arithmetic logic.
5. bar code decoding chip according to claim 4, it is characterized in that: described gating logic gate comprises an input port, a plurality of output ports and at least one control port, the input port of described gating logic gate connects the output port of described data-carrier store, a plurality of output ports of described gating logic gate connect the input port of corresponding described bar code arithmetic logic respectively, the control port of described gating logic gate connects described state machine, is communicated with the input port of described gating logic gate and the corresponding output port of described gating logic gate with selectivity under the control of described state machine.
6. bar code decoding chip according to claim 5 is characterized in that: after described bar code image was transferred to described data-carrier store, described data-carrier store transmit status was instructed described state machine.
7. bar code decoding chip according to claim 6, it is characterized in that: after described state machine receives described status command, described state machine is controlled described gating logic gate selectivity and is connected described data-carrier store and corresponding described bar code arithmetic logic, makes corresponding described bar code arithmetic logic call described bar code image in the described data-carrier store.
8. bar code decoding chip according to claim 7, it is characterized in that: when a bar code arithmetic logic in described at least two bar code arithmetic logics correctly identifies bar code information, when then follow-up bar code image being discerned, described state machine can be controlled a described bar code arithmetic logic and preferentially call described follow-up bar code image.
9. bar code decoding chip according to claim 1 is characterized in that: described bar code image is the bar code image fragment that described data-carrier store is stored.
10. bar code decoding chip according to claim 1 is characterized in that: each described at least two bar code arithmetic logic comprises a plurality of processing units corresponding to the different identification steps of same bar-code identification rule.
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Cited By (3)
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| CN104463073A (en) * | 2014-12-25 | 2015-03-25 | 福建新大陆电脑股份有限公司 | Barcode decoding chip with bus interface PS2 |
| CN104484692A (en) * | 2014-12-25 | 2015-04-01 | 福建新大陆电脑股份有限公司 | Barcode decoding device provided with PS2 bus interface |
| WO2017219441A1 (en) * | 2016-06-22 | 2017-12-28 | 福建联迪商用设备有限公司 | Method and system for multi-thread decoding based on multi-core mpu |
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| CN104463073A (en) * | 2014-12-25 | 2015-03-25 | 福建新大陆电脑股份有限公司 | Barcode decoding chip with bus interface PS2 |
| CN104484692A (en) * | 2014-12-25 | 2015-04-01 | 福建新大陆电脑股份有限公司 | Barcode decoding device provided with PS2 bus interface |
| CN104463073B (en) * | 2014-12-25 | 2018-05-08 | 福建新大陆电脑股份有限公司 | A kind of bar code decoding chip of band PS2 bus interface |
| CN104484692B (en) * | 2014-12-25 | 2018-10-23 | 福建新大陆电脑股份有限公司 | A kind of bar code decoding device of band PS2 bus interface |
| WO2017219441A1 (en) * | 2016-06-22 | 2017-12-28 | 福建联迪商用设备有限公司 | Method and system for multi-thread decoding based on multi-core mpu |
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