CN101853315B - The selection, placement, configuration and programming tool of simulation patch - Google Patents

Abstract

The invention discloses a kind of simulation patch selection, placement, configuration and programming (ATSPCP) instrument, transmit power management characteristic query by network.Inquiry web displaying includes the target property of PMIC to user, inquiry content.After reception user is to the response done by inquiry, instrument selection is a series of has predefined physical arrangement power management.Every piece of patch comprises bus portion and for storing configuration information storage organization.When patch is combined in many patchs power management integrated circuit, bus portion connects formation STD bus, and all signals are all suitable for this STD bus.The physical layout data of ATSPCP tool comprehensively every piece of patch forms the physical layout data of comprehensive entirety many patchs power management integrated circuit.

Description

The selection, placement, configuration and programming tool of simulation patch

Technical field

The present invention relates to the integrated circuit of programmable power supply management domain, more specifically, espespecially select power supply pipe Reason integrated circuit patch, places and controls patch and form required power management integrated circuit, configures integrated circuit And (or) program this integrated circuit and make it meet customer requirement.

Background technology

Fig. 1 is the schematic diagram of the existing system 1 comprising Analogous Integrated Electronic Circuits 2 and micro-control integrated circuit 3, its In, Analogous Integrated Electronic Circuits 2 is also sometimes referred to as Power Management Unit or PMU.Wish in relatively short period of time Design and produce meet user require PMU be the most urgent needs.Generally, the requirement of client can Can be to need PMU2 to include some different types of analog circuits.Such as, Analogous Integrated Electronic Circuits can be tool There is the integrated circuit silicon chip of intellectual property protection, such as, be that Hsin-chu Zhiyuan Technology Co., Ltd sets The silicon of meter.

Each Analogous Integrated Electronic Circuits has irregularly shaped, arranges to be stacked together each other through design, Form structure as shown in Figure 1.Partial simulation integrated circuit may be had various configurations mode.Such as, one The individual Analogous Integrated Electronic Circuits as manostat, it may be configured to serve as exporting an alternative voltage, it is possible to It is configured to the adjustable pressure regulator of threshold.Different analog circuits in PMU2 all may be so designed, If PMU2 configures in one way, then the several analog circuit of its certain comprised is the most corresponding and certain several input is defeated Go out (I/O) end to be connected, and if PMU2 configures in another way, then its another several simulations comprised Circuit is connected with another several input and output (I/O) end the most accordingly.Each analog circuit in PMU2 can Can be so configured so as itself or in running order or be in off position.Therefore, various different simulations Integrated circuit, such as PMU2, the mode of its configuration is the most.

But, each PMU is often customization product, and the specific design of its analog circuit comprised is subject to To limiting.Owing to each analog circuit is in irregular shape and has various configurations mode, for a special-purpose PMU, carry out Function Extension, need to spend considerable engineering design effort.Such as, a client can PMU can be needed to have 4 tunnel outputs, the different controlled voltage of each road output, and therefore, first design needs full This requirement of foot.Second client may need PMU to have 8 tunnel outputs, and each road also exports different controlled electricity Pressure.In order to meet second extra needs of client, first design basis needs be further added by pressure regulation electricity Road.Even if using existing Analog Circuit Design technology and SIP module, it is still necessary to for satisfied second demand Carrying out individually designed, the wiring of its physical layer must update, and new line layer needs design, and memory body needs Amendment is to address the regulating circuit newly increased.

Equally, in order to obtain similar function, replace another type of mould with a type of analog circuit Intend circuit, it is also desirable to spend considerable engineering design effort.Such as, in order to replace, there is linear voltage regulation merit The pressure regulator of energy, designer needs to redefine detailed integrated circuit sketch, line route and figure layer and compiles Number, in order to the actual layout data for IC manufacturing can be generated.

Above many restrictions directly result in the design cost of the PMU solution of user's Custom Prosthesis and are taken Between increase.Although, each PMU may be designed with very many functions, but still cannot meet some visitors The special requirement at family, and this multi-functional PMU is expensive, and volume is big, at the final products formed In, its some circuit comprised are likely to not be utilized.

Summary of the invention

The technical problem to be solved is to provide a kind of selection, placement, configuration and programming simulating patch Instrument.

In order to solve above technical problem, the technical scheme is that

A kind of many patchs power management integrated circuit (MTPMIC) includes the electricity able to programme of multiple regular shape Source control integrated circuit (PMIC) patch.These PMIC tile placed adjacent able to programme, each able to programme It is grid-like that PMIC tile is all fixed in the length of side, so can simplify patch in original integrated circuit diagram Placement, and the physical cross in physical layout can be simplified.Each PMIC tile able to programme always includes one Line part, is made up of the wire that can transmit digital signal, analogue signal and power supply signal, each bus portion Divide and also include that connecting line, the connecting line of the patch of each placed adjacent are sequentially connected, be consequently formed a STD bus. It is mutual that this STD bus realizes each PMIC tile in many patchs power management integrated circuit (MTPMIC) Between electrical connection and control connect.Additionally, each PMIC tile comprises the writeable depositor of memory structures, Those are for configuring the configuration information of PMIC tile functional circuit by the writeable configuration register of PMIC certainly Move and be stored in PMIC tile.In MTPMIC, these configuration register all can be by STD bus by solely Vertical addressing and write information.

In terms of a novelty, simulation patch selection, placement, configuration and programming (ATSPCP) instrument provides a net Page, this webpage is sent to a long-distance user by network (such as the Internet), and this webpage contains power management The problem of characteristic.This long-distance user has replied this problem by web browser.The return information quilt of this user Sending back ATSPCP tool, according to the return information of the user received, ATSPCP tool selectes a fixed number The PMIC tile of amount.By actual power management integrated circuit and the most suitable configuration of each patch of selecting Information combines, and these chosen PMIC tile disclosure satisfy that the requirement in user's return information.Once select Fixed PMIC tile is determined by user, the physical layout data of the comprehensive each selected patch of this ATSPCP tool, Form the comprehensive physical topology data for whole MTPMIC.Owing to need not custom design wiring layer or depositing Storage characteristic realizes the function of MTPMIC, and this ATSPCP can be automatically performed this synthetic operation.Each Selected patch all comprises memorizer to store required tile configuration information, additionally, at PMIC tile successively The STD bus formed after placed adjacent can provide the transmission of all desired signals.

In terms of another novelty, ATSPCP tool connected to the network will be put relative to the second PMIC tile The pattern of the first position relationship of the first PMIC tile put is sent to user by network, and this pattern is permissible It is one represent the figure on PMIC tile border with rectangle or comprise such a rectangle.This ATSPCP work Tool receives user's feedback information for this first pattern by the Internet, and this feedback information indicates a desire to mobile This second PMIC tile, relative to the position of the first PMIC tile, makes two patchs abut one another.As to this The response of field feedback for the first time, ATSPCP tool sends the second pattern by the Internet, and it contains this First patch is relative to the second position relationship of this second patch.User has browsed two spellings being in new position Sheet, sends back and expresses the second time feedback information satisfied to two patch the second position relationships.ATSPCP tool After receiving second time feedback information, generate and include first patch the second position relative to the second patch Physical layout data, to form MTPMIC.

Owing to the shape of every piece of PMIC tile is regular, the placement from each other of every piece of PMIC tile, row Cloth and rearrangement are the easiest, and the long-distance user by less Analog Circuit Design uses ATSPCP tool Also the placement work of patch can be completed.User can manipulate the PMIC tile simplification figure provided by web browser Sample, these simplify pattern and do not comprise the layout information of every piece of concrete patch, and these layout information are also It is not presented on the computer of user.The design of patch need not the customization signal path layer of complexity and connects respectively Patch, mutually adjoins placement and can form STD bus between patch.Therefore, once patch is placed shape by user The reply of formula is satisfied with, and ATSPCP tool just can generate the physical layout number being suitable to manufacture integrated circuit According to, meet user's needs.

In terms of the 3rd novelty, ATSPCP tool sends power management control characteristic inquiry letter by network Cease and receive user's return information to this inquiry message.According to described return information, ATSPCP tool generates For configuring the configuration information of PMIC tile, it is stored in the configuration register of available PMIC tile.Spell Sheet configuration information can be loaded in the writeable depositor of independence in any optional PMIC tile, is used for controlling Patch operation characteristic.Such as, an independent PMIC tile contains configurable analog circuit, such as can configure Battery charger, this battery charger can be chosen to be configured with the modulated electricity of adjustable output Pressure, adjustable output limited current, and there is optional enable control.Configuration information can be loaded into any In the writeable depositor of arbitrary independence in alternative PMIC tile.

Each PMIC tile comprises the writeable configuration register of their own, is stored in the writeable configuration of PMIC tile The configuration information of depositor controls the operation characteristic of patch functional circuit.Each configuration information is stored in every piece In PMIC tile, by this storage organization, can be for each new MTPMIC custom design collection Chinese style storage organization, MTPMIC can hold packed very much.Also, it is not necessary to mature deliberation tile configuration information Adaptation to this structure, for every piece of patch, its function is by the configuration being stored in each writeable configuration register Information bit institute is preset.Therefore, power management control characteristic can be inquired by ATSPCP tool based on user The return information of information, generates in a new MTPMIC design for every piece of PMIC tile fast automaticly Configuration information.

In terms of the 4th novelty, ATSPCP tool sends power management control characteristic inquiry letter by network Cease and receive user's echo message to this inquiry message.According to echo message, ATSPCP tool is to composition The PMIC tile of MTPMIC is programmed, and the storage organization of every piece of PMIC tile can be independent by STD bus Addressing, this STD bus is put together the MTPMIC needed for being formed by each patch being selected.And, It is preset and is presented in for storing the memorizer of the configuration information of every piece of patch in every piece of independent patch.Therefore And, ATSPCP tool according to the echo message of power management control characteristic inquiry message can be fast automatic right Patch in MTPMIC is programmed.Configuration information is passed in each is programmed that patch by STD bus Defeated.This programming can be carried out in the computer performing ATSPCP tool, it is also possible to carries out in remote user end.

In terms of the 5th novelty, utilize STD bus by tile configuration information from the first PMIC tile via Second PMIC tile is transferred to the 3rd PMIC tile, can complete to simulate the configuration of patch integrated circuit.Three In block patch each piece is all the ingredient of integrated circuit, mutually adjoins placement due to PMIC tile and connects Defining STD bus, the data/address bus of adjacent patch and control signal wire arrange also in a suitable manner It is connected with each other so that every piece of PMIC tile can be electrically connected to other PMIC tile effectively, without Complicated customization signal path layer carrys out boot configuration information and is transferred to another patch from a patch.No matter send and The PMIC tile relative physical location of reception information how, by using data/address bus and the control of STD bus How line, configuration information can be written into takes office in the PMIC tile chosen in arbitrary selected depositor. Therefore, tile configuration information can pass through any number of middle PMIC tile, by a PMIC tile transmission To another PMIC tile.Relative to more traditional IC design and layout techniques, described modularity is spelled Chip architecture and design tool reduce the lsi development time, use the user of this technology can be shorter In time, design offer meet potential user and set the Custom Prosthesis integrated circuit of specification, should so that use The user of structure and ATSPCP tool obtains design order.

More embodiment and beneficial effect will illustrate in detailed description of the invention below.Present invention is not Being intended to limit the present invention, protection scope of the present invention is defined by the claims.

Accompanying drawing explanation

These are used for illustrating the detailed description of the invention of the present invention with the accompanying drawing of digitized representation element.

Fig. 1 (prior art) is the schematic diagram of existing power supply administrative unit.

The power management integrated circuit that Fig. 2 is made up of novel power management integrated circuit (PMIC) patch Schematic diagram.The edge of PMIC tile meets lay out grid.The border of PMIC tile and domain grid Being consistent, PMIC tile includes predefined storage organization and bus portion, when patch is mutual When adjoining placement, storage organization and bus portion can be automatically connected to form STD bus.

Fig. 3 is some possible schematic shapes of PMIC tile.

Fig. 4 is the chart of the composition details of the bus portion about all kinds of PMIC tile forming standardized bus Explanation.

Fig. 5 be new simulation patch selection, arrange, configure and edit (ATSPCP) instrument operation simplify Flow chart.After client claims, select, install, configure and arrange PMIC tile to meet client Requirement.

Fig. 6 is the chart explanation in terms of a novelty of ATSPCP system and pattern.

Fig. 7 A-7C is inquiry input source-information, power supply output demand information, the power supply of control I/O demand The chart explanation of characteristics of management inquiry, and corresponding with the novelty aspect involved by chart 6.

Fig. 8 is that the integrated circuit patch being supplied to client for the novelty aspect involved by chart 6 selects Chart explanation.

Fig. 9 is that the figure of the patch being selected for the novelty aspect involved by chart 6 represents The chart explanation of (graphical representations).

Figure 10 is that the chart of the many patchs integrated circuit formed for the novelty aspect involved by chart 6 is said Bright.Many patchs integrated circuit is represented (graphical by the adjacent figure of the patch through selecting Representations) constitute.

Figure 11 A-11B is to meet the requirement of chart 6 and available device and through the device selected respectively Chart explanation.

Figure 12 is the chart explanation of the suggestion meeting the merging that chart 6 requires.Integrate and relate to the integrated of many patchs Circuit and external devices.

Figure 13 A-13B is to install and operate the chart of the mode of PMIC tile according to second novelty aspect Explanation.

Figure 14 is the chart explanation of record PMIC tile Collator Mode.

Figure 15 is the webpage schematic diagram comprising an arrangement being recorded (recorded arrangement). The arrangement being recorded includes the parts integrated circuit of patch more than and an outside, discrete.

Figure 16 is the chart explanation of the printed circuit board (PCB) performance of a circuit that disclosure satisfy that customer demand. Performance is the arrangement (recorded arrangement) being recorded based on chart 15.

Figure 17 is the chart explanation of the comprehensive description that the explanation of independent patch is combined to a MTPMIC, Wherein MTPMIC includes independent patch.

Figure 18 is the chart explanation of the method for the tile configuration information produced according to the 3rd new novelty aspect.

Figure 19 A-19B is the chart explanation of demand for control information and tile configuration information respectively.

Chart 20 is the chart explanation of configuration PMIC tile method, and wherein PMIC tile is the one of MTPMIC Part.

Figure 21 is to enter two patchs of MTPMIC in two different ways according to the 4th novelty aspect The chart explanation of row design.

Figure 22 is the detailed figures explanation that two patchs of configuration share identical bus-type wire and signalling channel, According to the 5th novelty aspect, this signalling channel be for by a tile configuration information from first spelling Sheet is sent to the 3rd patch via second patch.

Figure 23 is to seek the opinion of the outline flowchart that client needs, designs the MTPMIC method to meet customer need.

Figure 24 is the novelty aspect according to chart 6 and selects the outline flowchart of PMIC tile method.

Figure 25 is to handle the picture specification of the first PMIC tile according to the second PMIC tile and produce for MTPMIC The outline flowchart of the method for raw physical layout data, wherein MTPMIC include with chart 13 new First and second PMIC tile that newness aspect is consistent.

Figure 26 is the outline flowchart of picture specification method controlling the first patch, this first patch be about with The second patch that the novelty aspect of chart 13 is consistent.

Figure 27 is the novelty aspect according to chart 18 and produces the outline flowchart of tile configuration information method.

Figure 28 be the novelty aspect phase according to chart 21 and by the way of two kinds different one type of editor The outline flowchart of two MTPMIC element method.

Figure 29 is the novelty aspect phase according to chart 21 and edits the outline flowchart of PMIC tile method.

Figure 30 determines that a PMIC the most satisfactory and sends the product information of the most satisfactory PMIC Outline flowchart.

Figure 31 is the novelty aspect according to chart 22 and exchanges the outline flowchart of tile configuration information method.

Detailed description of the invention

Below in conjunction with the accompanying drawings embodiments of the invention are done and specifically elaborate.

Fig. 2 is the schematic diagram of system 300, system 300 comprise power management integrated circuit (PMIC) 301, Microcontroller integrated circuit 302 and bus 303.Simulation patch selection in this patent document/place/configuration/ Programming (ATSPCP) instrument can be conveniently used in many integrated circuits, existing with power management integrated circuit (PMIC) illustrate as a example by.It should be noted that PMIC is only to use ATSPCP tool to carry out One in the many integrated circuits designing, select and (or) configuring.Other integrated circuits include light regime Unit (LMU), electricity processing unit (EPU) and Power Management Unit (PMU) etc..But, the most also Its applicable integrated circuit kind non exhaustive.

PMIC301 includes optional regular shape integrated circuit patch 305-312, mutually adjoins placement.Every piece The rectangular grid palisade that patch is all fixing in the length of side, can simplify patch placement in original integrated circuit diagram And the physical cross in physical layout can be simplified.Patch 305,306 and 309 is step-down controller patch, tool There is voltage dropping power supply management function；Patch 308 and 310 is low dropout regulator, has voltage-regulation function； Patch 311 is input and output (I/O) patch, has signaling interface function, connects PMIC301 and its envelope Dress；Patch 307 refers to battery charger, has supply voltage function；Patch 312 refers to " main spelling Sheet ", main patch includes Bus Interface Unit and a storage organization depositor 323, is used for configuring in main patch Functional circuit.Such as, the functional circuit of main patch can include reference voltage maker and clock.Clock Signal and the signal generated by reference voltage maker are transferred to other patchs.Other integrated circuit patchs Example also includes having the boost converter patch of boost function, have the electric charge pump patch of power supply function, pipe Manage battery and power source path management patch, the Switching Power Supply control of control switched-mode power supply that many equipment is powered Device patch, illumination supervision module patch that DC lighting equipment powers is provided, realizes analog and D/A switch Data are changed patch, microcontroller and microprocessor patch, are had the interface patch of usb function, with And there is the monitoring patch of watchdog function (variable such as monitoring voltage, temperature).Due to every piece of patch all in The rectangular grid palisade (such as 0.5 millimeter) that the length of side is fixing, in integrated circuit diagram, these patchs can be by Placed adjacent simply.PMIC domain shown in Fig. 2 elaborates to be placed in the letter of the patch on a traditional grid Single layout.

How more detailed spliced structure information and patch are connected with each other, are in communication with each other, and how to be programmed Deng, refer to (1) Application No. 11/978,458, it is entitled that " the Micropump function in step-down controller is divided Join ", the date is on October 29th, 2007, applies for the U.S. Patent application of artificial Huynh etc.；(2) Patent No. 11/544,876, entitled " integrated circuit modules layout method and system ", the date is On October 7th, 2006, apply for the United States Patent (USP) of artificial Huynh etc.；(3) Provisional Application No. is 60/850,359, Entitled " for the eeprom structure of the monolayer polycrystalline that bit writes/rewrites ", the date is 2006 10 The U.S. Patent application on the moon 7；(4) Application No. 11/888,441, entitled " bit can be carried out The storage organization of write/rewriting ", the date is on July 31st, 2007, applies for the U.S. of artificial Grant etc. Patent application；(5) Application No. 11/978,319, the entitled " Analogous Integrated Electronic Circuits of modularized design Interconnection layer ", the date is on October 29th, 2007, applies for the U.S. Patent application of artificial Huynh etc.； (6) Application No. 11/452,713, entitled " scalable programmable power management integrated circuit system ", Date is on June 13rd, 2006, applies for the U.S. Patent application of artificial Huynh；(7) Provisional Application No. Being 60/691,721, entitled " scalable programmable power management integrated circuit system ", the date is 2005 In on June 16, in, apply for the U.S. Patent application of artificial Huynh；(8) Application No. 11/544,876, Date is the U.S. Patent application on October 7th, 2006.(theme of above-mentioned patent document is attached to the application Middle as reference.)

Fig. 3 is for illustrating possible patch common shape.Patch 370-374 is only simple illustration example, It it is not institute's likely situation of patch shape.Such as, patch 370 is the example of a tetragon patch； Patch 373 is the example of a hexagon patch；Patch 374 is the example of an octagon patch.Typically For, the polygon being shaped as a closing of every piece of patch, each drift angle of closed polygon is positioned at fixed edge On the lattice point of long square-grid or be located substantially near the lattice point of square-grid of the fixing length of side.It addition, close many The each edge of limit shape is positioned on the gridline on the square-grid of the fixing length of side, or is located substantially near gridline.Press According to above-mentioned geometrical rule, can create diversified patch shape, many of which can be encapsulated in In MTPMIC.

Returning to Fig. 2, patch 305-312 comprises storage organization depositor 316-323.Simple signal at Fig. 2 In, every piece of patch includes that the storage organization depositor of 8, these register reference numbering are respectively 316-323.But, each storage organization can include more or less figure place.Each storage organization can To be made up of volatibility position, it is possible to be made up of non-volatile bits.More detailed suitable storage organization information, Being referred to number of patent application is 11/888,441, and the date is the U.S. Patent application on July 31st, 2007. (theme of above-mentioned patent document is attached to herein as reference.)

Every piece of patch each comprises configuration register, and some features of configuration register are disclosed, such as The function of each optional place value of bit architecture, address and each depositor.As a part of PMIC301, Every piece of patch needs not rely on external memory storage and runs, it is not necessary to design a kind of Custom Prosthesis collection for PMIC301 Chinese style storage organization.Therefore, it can need not redesign for store configuration information storage organization and In the case of address structure, design is modified.One predefined storage organization and address are present in often In block patch.Once defining the specific function of patch in PMIC, depositor can automatically generate to comprise and deposit Device address and the tile configuration information of position configuration information.Between patch 305-312 mutual by STD bus 350 Connect.Patch 370-374 shown in Fig. 3 also includes respective bus portion 375-379, and each bus is along envelope Enclosed polygon patch at least place or near closed polygon patch at least while.

Fig. 4 illustrate when buck tile 305, buck tile 306, main patch 313, LDO tile 308, LDO tile 310 and buck tile 310 in integrated circuit diagram during placed adjacent, STD bus 350 Formed.LDO tile 308 includes a bus portion 352, and it includes many bus-type wires 354 and connects Line 353.Connecting line 353 comprises multiple conducting wires 355.When LDO tile 308 is adjacent to main patch 312, Connect wire 355 to be led by the corresponding bus-type of the bus-type wire 354 of LDO tile 308 with main patch 312 Line 356 is connected.Similarly, each bus-type wire of the bus portion 352 of LDO tile 308 is logical Cross connecting line 353 to be connected with each corresponding bus-type wire of the bus portion 357 of main patch 312.Respectively After patch placed adjacent in integrated circuits, STD bus 350 just defines.

In one embodiment, only by use the wire that comprised of STD bus construct one functional MTPMIC, it does not add any signal path layer.Due to patch placed adjacent regulation in integrated circuit The structure of STD bus, and the physical layout data of every piece of patch predetermines, and is suitable to what IC manufactured The physical layout data of functional MTPMIC can by ATSPCP tool fast automatic place it in patch Rear generation.

STD bus can include special signal wire, transmission signal conductor, control signal wire and power supply ground Line wire.Such as, STD bus can include 70 different wires, is used for transmitting some through careful Control signal, transmission signal and the power supply signal considered, these signals include (but being not limited only to this): (a) Special, fixed-purpose signal, such as reference voltage source and voltage source, reference current source and current source, agitator Signal, clock sync signal, for programming and transmission data and address signal, analog or digital fine setting letter Number, various earth signal: include simulation ground, digitally with signal ground, various power supply signal: include simulate core Heart power signal, digital core power supply signal, I/O mouth power supply signal, programming non-volatile memory power supply Signal；B () non-dedicated analog/digital signal, can be by one or more patchs company between sheet and sheet Use in connecing, control and (or) transmitting.In certain embodiments, at least one piece of patch is based on being stored in it At least part of information of memorizer configures and controls its electric characteristics；In other embodiments of the invention, At least one piece of patch is configured to generate reference voltage or clock signal, in order to be supplied to other patchs.

Fig. 5 is the operational flowchart of selection, placement, configuration and programming (ATSPCP) instrument 46 of simulation patch. Operating procedure includes that the patch selecting power management, placement to choose treats the integrated of construction in one In circuit, generate the comprehensive parameters of the integrated circuit treating construction, generation tile configuration information for treating construction Selected patch is programmed by integrated circuit and patch in the actual integrated circuit treating construction is carried out Programming.This process starts from soliciting input source information (step 10), solicits power supply output and require information (step Rapid 11) and solicit control I/O require information (step 12) (optional).The information solicited is used for Assessment, in order to determine whether its available part meets or substantially meet the information that step 10-12 is solicited Included in requirement (step 13).If judged result is at least some of available, then in step 13 Generate the option (step 14) of available part.Determine whether each option meets step by assessment The requirement included in information that 10-12 solicits, and determine whether the resource information (step also needing to increase 15).If needing to increase, then defining these needs the resource information increased so that itself and available part can Meet the requirement (step 16) comprised in the information that step 10-12 is solicited.If it is judged that for not having Available part disclosure satisfy that or substantially meet wanting included in the information that step 10-12 is solicited Ask, then generate each patch that can meet the requirement included in the information that part steps 10-12 is solicited, and Selection information (step 17) of described each patch is provided.These patchs are made a choice (step 18) concurrently Send selected patch or the representative image of patch group or mark (step 19).Selected patch or patch group are carried out Assessment decides whether that other patchs are to meet the requirement included in the information that step 10-12 is solicited (step 20).If needing other patchs, step 17-20 starts the cycle over repetition from step 17；If Selected patch or patch group meet the requirement included in the information that step 10-12 is solicited, then these quilts Patch or patch group is selected to be placed on (step 21) in the integrated circuit treating construction.Due to above-mentioned described Patch feature and the framework of STD bus so that patch is be positioned over after the integrated circuit of construction can be quickly Automatically generate physical layout data (step 22).

In one example, the GDS II layout data of every piece of patch chosen is from a GDSII patch domain Data base obtains.GDS II data describe the structure of each layer of patch, obtained selected patch GDS II data are integrated into into synthesis GDS II layout information, are used as to treat many patchs integrated circuit of construction Layout data.Now, the integrated circuit being made up of PMIC tile is determined.

For treating the integrated circuit of construction, solicit control and require that information (step 23) determines the requirement of programming. Based on the requirement information solicited, generate comprehensive integrated circuit specification (step 24) treating construction. For every piece of PMIC tile of MTPMIC, generate the tile configuration information (step 25) that can be used for programming. In one example, it is provided that a USB (universal serial bus) (USB) Dongle 50, USB software protector 50 have a slot or other mechanical mechanisms, it is possible to make the point cantact to MTPMIC51 and physical contact enter Row programming, the USB port of the computer 30 running ATSPCP tool 46 is inserted in one end of Dongle 50 In 52, it is not programmed that MTPMIC51 is inserted in the slot being positioned at the Dongle other end.Former After the mode stated determines configuration information, configuration information is passed through USB port 52 and USB by ATSPCP tool 46 Dongle 50 is transferred in MTPMIC51, is then transferred to main patch, and by MTPMICD standard Bus transfer in the suitable configuration register of each PMIC tile, thus each PMIC tile is programmed and Configuration.If it is required, MTPMIC51 can constantly be carried out overprogram by Dongle 50.

Fig. 6 is ATSPCP tool and the preferred embodiment schematic diagram of user 34 Communication on the Internet.? In this preferred embodiment, ATSPCP tool be a set of that be stored on processor readable medium, can be by processor The programmed instruction performed.Processor readable medium can be computer hard disc, DVD, CD, floppy disk, solid-state storage Device (such as random access memory ram), flash memory, EPROM or removable internal memory driver.It is stored in readable The programmed instruction of medium is read by computer and performs.In another embodiment, ATSPCP46 is by a meter Calculation machine performs, and user directly can communicate with exchange by display, it is also possible to remotely pass through network (as LAN) it is in communication with exchange.

In the preferred embodiment shown in Fig. 6, the first computer 30 is connected with first network port 35, This port is communicated by the Internet and second network port 32, and second network port is connected to be grasped by user 34 The second computer made.The ATSPCP tool 46 being implemented on computer 33 passes through the Internet 31 by power supply Management characteristic inquiry message is transferred to user 34.User is transferred back to choosing to the echo message 37 of inquiry message Selecting instrument, based on this echo message 37, ATSPCP tool 46 selects a power management 38.In the preferred embodiment, inquiry message 36 includes one or a series of webpage, and webpage is by running on calculating Web browser on machine 33 presents, and this browser can be such as MS internet explorer, and user is permissible Webpage is browsed by computer display.In other embodiments, inquiry message 36 can be by running on calculating Software Create on machine, is directly displayed to the user that by computer display.

Fig. 7 A is an example, the inquiry message of explaination power management features with the form of webpage 40 be shown to User 34, and this webpage comprises solicits input source information.In this instance, input source information includes that battery is as The user option 41 in one source and for the source that maximum current is 1 ampere of power supply adaptor as the use in the second source Family input item 42.User selects to be one of option specified in inquiry message user.Such as, user option 41 is a hook number in dialog box, and as one of the echo message 37 done for inquiry message 36 Point.User's input item is the instruction for parameter value specified in inquiry message.Such as, user's input item 42 is a digital quantity, the adapter maximum current needed for instruction, and as user for inquiry message 36 A part for the echo message 37 done.The example of input source information 43 includes input voltage information (such as The supply voltage of webpage 40) and input current information (the such as maximum current of webpage 40).About input Other examples of source information can include the restriction etc. to voltage and current value, the most exhaustive, and other are permitted Multiparameter can be solicited to user as a part for the input source information solicited.

Fig. 7 B is an example, and explaination power management characteristic query 36 information is shown to use with the form of webpage 44 Family 34, this webpage comprise solicit power supply output require information.The example of power supply input requirements information 45 includes Output voltage in supply voltage output channel quantity and each passage and the information of output electric current.Fig. 7 B Illustrate one to require as output current information and output voltage requirement using the minimum current of each passage Example as output voltage information.About such example not the most exhaustive, other many parameters are permissible Require that a part for information is solicited to user as the power supply output solicited.

Fig. 7 C is an example, and explaination power management characteristic query information 36 is shown to use with the form of webpage 50 Family 34, this webpage comprises solicits control input/output (I/O) requirement.The example controlling I/O requirement includes During the control input of a certain amount of ON/OFF, a certain amount of replacement input, a certain amount of replacement export and are a certain amount of Disconnected output.About such example not the most exhaustive, other many parameters can be as the control solicited The part that I/O requires is solicited to user.The most do not solicit control I/O requirement.

Fig. 8 is the schematic diagram that integrated circuit patch option is shown to user 34 with the form of webpage 60.Relatively In good embodiment, according to user's echo message 37 to power management characteristic query information 36, ATSPCP work Tool 46 generation string integrated circuit patch option.Webpage 60 is to need what user gave a response to solicit information, The quantity of the integrated circuit patch that its illustrative user is wanted and type, to meet power management characteristic query letter The requirement comprised in the information that breath 36 is solicited.In another embodiment, ATSPCP tool 46 is according to user For the echo message 37 made of power management characteristic query information 36, directly select a power management collection Become circuit patch.In certain embodiments, the figure of power management can be selected to represent (example Such as a rectangle representing its border).In other embodiments, power management can be selected Text representation.

Fig. 9 is the graphical representation schematic diagram of the selected patch being shown to user 34 with webpage 70 form.Relatively In good embodiment, the patch presenting to user is simple figure or character forms, does not include concrete circuit Physical characteristic information.Such as, power management 71 represents actual patch physical form with one Simple square and the mode of patch word indicating symbol present, the most do not comprise any relevant patch 71 The specifying information of inner function circuit.

Figure 10 is another example figured of the selected patch being shown to user 34 with webpage 72 form Schematic diagram.In this example, ATSPCP tool 46 is selected in transmitting the integrated circuit treating construction One simple graph of integrated circuit patch represents or indicates.According to novel standard bus architecture discussed above, The physical layout data of the integrated circuit shown by webpage 72 can be directly generated by ATSPCP tool 46, with For IC manufacturing.ATSPCP tool 46 can be according to the known physical layout data of every piece of individual tile Overall physical layout data needed for generation.ATSPCP tool can be put automatically according to the display content of webpage 72 Put each patch.

In another embodiment, the echo message for user, power management characteristic query information 36 made 37, ATSPCP tool 46 generates a series of available MTPMIC.As it was previously stated, available part can meet Or substantially meet needs.

Figure 11 A be with webpage 80 form send to user 34 available MTPMIC part textual form represent Schematic diagram.In order to meet the requirement indicated by power management characteristic query information, available part is presented to User, solicits the user 34 quantity for Integrated circuit portion and the hobby of type.Levy as to webpage 80 Ask the response of information, select instrument to select an available Integrated circuit portion.

Figure 11 B is the graphical representation schematic diagram of the optional partial circuit sending user 34 with webpage 81 form to. Simple graph or character forms include the relative size of PMIC tile and the identifier to every piece of patch, but do not wrap Include the specifying information of circuit physical feature.

When optional integrated circuit part can not meet the requirement that power management characteristic query information 36 is solicited Time, ATSPCP tool 46 can select extra discrete component to meet these requirements.This selection can be by selecting Instrument of selecting directly is carried out or by soliciting guided by the result that discrete component is liked by user.These discrete components It it is the add ons of integrated circuit external.

Figure 12 is delivered to the schematic diagram of the webpage 82 of user 34, webpage 82 include one meet want The figure of the combination asked represents.This combination includes available integrated circuit 47 and at least one discrete component 48.Can Interconnect in an appropriate manner on a printed circuit board (PCB) with integrated circuit 47 and discrete component 48,49, The demand of user can be met.

Figure 13 is the schematic diagram that novel ATSPCP tool 46 exchanges on the internet with user.Preferably implementing In example, instrument 46 is a set of processor executable being stored in processor readable medium.Processor is readable Medium can be computer hard disc, DVD, CD, floppy disk, solid-state memory (such as random access memory ram), Flash memory, EPROM or removable internal memory driver.Be stored in the instruction of readable medium read by computer and Perform.In other embodiments, running on the place tool on computer can be by display or such as The telecommunication network of LAN directly exchanges with user.

In the preferred embodiment shown in Figure 13 A and Figure 13 B, computer 93 is connected with the Internet 92 and aobvious Show that device 91 display includes the webpage 90 of the content come from computer 93 transmission.As shown in FIG. 13A, first Step, computer 93 performs instrument 46, and the first figure representing, 94 are transmitted by the Internet 92.Display 91 provide the webpage 90 representing 94 containing figure.Webpage 90 illustrate not yet be placed together to form yet to be built The stand-alone integrated circuit patch of the integrated circuit of structure.Second step, instrument 46 is received for figure and represents 94 Echo message 95, indicates the intention according to user patch to be put together and forms the integrated circuit treating construction.

As shown in Figure 13 B, the 3rd step, instrument 46 transmits second graph by the Internet 92 and represents 98.Aobvious Show that device 91 provides containing this figured webpage 96.Webpage 96 illustrates and puts together in order to forming portion Divide each stand-alone integrated circuit patch of the integrated circuit treating construction.User can be moved by drag operation 97 Patch figure in Figure 13 A represents, thus forms the integrated circuit treating construction as shown in Figure 13 B.4th Step, computer receives response 99, and the placement of the integrated circuit that this response instruction user treats construction is satisfied with. As response, in the 5th step, instrument 46 generates the physical layout data for manufacturing the integrated circuit treating construction.

Being another embodiment of ATSPCP tool 46 operation as shown in figure 14, this operation includes recording step. The first step, the computer 114 of execution instrument 46 receives a response 112.Respond 112 instruction users to agree with showing Show the arrangement that in device 110, the integrated circuit pattern treating construction shown in webpage 111 represents.As to response The response of 112, ATSPCP tool 46 this arrangement having agreed under the storage device records of computer 114 113 as an arrangement recorded.

Figure 15 is another step, illustrates the graphical representation being shown an arrangement being recorded by webpage 115, This graphical representation includes an integrated circuit and at least one discrete component.

Figure 16 illustrate based on as shown in figure 15 be recorded arrangement and a part of printed circuit board (PCB) of carrying out Design.

Figure 17 illustrates and illustrates to be combined into a comprehensive specification explanation by the specification of three pieces of individual tile 120-122 123, for the integrated circuit that thus three pieces of patchs are formed.Comprehensive specification explanation can include encapsulation of data, Such as pin assignment data, sized data, lead spacing, application data and the performance parameter of integrated circuit.

Figure 18 illustrates the operation according to the ATSPCP tool 46 in terms of another novelty.Preferably implementing In example, ATSPCP tool 46 is a set of processor executable being stored in processor readable medium.Place Reason device readable medium can be computer hard disc, DVD, CD, floppy disk, solid-state memory (such as random access memory RAM), flash memory, EPROM or removable internal memory driver.It is stored in the instruction of readable medium by computer Read and perform.In other embodiments, run on the place tool on computer can by display or The telecommunication network of person such as LAN directly exchanges with user.

Computer 133 is connected with the Internet 132 and display 130 shows to include and passes from computer 133 The webpage 131 of defeated next content.In the first step, computer 133 performs ATSPCP tool 46, by power supply Management control characteristic inquiry 134 is transmitted by the Internet 132.Display 130 display is containing inquiry message Webpage 131.The control that webpage 131 is solicited needed for containing requires information.Second step, instrument 46 receives pin Echo message 135 to inquiry message 134, illustrates user's requirement to control characteristic.As response, In 3rd step, instrument 46 generates tile configuration information 136.

Figure 19 A shows that being solicited control by webpage 140 for one requires that the power management control characteristic of information is inquired Example.Such as, problem is specifically directed to the characteristic required for every piece of patch, thus draws control requirement.Right For main patch, these problems include docking port agreement, clock frequency, replacement pause period, button interfaces, Reference source bypasses, controls the destination register of the first patch open/close state and the choosing of the polarity etc. of this state Select.Other problem is specifically designed for the characteristic needed for the first buck tile.These problems include to standby voltage, Whether whether mode of operation, switching frequency, switch phase, fault interrupting, tracking enable and by main patch Signal automatically start the selection of this patch etc..The response relevant with the problem of every piece of individual tile forms independence A part for patch specification explanation, is present in every piece of patch in many patchs integrated circuit.

According to the storage organization of novel, in the preferred embodiment, the memorizer in every piece of individual tile is only Store the configuration information of to one's name patch.For the address of recognition memory, it is stored in configuration register The function of every place value predetermines.Therefore, as shown in Figure 19 A, the control solicited for every piece of patch System requires that information can map directly to the specific tile configuration information of every piece of individual tile.As shown in Figure 19 B, Tile configuration information is a Bit String, and this bit string represents in MTPMIC stored by the configuration register of every piece of patch Bit value.In the example of Figure 19 B, the configuration information Bit String being loaded into BUCK_1 depositor is “10010110”.In this manner, it is stored in configuration register and can be directly used for configuring integrated electricity The tile configuration information on road, directly can be had many patchs integrated circuit of this patch according to power supply by any Management control characteristic is inquired and is generated, it is not necessary to just may be used for each IC design Custom Prosthesis memory construction To set up suitable Bit String and register address.

As shown in figure 20, the tile configuration information 136 generated by ATSPCP tool 46 for explaination configures a spelling The example of sheet.In the simplification of Figure 20 is illustrated, every piece of patch includes one or eight bit memory organization depositors.These The numbered 316-322 of depositor.Bus Interface Unit 314 in main patch 312 is total by a common data Line DIN [7:0] is coupled to the memory element of every piece of patch.In the preferred embodiment, common data bus is A part for STD bus 350 shown in Fig. 2, for convenience of description, is separately depicted in fig. 20.

In this example, patch comprises needs configuration and the analog power control circuit controlled.The one of this kind of circuit Individual example is constant current constant voltage (CC-CV) battery charger in patch 307.This charging circuit for Battery outside integrated circuit 301 provides charging current.The output voltage of charging circuit is a modulated electricity Pressure, its amplitude is determined by the first value being stored in depositor 318.The cut-off current of charging circuit equally by Programming, and determined by the second value being stored in depositor 318.Charging circuit can also be enabled and invalid, It is determined by the 3rd value being stored in depositor 318.

In one embodiment, each storage organization includes a non-volatile cell and a volatile cells.Collection Becoming circuit 301 once to power on, the data content in non-volatile cell is automatically transferred in volatile cells. The data being stored in volatile cells are supplied to the circuit in patch 307 in turn, configure it and control. In one example, once after integrated circuit 301 initial power-on, there is the depositor 318 of storage organization Non-volatile cell runs to the logic state invalid so that the charging circuit of patch 307.Then, microcontroller Device 302 writes data to the depositor 318 with storage organization, thus configures the output voltage of charging circuit With restriction electric current.Afterwards, microcontroller 302 is by the suitable storage organization of suitable value write depositor 318 In, thus enable this charging circuit.Charging circuit subsequently enters properly functioning, enters external cell or equipment Row charging.

If system 300 re-powers after being de-energized, owing to previous configuration information is already stored in depositing In the non-volatile cell of device 318, microcontroller 302 need not the storage organization of patch 307 carries out weight Newly configured.Data content in the non-volatile cell of depositor 318 can entered to depositor 318 automatically In the volatile cells of middle correspondence, so that the circuit of patch 307 can be configured and control by configuration information System.

In the example illustrated, each piece of patch 305-311 be all mutually coupled receive from same data total Line DIN [7:0], same program voltage wire and the information of same programming signal wire.Program voltage wire and Programming signal wire is represented by the arrow indicating VPP and PGM respectively.In addition to these common wire, every piece Patch each connects, and receives the local clock pulses of autonomous patch 312.The local clock letter of patch 307 Number represent with reference number L.Local clock pulses L is connect by depositor 318 by clock signal conductor 326 Receive.It is set to overturn to the clock being intended for a depositor simultaneously, and specific clock signal is allowed to according to passing through The value of address AD R that Bus Interface Unit 314 is loaded into overturns.

For example, if microcontroller 302 to write data to the depositor 318 of patch 307, the most micro- Controller 302 provides address AD R by bus 303 to Bus Interface Unit 314.This address AD R It is latched in Bus Interface Unit 314.This address is decoded by decoder 315, the most fair with door 324 Perhaps on clock signal is provided in clock output line one.In this example, patch 307 is recognized when address Depositor 318 after, permission clock signal is delivered to this locality by global clock wire 325 by decoder 315 Clock conductor 326 and depositor 318.

The data write bus preparing write depositor 318 is connect by microcontroller 302 subsequently by bus 303 Mouth unit 314.These data pass sequentially through data/address bus DIN [7:0] and are provided to the institute of integrated circuit 301 Have in depositor.Bus Interface Unit 314 receives the clock signal on global clock wire 325 subsequently, from And provide local clock pulses to the depositor addressed by address AD R.In this example, local clock pulses L It is provided to depositor 318.This clock signal is that data are transferred to depositor from data/address bus DIN [7:0] The volatile cells of 318 provides clock count.By this way, microcontroller 302 can write data into In any one depositor of in integrated circuit 301 316 to 322.

Once data are written into the volatile cells of destination register, and a programming pulse signal is provided to collection Become circuit 301.This programming pulse signal is provided to all depositor 316-323 of integrated circuit 301 In all storage organizations.Each volatile cells of depositor 318 has a corresponding non-volatile cell. If the data content in non-volatile cell is different from the data content in volatile cells, non-volatile list Unit can be programmed, thus the data content that storage is identical with volatile cells.If in non-volatile cell Data content identical with the data content in volatile cells, the most do not change and be stored in non-volatile cell Digital logic states.In another embodiment, programming pulse signal is generated by integrated circuit 301 is upper. In this manner it is achieved that the field programming to integrated circuit 301.Such as, in system operation Volatile memory can be changed, so that system is converted to sleep or battery saving mode.

Figure 21 show the schematic diagram according to the ATSPCP tool 46 in terms of another novelty.In this enforcement In example, ATSPCP tool 46 is a set of processor executable being stored in processor readable medium.Place Reason device readable medium can be computer hard disc, DVD, CD, floppy disk, solid-state memory (such as random access memory RAM), flash memory, EPROM or removable internal memory driver.It is stored in the instruction of readable medium by computer Read and perform.In other embodiments, run on the place tool on computer can by display or The telecommunication network of person such as LAN directly exchanges with user.

The first step, ATSPCP tool 46 receives a first requirement 177 at first instance 171；Two steps, work Tool 46 identification particular type MTPMIC group meets one of first requirement；3rd step, to identified The MTPMIC meeting first requirement is programmed.This program is that every piece of patch of configuration MTPMIC is musted The configuration information of palpus.It is programmed that a MTPMIC is sent to first instance；4th step, ATSPCP work Tool 46 receives one second requirement from a second instance；5th step, ATSPCP tool 46 is from MTPMIC In identify one the 2nd MTPMIC with a MTPMIC same type；6th step, for meeting the second requirement And the 2nd identified MTPMIC is programmed by the program designed.This program is every piece of configuration MTPMIC Patch meets configuration information necessary to the second requirement.It is programmed that the 2nd MTPMIC is sent to second instance. Unit with type is identical or the most close.

One feature of preferred embodiment is that same type of MTPMIC can be reconfigured to meet different visitor The needs at family.Figure 22 is that the power management integrated circuit 301 shown in Fig. 2 simplifies the schematic diagram replicating. Such as, the 5V output voltage that each step-down controller patch can provide a road maximum current to be 1A.If The first requirement of first instance is the 3.3V output voltage needing three road maximum currents to be 1A, and three pieces of blood pressure lowerings are spelled Each piece of sheet can be configured to export a road required voltage, by using the side described in similar Figure 20 Method, can configure every piece of buck tile and make it export the output voltage of 3.3V.Second requirement of second instance is The 3.3V output voltage needing a road maximum current to be 2A.In one embodiment, program through another, By making one piece of buck tile invalid and connecting remaining two pieces of buck tile one biphase step-down controller of composition Combination improves power supply fan-out capability, thus meets this requirement.Under such arrangement, the first buck tile Be programmed to 0 degree output phase place and the second buck tile be programmed to 180 degree output phase places.And, two Step-down controller shares a pulse-width modulation control signal to realize the raising of fan-out capability.Such as, at one In master/slave arrangement, the first buck tile the pulse-width modulation control signal generated is not merely for control first Buck tile, and be transmitted to the second patch and control it.

Figure 22 depicts a part for power management integrated circuit 301, is used for explaining configuring in the foregoing manner Two buck tile are to meet the detail of the second requirement.Every piece of patch include a bus portion, an input/ Output interface part, storage part and a funtion part.Buck tile 305 includes producing pulsewidth modulation control The functional circuit 380 of signal 387 processed, this control signal is on input/output interface 383 and holding wire 385 Transmission.Similarly, buck tile 306 includes the functional circuit 381 receiving pulse-width modulation control signal 387, This control signal is transmitted on input/output interface 382 and holding wire 386.In order to meet the second requirement, arteries and veins Wide modulator control signal 387 must by a bus-type wire from input/output interface 383 be transferred to input/ Output interface 382.

The interface section of patch includes a set of Port Multiplier and shunt.Port Multiplier and shunt can be used by control Connect a target bus type wire and a set of destination node.Form a functional circuit so that no matter from it The information that receives at his patch is still in the case of other patch transmission information, and signal conductor can be connected to On this node.By the control that docking port part Port Multiplier and shunt are suitable, the signal of functional circuit is led Line is connected on a target bus type wire through interface section.Due to the company of STD bus between adjacent patch Connect mode so that target bus type wire extends to the total interface part of all patchs of integrated circuit.Therefore, The interface section of one piece of patch can be connected to a certain target joint of functional circuit in another patch by configuring Point.

In the specific examples shown in Figure 22, holding wire 385 and 386 is connected respectively to interface section 383 With in the corresponding node of 382.The memory part of every piece of patch stores configuration information in non-volatile memory cells In.This configuration information is controlled by the functional circuit of patch, it is provided that control multichannel to patch interface section Device and the configuration of shunt.Therefore, the configuration information content of memory part, Ke Yigai it are stored in by change Become the Port Multiplier in the interface section of integrated circuit 121 and the configuration of shunt.

In the example shown in Figure 22, the memory part 316 of buck tile 305 and buck tile 306 interior Nonresident portion 317 is written into configuration information so that the holding wire 385 of the functional circuit 380 of buck tile 305 The holding wire 386 of the functional circuit 381 of buck tile 306 it is couple to by interface section 383 and 382.

The configuration of the storage part of various patchs is loaded into by main patch 312, with similar as described in Figure 20 Mode is carried out.Figure 22 shows that the tile configuration information EBI 314 from main patch 312 is to buck tile The signal path of the memory part 316 of 395.In terms of another novelty, a programmable analog tile Integrated circuit is configured by STD bus, and configuration information is integrated via second from the first integrated circuit patch Circuit patch arrives the 3rd integrated circuit patch.Three integrated circuit patchs are a part for an integrated circuit. In Figure 22 example, form the wire transmission tile configuration information of STD bus from main patch 312 via fall Pressure patch 306 arrives buck tile 305.In another embodiment, main patch 312 by STD bus to All patchs provide reference voltage, clock signal and other common sources.

Similarly, power supply patch may be configured to run parallel or leggy operation.Patch output is permissible It is cascaded or is connected in series, the input being output into another module of a patch.Want according to special Asking, the skilled people grasping this art one can easily realize that multiformity and the dynamic and configurable of selection The well-formedness of structure, this framework can be with only by implementing various optional tile programming modes and elastic patch Method of attachment realizes.All these can need not to reformulate domain or use design verification, Realize in the case of circuit simulation or unable design verification, because STD bus makes all holding wires to each Block patch all can be used, and by reasonable disposition, tile configuration information can be connected to STD bus by every piece Patch generates.More specifying informations about intercommunication exchange configuration patch refer to number of patent application and are 11/978,458, the date is the U.S. Patent application on October 29th, 2007.(whole about this file Individual theme adnexa in this as reference.)

It is a flow chart as shown in figure 23, is illustrated as meeting customer requirement and power management integrated circuit is compiled One example of journey.This process starts from soliciting input source information 150, power supply output requires information 151, Control I/O and require that information and control require information 153.Wherein control I/O and require that soliciting of information is can Choosing.In certain embodiments, information 150-153 controls as power management characteristic query and power management A part for property query is solicited.The information solicited is used for assessing whether 154 its available parts meet Or the requirement that the information 150-153 of substantially meeting is comprised.If it is determined that can use at least partially, then generate The option one 55 of available part.By assessment 156, each option determines whether this option meets and is levied Ask the requirement of information 150-153, or the need of other resource.If needing other resource, then These resources will be defined 157 so that available part and other resource disclosure satisfy that solicited information Requirement in 150-153.If it is determined that do not have available part to disclosure satisfy that or substantially meet solicited letter The requirement of breath 150-153, then generate customization PMIC option one 58, and this customization PMIC meets solicited information The requirement of 150-153.Sent by the product information of the 158 and/or 155-157 relevant PMIC options generated To an entity, such as an intended client 159.Product information can include pricing information, R&D cycle letter Information and ordering information etc. are seeked the opinion of in breath, additional control requirement, the most exhaustive all information included. Response to product information is received 160 and is thrown sheet according to response 162 startup MTPMIC.

Figure 24 is the flow chart of method 405.One power management characteristic query is transmitted to user's (step 400), such as potential customers.Response to inquiry is received (step 401) by network.This network Can be LAN or the Internet.According to response, a PMIC tile selected (step 402).Step 400-402 is completed by ATSPCP tool 46.

Figure 25 is the flow chart of method 415.First patch is relative to the first figure of the primary importance of the second patch Shape is transmitted (step 410).The first response to the first figure is received (step 411).According to first Responding, the first patch is transmitted (step 412) relative to the second graph of the second position of the second patch. The second response to second graph is received (step 413).This second response is the accreditation to second graph. Responding according to second, generate an integrated circuit layout data (step 414), this integrated circuit comprises and is in First patch of the second position.Step 410-414 is completed by ATSPCP tool 46.

Figure 26 is the flow chart of method 450.First patch is relative to the figure quilt of the primary importance of the second patch Transmit (step 451).This figure can pass through Internet transmission.Response to figure is connect by network Receive (step 452).According to response, it is manipulated by (step relative to the figure of the first patch of the second patch placement Rapid 453).Step 451-453 is completed by ATSPCP tool 46.

Figure 27 is the flow chart of method 425.One power management control characteristic inquiry is transmitted to a user (step Rapid 420).User is received (step 421) to the response of inquiry by network.According at least part of user Respond and generate tile configuration information (step 422).Step 420-422 is completed by ATSPCP tool 46.

Figure 28 is the flow chart of method 436.Obtain one first control from first instance and require (step 430). The MTPMIC (step 431) of a type is identified from the MTPMIC inventory currently produced.Use First method is to one the oneth MTPMIC programming in identified MTPMIC type, to meet the first control Require (step 432).Obtain one second control from second instance and require (step 433).From manufacturing MTPMIC inventory identifies the MTPMIC (434) identical with the type that step 431 is identified. Use second method that one the 2nd MTPMIC in identified MTPMIC type is programmed, to meet second Control to require (step 435).In some example, this inventory is on-hand inventory.In other examples, This inventory is the available design that will be manufactured.In one example, step 430-435 is set by such as quasiconductor Meter company or store company or distributor company complete, and the first and second entities are the client of company.Public Department uses ATSPCP tool 46 determines how to be programmed the first and second MTPMIC.

Figure 29 is the flow chart of method 460.One power management characteristic query is transmitted (step 461).With Family is received (step 462) to the response of inquiry by network.Respond first according at least part of user PMIC tile is programmed (step 463).This PMIC tile ingredient power management integrated circuit.

Figure 30 is the flow chart of method 470.Obtain control by network from an entity and require (step 471). The multiple PMIC tile (step 472) of identification are responded according at least part of user.These patchs composition treats construction Power management integrated circuit.Product information about the PMIC treating construction sends this entity to by network (step 473).Step 471-473 is completed by ATSPCP tool 46.

Figure 31 is the flow chart of method 445.Tile configuration information is through second from the first integrated circuit patch Integrated circuit patch passes to (step 440) of the 3rd integrated circuit patch.First, second, third is integrated Circuit patch is the ingredient of MTPMIC.In first, second and third integrated circuit patch at least one It it is power management.

In the described embodiment, from any novelty instrument to overall transmission may be by as The network of INTERNET or LAN.But, any novelty instrument the content produced can also directly in Browse being supplied to an entity on computer monitor now.One entity can be a potential passenger, User, company or any individual or the collective relevant with company.In the described embodiment, webpage is used to Transmission information.But, information can also be transmitted by a series of webpages.

When one widely tile library constitute product, through checking design, PMIC can need not tradition It is designed with sex-limited demand, need not circuit simulation, need not DRC/LVS physical Design and tested and be just placed on Together.It is clear that the above embodiments provide and traditional design mode (e.g., simulation/electronics mark Quasi-IP library, etc.) visibly different method, at least patch in more preferable embodiment be applicable size Or the size aspect being relatively suitable for is such, and these patchs are that the analog/mixed signal that can program is spelled Sheet, has size, and it is furnished with port can reach the solution size of minimum and the fastest towards market Time.Such as, in more preferably embodiment, patch all length and width about 0.5 millimeter is multiplied by The I/O port separation distance of 0.5 millimeter, the most as shown in Figure 3, and is furnished with reference power supply, exchanges and control Total road, when patch is put together when, it can link together automatically.In this manner it is possible to it is the quickest Easily highly integrated power supply is controlled integrated circuit to put together, at least as tile library With the efficiency in brains the most all set.

Although some special exemplary embodiments is already described above, in order to this invention to be described, but This invention is not limited only to these particular embodiments.Although ATSPCP tool is described above, i.e. shape Become patch to select, disposed, configured and programing function, but ATSPCP tool need not realize all functions Or all functions of even having had the ability.Such as, support can use ATSPCP tool execution patch to select With the operation disposed.Once having disposed, the second ATSPCP tool can be used to determine configuration information and compile Collect the real content in catalogue or produce the physical design data of combination in order to improve out satisfied MTPMIC. Dongle 50 can be used to edit MTPMIC in center, and wherein computer 30 is had good positioning, this The MTPMIC edited that sample produces the most just has been transported to personal user.Or, individual supports can also Dongle is used remotely to edit MTPMIC user.Dongle is it may be that but need not necessarily Be, connect perform ATSPCP46 on same computer.Correspondingly, the different characteristics of the embodiment of description Different amendments, transform and synthesize the scope that can need not leave the invention in rights statement book and just carry out Implement.

Claims (25)

1. the method simulating patch selection, placement, configuration and programming, it is characterised in that comprising:

A () processing module sends the inquiry message of a power management features to a user side by network；

B () described processing module receives the described user side echo message to described inquiry message by network； With

C () described processing module is at least partially based on the described user side echo message to described inquiry message Select one first power management, described first power management There is a depositor, described depositor by a STD bus separately addressed and write information.

2. the method simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, the next free input voltage information of described power management characteristic query information is seeked the opinion of and is seeked the opinion of with output voltage information The group formed.

3. the method simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, farther include:

D () described processing module is at least partially based on described user side and selects the echo message of described inquiry message Select a second source management integrated circuit patch；With

E described first power management integrated circuit that () described processing module sends placed adjacent by network is spelled Sheet and a representative sample of described second source management integrated circuit patch.

4. the method simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, it farther includes:

D () described processing module sends a representative of described first power management by network Sample.

5. the method simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, it farther includes:

D described first power management integrated circuit that () described processing module sends placed adjacent by network is spelled Sheet and a representative sample of second source management integrated circuit patch.

6. the method simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, described first power management is the member of a power management group, its Comprise one first bus portion；Belong to the second source management in described power management group Integrated circuit patch comprises one second bus portion；If described first power management integrated circuit is spelled and described Second source management integrated circuit patch placed adjacent in an integrated circuit diagram, the most described first bus portion Divide and described second bus portion is connected to form described STD bus.

7. the method simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, described first power management is from the group consisted of: a step-down controller patch, One boost converter patch, a low dropout regulator patch, a linear regulator patch, a battery charger Patch, an electric charge pump patch, a battery and power source path management patch, a switch power controller patch and One lighting control module patch.

8. the method simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, described first power management and second source management integrated circuit patch placed adjacent Form patch integrated circuit more than.

9. the method simulating patch selection, placement, configuration and programming as claimed in claim 8, its feature exists In, described many patchs integrated circuit includes an illumination supervision unit.

10. the method simulating patch selection, placement, configuration and programming as claimed in claim 8, its feature exists In, described many patchs integrated circuit includes a Power Management Unit.

11. methods simulating patch selection, placement, configuration and programming as claimed in claim 8, its feature exists In, described many patchs integrated circuit includes an electricity processing unit.

12. methods simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, it includes that providing a webpage, described power management features inquiry message is a part for described webpage.

13. methods simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, described power management features inquiry message is to seek the opinion of input source information.

14. methods simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, the inquiry of described power management features is to seek the opinion of power supply output to require information.

15. methods simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, described network is the Internet.

16. methods simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, described echo message includes by the output voltage values of user's input.

17. methods simulating patch selection, placement, configuration and programming as claimed in claim 1, its feature exists In, described echo message includes the output voltage values selected by user.

18. 1 kinds of methods simulating patch selection, placement, configuration and programming, it is characterised in that comprising:

A () processing module transmits a power management characteristic query information to a user side；

B () described processing module receives the described user side echo message to described inquiry message by network； With

C echo message that () described processing module is at least partially based in described (b) selects an integrated circuit Patch, described integrated circuit patch has a depositor, described depositor by a STD bus separately addressed and Write information.

19. 1 kinds of methods simulating patch selection, placement, configuration and programming, it is characterised in that comprising:

A () processing module transmits a power management characteristic query information by network；

B () described processing module receives the echo message to described inquiry message by network；With

C () described processing module is at least partially based on the echo message in described (b) and selects one first power supply One representative sample of management integrated circuit patch, described first power management has a depositor, Described depositor by a STD bus separately addressed and write information.

20. methods simulating patch selection, placement, configuration and programming as claimed in claim 19, its feature exists In, step (c) includes that described processing module selects one based on the echo message in the most described (b) One figure of the first power management represents, described figure represents and includes a rectangle.

21. methods simulating patch selection, placement, configuration and programming as claimed in claim 19, its feature exists In, step (c) includes that described processing module selects one based on the echo message in the most described (b) The text representation of the first power management.

22. methods simulating patch selection, placement, configuration and programming as claimed in claim 19, its feature Being, described processing module is a computer.

23. 1 kinds of simulation patch selection, placement, configuration and programming devices, it is characterised in that comprising:

One network port；

One processing module；

One user side, described user side is by the described network port and described processing module communication；

Described processing module sends a power management characteristic query information to described user by the described network port End, and receive the described user side echo message to described inquiry message, described processing module is according to described time Answering information, described processing module selects one first power management based on described echo message, Described first power management has a depositor, and described depositor is independent by a STD bus Addressing and write information.

24. 1 kinds of methods simulating patch selection, placement, configuration and programming, it is characterised in that comprising:

A () provides a webpage, described webpage to include a power management characteristic query information；

B () processor receives a user side echo message to described inquiry message；With

C () described processor selects multiple power management integrated circuits based on the echo message in described (b) Patch, the plurality of power management is respectively provided with a depositor, and described depositor is by a standard Bus separately addressed and write information, described patch is from the group consisted of: a step-down controller patch, One boost converter patch, a voltage regulator patch and a linear regulator patch.

25. methods as claimed in claim 24, it is characterised in that it farther includes:

The physical layout number of the most the plurality of power management chosen of (d) described processor According to, thus form the physical layout data for the integrated circuit of patch more than.