CN101848588A - Control method of full digital high-power metal halide lamp electronic ballast - Google Patents
Control method of full digital high-power metal halide lamp electronic ballast Download PDFInfo
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- CN101848588A CN101848588A CN201010201536A CN201010201536A CN101848588A CN 101848588 A CN101848588 A CN 101848588A CN 201010201536 A CN201010201536 A CN 201010201536A CN 201010201536 A CN201010201536 A CN 201010201536A CN 101848588 A CN101848588 A CN 101848588A
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Abstract
The invention relates to the control method of the electronic ballast and aims to provide a control method of a full digital high-power metal halide lamp electronic ballast. The method comprises the step of controlling the start-up procedure and steady state operation of the electronic ballast, wherein the hardware counter in the DSP controller circuit and the ADCs are set to perform interrupt drive, and when the DSP controller circuit drives one ADC to break out, the corresponding circuit modules in the circuit are controlled to execute in turn, thus controlling the power-on, power-off, constant-power operation and V-shaped grooving operation of the metal halide lamp. The method can be used in the control of the high-power electronic ballast device, can perform power factor correction control to the input stage of the ballast and reduce the pollution to the harmonic wave of the grid; power grooving control is performed to the Buck converting circuit, thus achieving the aim of protecting the power switch and passive elements; and the DSP controller circuit has 16-path ADC for sampling and 16-path PWM so that the control circuit can be easy to design, the reliability of the system can be improved and the hardware cost can be reduced.
Description
Technical field
The present invention relates to a kind of control method of electric ballast, the control method of particularly a kind of full digital high-power (multikilowatt) metal halide lamp electronic ballast.
Background technology
For powerful ballast, realize functions such as High Power Factor, low Harmonics of Input, lamp power adjustments, generally all adopt the simulation controlling schemes at present.Along with the reduction greatly of digitial controller costs such as DSP, be the direction of future development based on the electric ballast of total control system.The DSP numerical control system has flexibility and is convenient to realize fast the characteristics of complicated controlled function, makes that same control system can be according to the characteristic changing control strategy of lamp to adapt to the control of different lamps.
The electric ballast contrast of the electric ballast of employing digitial controller and traditional employing analog controller, the former has following advantage:
(1) required peripheral components is few, and circuit is fairly simple with respect to simulation control;
(2) anti-interference to noise is better than analog circuit, and is difficult for aging;
(3) adaptability is strong, does not need to change circuit when needing to change control algolithm and just can realize, can realize modularized design;
(4) in general, the permanent power control of the electric ballast of a lot of simulation controls often belongs to approximate constant power control, is not real permanent power, and control precision is lower.Simulate the control of permanent power in addition and must will use and add analog multiplier, so just strengthened the cost of electric ballast.For digital control, there is ready-made high-speed gear DSP inside, easily realizes accurate permanent power control;
(5) can carry out fault self-checking and protection to system, realize Presentation Function, and can carry out communication, realize the networking application with host computer.
Digital high power (multikilowatt) metal halide lamp (abbreviation Metal halogen lamp) electric ballast is a kind of power electronic system by the control of dsp controller circuit, startup and two kinds of patterns of operate as normal of electric ballast in the software control that moves on DSP, the dsp controller circuit is being brought into play leading role, fail safe, stability and service behaviour thereof when directly affecting Metal halogen lamp work.
In present high power (multikilowatt) Metal halogen lamp,, generally all lack the control of Power Factor Correction Control and power fluting even if with the electric ballast of digital control.Based on this electric ballast, there is following defective in its controlling party rule: controlled function is limited, is applied to usually in the low power electron rectifier; Ballast lacks the control of power factor correction at the electrical network incoming end, so harmonic wave is very big, and electric power system has been caused harmonic pollution; In the dead band of inverter, intergrade Buck translation circuit output voltage can increase sharply, and makes the voltage stress of switching device and passive device increase, and causes danger.
Summary of the invention
Technical problem to be solved by this invention is, overcomes deficiency of the prior art, and a kind of control method of full digital high-power metal halide lamp electronic ballast is provided.
For solving the problems of the technologies described above, solution provided by the invention is: the control procedure of electric ballast is divided into start-up course and the steady operation process is carried out the control of different mode.In start procedure of electric ballast, each circuit start in the different moment to electric ballast, pfc circuit is adopted soft start control, overvoltage and the overcurrent to switching component impacts in the cooperation solution ballast start-up course like this, to reach the purpose of clean boot and reasonable startup ballast.
The control method of the full digital high-power metal halide lamp electronic ballast among the present invention comprises the control of start-up course of electric ballast and the control of steady operation:
In the start-up course of described electric ballast, may further comprise the steps:
The A.DSP controller circuitry judges whether to be cycle interruption, then carries out next step in this way;
The B.DSP controller circuitry judges whether then to carry out next step in this way into the circuit of power factor correction soft start moment;
Whether the C.DSP controller circuitry judges the set of circuit of power factor correction soft start sign, then carries out next step in this way;
The D.DSP controller circuitry judges whether to the Buck translation circuit and the single-phase full bridge inverter circuit starts and lamp triggers constantly, then carries out next step in this way;
The E.DSP controller circuitry is judged that the Buck translation circuit starts and is indicated whether set, then carries out next step in this way;
The F.DSP controller circuitry judges whether to cancel constantly for the lamp triggering signal, then carries out next step in this way;
The G.DSP controller circuitry is closed the cycle interruption program;
In the steady operation of described electric ballast, may further comprise the steps:
Whether a, dsp controller circuit judges are that analog-to-digital conversion interrupts then carrying out next step in this way constantly;
B, dsp controller circuit are carried out the analog-to-digital conversion interrupt routine, enter sampling routine, circuit of power factor correction input voltage, circuit of power factor correction input current, circuit of power factor correction output voltage, Buck translation circuit output voltage, Buck translation circuit output current and power adjustments signal are sampled;
Whether c, dsp controller circuit judges enter the protection control program, then carry out next step in this way;
Whether the control of ingoing power factor correcting circuit soft start is then carried out constantly in this way for d, dsp controller circuit judges;
Whether the normal steady operation control of ingoing power factor correcting circuit is then carried out constantly in this way for e, dsp controller circuit judges;
Whether f, dsp controller circuit judges enter Buck translation circuit start-up control constantly, then carry out next step in this way;
G, dsp controller circuit execution Buck translation circuit control program calculate real-time power output, and judge and carry out constant current control and execution, or control of permanent power and execution, or control of power fluting and execution, or the Power Regulation brightness adjustment control.
As a kind of improvement, the present invention also comprises: the dsp controller circuit is according to the sampled value of sampling gained among the step b, judges whether carry out overvoltage, overcurrent or under-voltage protection control.
As a kind of improvement, in whole starting process, the dsp controller circuit is realized constant current control to the Buck translation circuit; In steady state operation, the dsp controller circuit is realized permanent power control to the Buck translation circuit.
As a kind of improvement, in described step b, less than 310V, then circuit of power factor correction is taked soft start control as the circuit of power factor correction output voltage values; Greater than 310V, then circuit of power factor correction is taked Power Factor Correction Control as this output voltage values.
As a kind of improvement, in electric ballast steady operation process, when the single-phase full bridge inverter circuit enters the brachium pontis dead band, the dsp controller circuit reduces the power output of Buck translation circuit earlier, then increase its power output, the power output that is the Buck translation circuit is " V-type " Changing Pattern after single-phase full bridge inverter circuit brachium pontis enters the dead band, the dsp controller circuit is done fluting control to the power output of Buck translation circuit in single-phase full bridge inverter circuit dead band.
As a kind of improvement, in start-up course, cycle interruption and analog-to-digital conversion are interrupted paired running, and cycle interruption is set is high priority; After start-up course finished, the dsp controller circuit was closed cycle interruption.
As a kind of improvement, the one-off pattern number conversion takes place and interrupts in the every 40us of described dsp controller circuit, and after each interruption took place, the dsp controller circuit entered the analog-to-digital conversion interrupt handling routine.
As a kind of improvement, described dsp controller circuit has three hardware timer T1, T3 and T4; Wherein timer T1 is as the time base of the PWM output signal of the drive signal of circuit of power factor correction and Buck translation circuit, in the steady operation process of electric ballast as analog-to-digital starter; Timer T3 is as the time base of the PWM output signal of single-phase full bridge inverter circuit; Timer T4 is as the starter of the start-up course of electric ballast.
As a kind of improvement, when timer T1 underflow, start analog-to-digital conversion; After analog-to-digital conversion finishes, enter the analog-to-digital conversion interrupt routine.
As a kind of improvement, in start-up course, the every 20ms of the T4 cycle interruption of dsp controller circuit takes place once, and the dsp controller circuit of having no progeny at every turn advancing carries out Interrupt Process.
Compared with prior art, the beneficial effect that the present invention brought is:
In the high power metal halogen lamp electric ballast circuit, circuit of power factor correction input voltage sample circuit, circuit of power factor correction input current sample circuit, circuit of power factor correction output voltage sampling circuit, Buck output voltage sampling circuit, Buck output current sample circuit and power are adjusted startup and control circuit, Buck translation circuit, single-phase full bridge inverter circuit, the protective circuit of signals sampling circuit, ballast starting circuit, circuit of power factor correction and are controlled by the dsp controller circuit is unified.By drives interrupts is carried out in the setting of the hardware counter in the dsp controller circuit and the setting of ADC, ADC of the every driving of dsp controller circuit interrupts, then successively corresponding circuit module in the circuit is controlled and carried out, thereby finish the control of startup, the shutoff of Metal halogen lamp, permanent power work, the work of " V " type fluting.Control method of the present invention is fairly simple on program, and is modified easily, upgrades and transplants, thereby has alleviated developer's workload.
The employing dsp controller circuit that the present invention proposes is as the core controller of ballast, its controlled function is powerful, can be applicable to the control of high-power electronic ballast device, the input stage of ballast is carried out Power Factor Correction Control, reduce harmonic pollution electrical network; The Buck DC transfer circuit is carried out the control of power fluting, thereby reach the purpose of protection power switch and passive component.The dsp controller circuit has 16 road ADC sampling and 16 road PWM usually in addition, makes Circuit Design simple, but the reliability of elevator system and reduction hardware cost.
Description of drawings
Fig. 1 is circuit theory diagrams of the present invention;
Fig. 2 is a main program flow chart of the present invention, metal halogen lamp electric ballast system control flow chart;
Fig. 3 is an interrupt service routine flow chart of the present invention, power factor correction (PFC) circuit control program flow chart;
Fig. 4 is an interrupt service routine flow chart of the present invention, Buck translation circuit control program flow chart;
Fig. 5 is Buck translation circuit control system schematic diagram among the present invention;
Fig. 6 is the power V-type fluting control schematic diagram of Buck translation circuit among the present invention.
Embodiment
The invention will be further described below in conjunction with Figure of description.
As shown in Figure 1; digital high power metal halogen lamp electric ballast among the present invention comprises full bridge rectifier 1; circuit of power factor correction 2; Buck translation circuit 3; single-phase full bridge inverter circuit 4; start-up circuit 5; PFC input voltage sample circuit 7; PFC input current sample circuit 8; PFC output voltage sampling circuit 9; Buck output current sample circuit 10; Buck output voltage sampling circuit 11; protective circuit 12; protective circuit 13; given power samples circuit 14; sampled signal modulate circuit 15; isolated drive circuit 16; auxiliary power circuit 17 and dsp controller circuit 18.
Described full bridge rectifier 1 is connected with auxiliary power circuit 17, and described auxiliary power circuit 17 is connected respectively with dsp controller circuit 18, sampled signal modulate circuit 15 and isolated drive circuit 16.Described circuit of power factor correction 2 is connected with the output of full bridge rectifier 1, and described Buck translation circuit 3 is connected with the output of described circuit of power factor correction 2.The output of described Buck translation circuit 3 is connected with start-up circuit 5, and this start-up circuit 5 is connected with Metal halogen lamp 6.1 pair of civil power of full bridge rectifier carries out rectification, and the output voltage and the electric current of 2 pairs of full bridge rectifiers 1 of circuit of power factor correction carry out power factor correction, and output voltage is controlled, and obtains the required direct voltage of Buck translation circuit 3.Described Buck translation circuit 3 outputs are connected with single-phase full bridge inverter circuit 4 inputs, single-phase full bridge inverter circuit 4 is connected with Metal halogen lamp 6, after Metal halogen lamp was breakdown, its effect was equivalent to a heavy load, and the direct voltage of Buck translation circuit 3 outputs is pulled down to the normal working voltage of Metal halogen lamp.
Described dsp controller circuit 18 is provided with three hardware timer T1, T3 and T4, the PWM delivery outlet of the PWM delivery outlet of 2 25kHz and 2 low frequencies (50Hz, 60Hz or 70Hz), 6 ADC input ports.The T1 timer adopts 1 frequency division, the T1 timer is as the time base of the PWM output signal of the drive signal of circuit of power factor correction 2 and Buck translation circuit 3, the T3 timer adopts 32 frequency divisions, the T3 timer is as the time base of the PWM output signal of single-phase full bridge inverter circuit 4, the T4 timer adopts 20ms as timing cycle, the soft start of T4 timing ballast.
Described circuit of power factor correction 2 inputs are provided with PFC input voltage sample circuit 7 and PFC input current sample circuit 8, described circuit of power factor correction 2 outputs are provided with PFC output voltage sampling circuit 9, and described Buck translation circuit 3 outputs are provided with Buck output voltage sampling circuit 11 and Buck output current sample circuit 10; Described PFC input voltage sample circuit 7, PFC input current sample circuit 8, PFC output voltage sampling circuit 9, Buck output voltage sampling circuit 11 and output current sample circuit 10, given power samples circuit 14 all are connected with 6 road ADC ports of dsp controller circuit 18 by sampled signal modulate circuit 15.4 road PWM ports of dsp controller circuit 18 are connected with isolated drive circuit 16.Isolated drive circuit 16 is connected with Buck translation circuit 3 with circuit of power factor correction 2 by the drive signal of one road 25kHz respectively, and isolated drive circuit is connected with single-phase full bridge inverter circuit 4 by 2 road low frequencies (50Hz, 60Hz or 70Hz) drive signal.Circuit of power factor correction 2 inputs are connected with protective circuit 12, and start-up circuit 5 inputs are connected with protective circuit 13.
Shown in Fig. 2,3, when ballast works on power, at first execution in step 101-begins initialization, timer in the dsp controller circuit 18 (not indicating) T1, T3 and T4 are changed to 0, and all flag bits clear 0, and T1PWM, PWM1, PWM7 and PWM8 initialization are forced to low, finish all the other initialization settings of software simultaneously.The every operation 20ms of system, dsp controller circuit 18 is carried out the T4 interrupt routine: counter T adds 1, and then dsp controller circuit 18 execution in step 205 judge whether counter T has reached 25, then interrupt if not returning; If then dsp controller circuit 18 continues to carry out 206 and judges PFC soft start flag set not, then continue to carry out 114 if not and put PFC soft start sign and interrupt returning; Judge whether counter T has reached 65 if then continue to carry out 207, then interrupt if not returning; If then dsp controller circuit 18 is carried out 208 and judged that the Buck translation circuits start flag set not, then continue to carry out 115 if not and put the Buck translation circuit and start sign and lamp triggering signal and interruption and return; Judge whether counter T has reached 100 if then continue to carry out 209, then interrupt if not returning; If carry out 116, cancel the lamp triggering signal, then continue to carry out 001, close T4 cycle interruption program.Dsp controller circuit 18 T4 interrupt being set to high-priority interrupt.
The definition of table 1ST_FLAG correlating markings position:
| The position | ??4 | ??3 | ??2 | ?1 | ??0 |
| Definition | Lamp triggers and allows | Buck translation circuit, single-phase full bridge inverter circuit allow | PFC normally starts permission | The PFC soft start allows | Master switch |
| Working procedure | Buck translation circuit control program | The PFC control program | PFC soft start program |
Analog-to-digital conversion ADC interrupts being set to low priority interrupt, and it interrupts program package draws together PFC soft start program, PFC control program and Buck translation circuit control program.The corresponding opening process of above-mentioned three programs is controlled by register ST_FLAG corresponding positions, and is as shown in table 1.
T1 underflow interrupt identification starts timer, timing cycle 40us.Behind system initialization; every operation 40us; enter the ADC interrupt routine: carry out the sampling of 102-PFC input voltage; then carrying out the 103-PFC input current samples; then carry out the sampling of 104-PFC output voltage; then carry out the sampling of 105-Buck output voltage; then carry out the sampling of 106-Buck output current; then carry out the given power samples of 107-; then carry out the clear ADC interrupt identification of 108-, then carry out the 109-defence program, then carry out 202 and judge whether the PFC soft start; then carry out the 111-PFC control program if not, if then carry out 110-PFC soft start program.After executing 111 or 110, carry out 203-and judge that Buck starts, then interrupt if not returning; If then carry out the 112-Buck control program, then interrupt returning.
The cycle interruption priority of T4 is higher than analog-to-digital conversion ADC interrupts, and system determines every 20ms to enter interruption by the T4 cycle interruption in starting running, and counts by counter T, whenever advance the T4 cycle interruption one time, T adds 1, when T is increased to 25, PFC is started flag set, when T is increased to 65, the Buck translation circuit is started sign and the set of lamp triggering signal, when T is increased to 100, the lamp triggering signal is cancelled, and close the T4 cycle interruption, system starting process finishes.When ADC interrupts taking place, at first carry out sampling routine, follow clear ADC interrupt identification, enter defence program then; Then judge whether to carry out soft start, and carry out corresponding program; Then judge whether to carry out Buck and start, and carry out corresponding program.ADC interruption and T4 interrupt walking abreast in start-up course, but the ADC priority of interrupt is lower than the T4 cycle interruption, and therefore in start-up course, the ADC that has precedence over that T4 interrupts interrupts; After start-up course finished, system had only ADC to interrupt.
After the system finishing start-up course, software is carried out PFC control program and Buck control program.The PFC control program as shown in Figure 3, the Buck control program is as shown in Figure 4.
As Fig. 3, enter the PFC control program, it is effectively low that 18 execution 301 of dsp controller circuit are provided with T1PWM, then carries out 302 and whether judge the PFC electric current greater than 36A, if it is low then to carry out the 304T1PWM pressure, then finishes the PFC control flow; If 302 are judged as otherwise carry out 303 and whether judge the PFC output voltage greater than 360V, if it is low then to carry out the 304T1PWM pressure; If 303 judged results are not, then dsp controller circuit 18 continues to carry out the control of 305-PFC Voltage loop, then carries out the 306-PFC current loop control, and then finishes the PFC control flow.As Fig. 4, enter the Buck control program, it is effectively low that 18 execution 401 of dsp controller circuit are provided with PWM1, then carries out 402 and whether judge Buck translation circuit output current greater than 32A, forces low if then carry out 403-PWM1; If 402 are judged as otherwise carry out 404 and judge whether soft start finishes, then carrying out 408-setting reference power value if not is the soft start value, then carries out the 406-Buck power control loop, then carries out the 407-Buck current regulator, then finishes the Buck control flow; If carry out 404 judged results for being that then then carrying out 405-setting reference power is set-point, then carries out the 406-Buck power control loop, then carries out the 407-Buck current regulator, then finishes the control flow of Buck translation circuit.
Dsp controller circuit shown in Figure 3 carries out 304, and the output voltage values of circuit of power factor correction is carried out closed-loop control, adopts the PI controlling schemes, and output voltage is 340V; Then the dsp controller circuit carries out 305 as shown in Figure 3, the PFC input current is carried out current closed-loop control, adopt the PI controlling schemes, the product of the voltage close loop control output valve with 304 and the sampled value of PFC input voltage carries out the modulation of PI ring then as the reference value of PFC input current to the PFC input current value.As shown in Figure 3, done the control of PFC peak current in PFC program beginning, when the line voltage effective value is 180V, during power output 4kW, PFC input current peak value is about 32A, is 36A so set PFC current peak controlling value.In addition also done PFC output voltage overvoltage protection control, when PFC output voltage during greater than 360V, the T1PWM signal is forced to low, and pfc circuit is protected.Because having added the above-mentioned T1PWM of setting is forced to low program, so when entering the PFC program, T1PWM is set at every turn for effectively low, to open T1PWM, as 301 of Fig. 3.
As Fig. 4, dsp controller circuit 18 is carried out the 406-Buck power control loop, then carries out the 407-Buck current regulator, and 406 and 407 control principle as shown in Figure 5.
Pref is the reference output power of Buck translation circuit among Fig. 5, I
LBe the electric current of the outputting inductance of Buck translation circuit, V
oIt is the output voltage values of Buck translation circuit.Dsp controller circuit 18 is by 105 and 106 of execution graph 2, output voltage and electric current are sampled, carry out 406 and 407 at Fig. 4 Buck control program then, carry out the power ring modulation earlier, carry out the electric current loop modulation again: the real output that calculates the Buck translation circuit, make comparisons with reference power, carry out PI control, amplitude limit is carried out in this output; With the reference of power ring output as electric current loop, compare with output current value, carry out PI control, and amplitude limit is carried out in the output of this PI control, go turning on and off of control switch pipe then.Metal halide lamp starts to reach from puncture and is the start-up course of Metal halogen lamp in this section of setting power period, and power ring is saturated, and its output variable amplitude limit at 28A, is carried out constant current control.When the power of Metal halogen lamp reached set point, power ring began to move back saturated, and the output current of Buck translation circuit begins to descend, until the steady operation electric current of lamp is realized normal modulation.The Buck start-up routine begins to have the control of Buck output current peak value, then is provided with the Buck translation circuit soft start of 61 switch periods, and in this soft start-up process, the set point of Buck translation circuit power output increases gradually, but is no more than reference power value.
In addition, when the brachium pontis of single-phase full bridge inverter circuit 4 switches, set the dead band, for reducing during the dead band impact, the power control program of Buck translation circuit has been designed the control of power fluting V-type switching tube for preventing bridge arm direct pass.The power output fluting of Buck translation circuit increases after promptly output work takes the lead in reducing again.As shown in Figure 6,, reduce the output reference power of Buck earlier, increase to given reference power value again at the brachium pontis generation switching tube switching instant of single-phase full bridge inverter circuit 4.Suppose that moment t1 is the zero hour of fluting among Fig. 6, t2 is the finish time of fluting, and t2-t1 section definition during this period of time is the width of fluting; Suppose that Pref is specified given reference power value among Fig. 6, Pref ' is an interior minimum reference power value between slotted zones, and then Pref-Pref ' is defined as the degree of depth of fluting.For preventing the back Metal halogen lamp generation scintillation of slotting, need the degree of depth and the width of appropriate design fluting, through debugging repeatedly, the width of fluting is 320us.Need to illustrate different frequency periodic quantity and comparison value in addition, fluting is constantly all inequality.
The cycle that T4 sets in the main program flow shown in Figure 2 can be selected arbitrarily, PFC soft start flag set, Buck start flag bit and the moment point that the set of lamp triggering signal, lamp triggering signal are cancelled can be selected with different in the program circuit, as long as the assurance ballast can be normally and clean boot.The cycle of T1 not necessarily will be selected 40us by the switch periods decision in addition, but will meet the switch periods conditional request of circuit of power factor correction 2 and Buck translation circuit 3 selected power components.The cycle of T3 timer is by metal halide lamp 6 decisions.The time reference of T1, T3 and three counters of T4 is by the crystal oscillator decision of dsp controller circuit 18.
Should be noted that employed specific term should not be used to be illustrated in when explanation some feature of the present invention or scheme redefines this term here with restriction of the present invention some certain features, feature or the scheme relevant with this term.In a word, should be with the terminological interpretation in the claims of enclosing, used for not limiting the invention to disclosed specific embodiment in the specification, unless above-mentioned detailed description part defines these terms clearly.Therefore, actual range of the present invention not only comprises the disclosed embodiments, also is included in to implement or carry out all equivalents of the present invention under claims.
Claims (10)
1. the control method of a full digital high-power metal halide lamp electronic ballast comprises the control of start-up course of electric ballast and the control of steady operation, it is characterized in that:
In the start-up course of described electric ballast, may further comprise the steps:
The A.DSP controller circuitry judges whether to be cycle interruption, then carries out next step in this way;
The B.DSP controller circuitry judges whether then to carry out next step in this way into the circuit of power factor correction soft start moment;
Whether the C.DSP controller circuitry judges the set of circuit of power factor correction soft start sign, then carries out next step in this way;
The D.DSP controller circuitry judges whether to the Buck translation circuit and the single-phase full bridge inverter circuit starts and lamp triggers constantly, then carries out next step in this way;
The E.DSP controller circuitry is judged that the Buck translation circuit starts and is indicated whether set, then carries out next step in this way;
The F.DSP controller circuitry judges whether to cancel constantly for the lamp triggering signal, then carries out next step in this way;
The G.DSP controller circuitry is closed the cycle interruption program;
In the steady operation of described electric ballast, may further comprise the steps:
Whether a, dsp controller circuit judges are that analog-to-digital conversion interrupts then carrying out next step in this way constantly;
B, dsp controller circuit are carried out the analog-to-digital conversion interrupt routine, enter sampling routine, circuit of power factor correction input voltage, circuit of power factor correction input current, circuit of power factor correction output voltage, Buck translation circuit output voltage, Buck translation circuit output current and power adjustments signal are sampled;
Whether c, dsp controller circuit judges enter the protection control program, then carry out next step in this way;
Whether the control of ingoing power factor correcting circuit soft start is then carried out constantly in this way for d, dsp controller circuit judges;
Whether the normal steady operation control of ingoing power factor correcting circuit is then carried out constantly in this way for e, dsp controller circuit judges;
Whether f, dsp controller circuit judges enter Buck translation circuit start-up control constantly, then carry out next step in this way;
G, dsp controller circuit execution Buck translation circuit control program calculate real-time power output, and judge and carry out constant current control and execution, or control of permanent power and execution, or control of power fluting and execution, or the Power Regulation brightness adjustment control.
2. control method according to claim 1 is characterized in that, also comprises: the dsp controller circuit is according to the sampled value of sampling gained among the step b, judges whether carry out overvoltage, overcurrent or under-voltage protection control.
3. control method according to claim 1 is characterized in that, in whole starting process, the dsp controller circuit is realized constant current control to the Buck translation circuit; In steady state operation, the dsp controller circuit is realized permanent power control to the Buck translation circuit.
4. control method according to claim 1 is characterized in that, in described step b, less than 310V, then circuit of power factor correction is taked soft start control as the circuit of power factor correction output voltage values; Greater than 310V, then circuit of power factor correction is taked Power Factor Correction Control as this output voltage values.
5. control method according to claim 1, it is characterized in that, in electric ballast steady operation process, when the single-phase full bridge inverter circuit enters the brachium pontis dead band, the dsp controller circuit reduces the power output of Buck translation circuit earlier, then increase its power output, the power output that is the Buck translation circuit is " V-type " Changing Pattern after the brachium pontis of single-phase full bridge inverter circuit enters the dead band, the dsp controller circuit is done fluting control to the power output of Buck translation circuit in the dead band of single-phase full bridge inverter circuit.
6. according to the control method described in any one of the claim 1 to 5, it is characterized in that in start-up course, cycle interruption and analog-to-digital conversion are interrupted paired running, and cycle interruption is set is high priority; After start-up course finished, the dsp controller circuit was closed cycle interruption.
7. according to the control method described in any one of the claim 1 to 5, it is characterized in that the every 40us of described dsp controller circuit the one-off pattern number conversion takes place interrupts, each interrupt taking place after, the dsp controller circuit enters the analog-to-digital conversion interrupt handling routine.
8. according to the control method described in any one of the claim 1 to 5, it is characterized in that described dsp controller circuit has three hardware timer T1, T3 and T4; Wherein timer T1 is as the time base of the PWM output signal of the drive signal of circuit of power factor correction and Buck translation circuit, in the steady operation process of electric ballast as analog-to-digital starter; Timer T3 is as the time base of the PWM output signal of single-phase full bridge inverter circuit; Timer T4 is as the starter of the start-up course of electric ballast.
9. control method according to claim 8 is characterized in that, when timer T1 underflow, starts analog-to-digital conversion; After analog-to-digital conversion finishes, enter the analog-to-digital conversion interrupt routine.
10. control method according to claim 8 is characterized in that, in start-up course, the every 20ms of the timer T4 cycle interruption of dsp controller circuit takes place once, and the dsp controller circuit of having no progeny at every turn advancing carries out Interrupt Process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102015361A CN101848588B (en) | 2010-06-12 | 2010-06-12 | Control method of full digital high-power metal halide lamp electronic ballast |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102015361A CN101848588B (en) | 2010-06-12 | 2010-06-12 | Control method of full digital high-power metal halide lamp electronic ballast |
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| Publication Number | Publication Date |
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| CN101848588A true CN101848588A (en) | 2010-09-29 |
| CN101848588B CN101848588B (en) | 2013-01-02 |
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| CN2010102015361A Expired - Fee Related CN101848588B (en) | 2010-06-12 | 2010-06-12 | Control method of full digital high-power metal halide lamp electronic ballast |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497705A (en) * | 2011-12-14 | 2012-06-13 | 西安华雷船舶实业有限公司 | Lamp energy conservation control method and energy-conservation circuit thereof |
| CN103647459A (en) * | 2013-11-22 | 2014-03-19 | 肖红军 | High-frequency-link parallel inverter with no connection wire |
| CN108667322A (en) * | 2018-05-24 | 2018-10-16 | 中车青岛四方车辆研究所有限公司 | single-phase rectifier control method and system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1596057A (en) * | 2004-06-30 | 2005-03-16 | 哈尔滨工业大学 | Digital electronic ballast of high pressure gas discharge lamp and digital control method therefor |
| US20070152600A1 (en) * | 2005-12-29 | 2007-07-05 | Nerone Louis R | Output short circuit protection for electronic ballasts |
-
2010
- 2010-06-12 CN CN2010102015361A patent/CN101848588B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1596057A (en) * | 2004-06-30 | 2005-03-16 | 哈尔滨工业大学 | Digital electronic ballast of high pressure gas discharge lamp and digital control method therefor |
| US20070152600A1 (en) * | 2005-12-29 | 2007-07-05 | Nerone Louis R | Output short circuit protection for electronic ballasts |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497705A (en) * | 2011-12-14 | 2012-06-13 | 西安华雷船舶实业有限公司 | Lamp energy conservation control method and energy-conservation circuit thereof |
| CN102497705B (en) * | 2011-12-14 | 2014-04-02 | 西安华雷船舶实业有限公司 | Lamp energy conservation control method and energy-conservation circuit thereof |
| CN103647459A (en) * | 2013-11-22 | 2014-03-19 | 肖红军 | High-frequency-link parallel inverter with no connection wire |
| CN108667322A (en) * | 2018-05-24 | 2018-10-16 | 中车青岛四方车辆研究所有限公司 | single-phase rectifier control method and system |
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| CN101848588B (en) | 2013-01-02 |
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