CN101842979A - Programmable gain circuit - Google Patents
Programmable gain circuit Download PDFInfo
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- CN101842979A CN101842979A CN200880113762A CN200880113762A CN101842979A CN 101842979 A CN101842979 A CN 101842979A CN 200880113762 A CN200880113762 A CN 200880113762A CN 200880113762 A CN200880113762 A CN 200880113762A CN 101842979 A CN101842979 A CN 101842979A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/001—Digital control of analog signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/24—Frequency-independent attenuators
Abstract
A programmable gain circuit suitable for a programmable gain amplifier is described. In one design, the programmable gain circuit includes multiple attenuation circuits coupled in series. Each attenuation circuit operates in a first mode or a second mode, attenuates an input signal in the first mode, and passes the input signal in the second mode. The multiple attenuation circuits may provide the same or different amounts of attenuation. The multiple attenuation circuits may include binary decoded attenuation circuits and/or thermometer decoded attenuation circuits. In one design, each attenuation circuit includes a divider circuit and at least one switch. The switch(es) select the first mode or the second mode. The divider circuit attenuates an input signal in the first mode and passes the input signal in the second mode. The programmable gain circuit may have a predetermined input impedance and a predetermined output impedance for all gain settings.
Description
Technical field
The present invention generally relates to electronic equipment, and more particularly relates to a kind of gain circuitry and a kind of amplifier.
Background technology
Amplifier is generally used for amplifying signal to obtain required signal level.Amplifier is widely used in various application, for example communicates by letter, calculates, networking, electronic equipment for consumption etc.For instance, in radio communication device, amplifier can be used for drive headphones, loud speaker, external device (ED) etc.
Amplifier can have various requirement.For instance, can require amplifier that large-scale gain is provided and have I programming gain step size.May expect that also amplifier has sane performance and takies little layout areas to reduce cost.
Summary of the invention
A kind of be adapted at use and the suitable programmable gain circuit that uses with other circuit in the programmable gain amplifier are described herein.In a design, described programmable gain circuit comprises a plurality of attenuator circuits of series coupled.Each attenuator circuit can be operated in first pattern or second pattern, and the input signal and transmit (or unattenuated) described input signal in described second pattern of can decaying in described first pattern.Described a plurality of attenuator circuit can provide identical or different attenuation.Can obtain a plurality of gain settings with operation in described first pattern or described second pattern by each that control in described a plurality of attenuator circuit corresponding to the differential declines total amount.
In a design, described a plurality of attenuator circuits comprise the attenuator circuit of one group of binary decoded attenuation circuits and one group of thermometer decoder.Described binary decoded attenuation circuits can provide different attenuations (for example, the multiple with 2 is a unit with decibel (dB)), and can select by arbitrary order.Can determine described selected binary decoded attenuation circuits based on selected gain setting.But the attenuator circuit of described thermometer decoder can provide equal attenuation and predetermined order to select.Can determine the number of selected temperature meter decoded attenuation circuits based on described selected gain setting.
Described programmable gain circuit can have predetermined input impedance and predetermined output impedance at all described gain settings.Amplifier can be coupled to described programmable gain circuit and can provide fixed gain based on the described output impedance and the feedback resistor of described programmable gain circuit.
In a design, each attenuator circuit comprises divider circuit and at least one switch.Described at least one switch is that described attenuator circuit is selected described first pattern or described second pattern.In described first pattern, decay input signal and in described second pattern, transmit described input signal of described divider circuit.Described divider circuit can be by enforcements such as T resistor pad, π resistor pad, and both can have fixedly input impedance and fixedly output impedance at described first pattern and described second pattern.In a design, described at least one switch comprises single-pole double throw (SPDT) switch, and described single-pole double throw (SPDT) switch is directed to intermediate current ground connection or is directed to the output of described programmable gain circuit described second pattern from described divider circuit in described first pattern.In another design, described at least one switch comprises first switch and second switch.Described first switch is crossed over the input of described divider circuit and output and is coupled.Described second switch is coupled between the Centronics port and ground connection of described divider circuit.Described first switch and described second switch are enabled described divider circuit at described first pattern and at the described divider circuit of the described second pattern short circuit.
Various aspects of the present invention and feature are hereinafter described in further detail.
Description of drawings
Figure 1A and 1B show the variable gain amplifier that has the variable feedback resistor and have variable input resistor respectively.
Fig. 2 shows the programmable gain amplifier with programmable gain circuit.
Fig. 3 A shows three attenuator circuits with T resistance pad to 3C.
Fig. 4 shows the attenuator circuit with π resistance pad.
Fig. 5 shows another attenuator circuit with T resistance pad.
Fig. 6 shows the programmable gain circuit with two 6dB attenuator circuits.
Fig. 7 shows the programmable gain circuit with a plurality of attenuator circuits.
Fig. 8 shows the difference programmable gain amplifier with programmable gain circuit.
Fig. 9 shows the process that is used for conditioning signal.
The block diagram of Figure 10 display radio communicator.
Embodiment
Figure 1A shows the schematic diagram of the variable gain amplifier 100 with variable feedback resistor.In amplifier 100, resistor 112 and 114 has and receives V respectively
InpAnd V
InnAn end of signal and the other end that is coupled to the noninverting and anti-phase input of operational amplifier (op-amp) 110 respectively.V
InpWith V
InnSignal forms the differential input signal of amplifier 100.Resistor 116 has an other end of holding and be coupled to circuit ground of the noninverting input of being coupled to operational amplifier 110.Resistor 118 has an other end of holding and be coupled to the output of operational amplifier 110 of the anti-phase input of being coupled to operational amplifier 110.Resistor 112 and 114 has fixed value R
In, and resistor 116 and 118 has variable value R
Fb Operational amplifier 110 provides signal to amplify.Resistor 112 to 118 is determined the gain G of amplifier 100, and described gain G can be expressed as:
In general and as used herein, gain can be: (i) equal 1 by linear unit, it is 0dB by log unit, (ii) presses linear unit greater than 1, or (iii) presses linear unit less than 1.Amplify and postiive gain (is unit with dB) corresponding to signal greater than 1 gain by linear unit.By linear unit less than 1 gain corresponding to signal attenuation and negative gain (is unit with dB).Decay to negative gain, so the decay of xdB is equivalent to-gain of xdB.
Figure 1B shows the schematic diagram of the variable gain amplifier 150 with variable input resistor.In amplifier 150, operational amplifier 160 and resistor 162,164,166 and 168 respectively with Figure 1A in the identical mode of operational amplifier 110 and resistor 112,114,116 and 118 be coupled. Resistor 162 and 164 has variable value R
In, and resistor 166 and 168 has fixed value R
FbAs shown in equation (1), can determine the gain of amplifier 150.Because resistor 166 and 168 has fixed value, so the spuious parasitics in the feedback loop can not change with the gain G that changes, and do not have extra stability and change and can produce because of making described change in gain.Yet (for example, 54dB), resistor 162 and 164 can make that maximum is the manyfold (for example, 500 times) of minimum value through design in order to obtain wide gain ranging.Big resistor ratio can make the signal integrity degradation and can further require big resistor area.
On the one hand, programmable gain amplifier can be implemented with the programmable gain circuit of fixed gain amplifier by heel.Described fixed gain amplifier can have fixed value R
FbAnd can therefore avoid spuious parasitics that the effect of the stability of feedback loop is changed.Described programmable gain circuit can be by about log
2(N) individual level is supported N different gain setting, and wherein N can be arbitrary integer value.Described programmable gain circuit also can be all N gain setting fixedly input impedance and fixedly output impedance is provided.
Fig. 2 shows the schematic diagram of the design of programmable gain amplifier 200.In amplifier 200, programmable gain circuit 210 has the V that reception is used for differential input signal
InpAnd V
InnThe difference output of the noninverting and anti-phase input of operational amplifier 220 is imported and be coupled to the difference of signal.Resistor 222 has an other end of holding and be coupled to circuit ground of the noninverting input of being coupled to operational amplifier 220.Resistor 224 is coupled between the anti-phase input and output of operational amplifier 220. Resistor 222 and 224 has fixed value R
Fb Operational amplifier 220 provides single-ended output signal V
Out
In general, programmable gain circuit can provide arbitrary gain ranging and support arbitrary number gain setting.Programmable gain circuit can use with amplifier, and for example operational amplifier (for example, as shown in Figure 2), and also can use with other circuit.
Programmable gain circuit can be implemented by one or more attenuator circuits.Each attenuator circuit can provide the particular decay amount when chosen, and can not provide decay when being bypassed.By suitable termination the time, each attenuator circuit also can have fixedly input impedance R
0Reach fixedly output impedance R
0Input and output impedance through coupling can allow the arbitrary number of a series coupled attenuator circuit.
Fig. 3 A shows the schematic diagram of the design of attenuator circuit 320.Input signal source 310 provides V
InThe input voltage of=2V and I
InThe input current of=I, wherein V and I can be any suitable values and can change in time.Input resistor 312 has a value R
0And be coupled between the input of signal source 310 and attenuator circuit 320.Output resistor 314 also has a value R
0And be coupled between the output and signal source output 316 of attenuator circuit 320.The low impedance circuit that 316 pairs of attenuator circuits 320 of signal source can be coupled to (for example, the anti-phase input of operational amplifier) is carried out modeling.The output of signal source 316 can be considered to virtual ground.
Selectable resistors value R
1, R
2And R
3Think that divider circuit 330 provides required attenuation G
AttenIn addition, can select R
1, R
2And R
3, make and work as with R
0When the input of suitable termination attenuator circuit 320 and output, attenuator circuit 320 has input impedance R
0And output impedance R
0, as shown in Fig. 3 A.
The row 2 of table 1 have provided the R that the design of 6dB decay is provided at divider circuit 330 wherein
1, R
2And R
3Value.Row 2 give the various voltages of institute's mark among Fig. 3 A and the value of electric current.
Table 1-is at the 6dB attenuator
| Parameter | Attenuator |
|
|
Attenuator circuit 324 | Attenuator circuit 324 | ||
| Gain | ??-6dB | ??0dB | ??-6dB | ??0dB | ??-6dB | ||
| ??R 1、R 2 | ??R 0/3 | ??R 0/3 | ??R 0/3 | ??R 0/3 | ??R 0/3 | ||
| ??R 3 | ??4R 0/3 | ??4R 0/3 | ??4R 0/3 | ??4R 0/3 | ??4R 0/3 | ||
| ??V 1 | ??V | ??3V/2 | ??V | ??V | ??V | ||
| ??V 2 | ??V/2 | ??V | ??V/2 | ??V/2 | ??V/2 | ||
| ??V 3 | ??0 | ??2V | ??0 | ??0 | ??0 | ||
| ??I 1 | ??I | ??I/2 | ??I | ??I | ??I | ||
| ??I 2 | ??I/2 | ??I | ??I/2 | ??I/2 | ??I/2 | ||
| ??I 3 | ??I/2 | ??-I/2 | ??I/2 | ??I/2 | ??I/2 | ||
| ??I out | ??I/2 | ??I | ??I/2 | ??I | ??I/2 |
As shown in the row 2 of table 1, pass the output current I of virtual ground
OutBe input current I from signal source 310
InHalf of=I (or-6dB).G
AttenOther value (for example, 1.5dB, 3dB, 12dB etc.) can be by R
1, R
2And R
3Other be worth and obtain, also can select R
1, R
2And R
3Think that attenuator circuit provides fixing input and output impedance R
0
Can regard attenuator circuit 320 as current attenuator, it can be with input current I
1Some electric current as electric current I
2Be directed to output port and with I
1Remainder as electric current I
3Be directed to Centronics port.Output current I
2With input current I
1Ratio equal the G that decays
AttenAnd depend on R
1, R
2And R
3Set point value and R
0Set point value.Can should be used for selecting R based on what wherein use attenuator circuit 320
0, and R
0Application can equal 50 or 75 Europe at radio frequency (RF), can equal 5K, 10K or 15K Europe at voice applications, or the like.
Fig. 3 B shows can provide 0dB or G
AttenThe schematic diagram of the design of the attenuator circuit 322 of decay.Attenuator circuit 322 comprises divider circuit 330 and switch 340.Switch 340 is single-pole double throw (SPDT) switch: its hilted broadsword is coupled to the Centronics port P of divider circuit 330; It first is thrown and is coupled to node A (described node A is coupled to the output of signal source 310); It second is thrown and is coupled to Node B (described Node B is a circuit ground).
The row 3 of table 1 and row 4 provide at wherein it provides the R of the design of 6dB decay when selecting attenuator circuit 322
1, R
2And R
3Value.Row 3 give the value that the various voltage urgent telegrams of institute's mark are flowed among Fig. 3 B when attenuator circuit 322 is in the bypass mode.Row 4 provide the value of various voltages and electric current when attenuator circuit 322 is in the evanescent mode.As shown in row 3, in bypass mode, pass the output current I of virtual ground
OutEqual input current I from signal source 310
InAs shown in row 4, in evanescent mode, pass the output current I of virtual ground
OutBe input current I from signal source 310
InHalf (or-6dB).At bypass mode and evanescent mode both, the input and the output impedance of attenuator circuit 322 are equal to R
0
In the design shown in Fig. 3 B, switch 340 can be coupled to node A or Node B at any given instant.Node B at ground connection place and node A at variable input voltage V
InThe place.Switch 340 can be implemented by one or more mos field effect transistor (MOSFET).When the source electrode of MOSFET and drain coupled to fixing or small voltage but not during big variable voltage, the linearity of described MOSFET can be improved.
Fig. 3 C shows can provide 0dB or G
AttenThe schematic diagram of the design of the attenuator circuit 324 of decay.Attenuator circuit 324 comprises divider circuit 330 and switch 340.Switch 340 makes its hilted broadsword be coupled to the Centronics port P of divider circuit 330, and it first is thrown and be coupled to node Y (described node Y is a circuit ground), and it second is thrown and be coupled to node Z (described node Z is coupled to the virtual ground of output place of signal source 316).Attenuator circuit 322 provides decay G when switch 340 is coupled to node Y
AttenAnd when being coupled to node Z, switch 340 do not provide decay.Because node Y and Z are at reality or virtual ground place, so the linearity of switch 340 can be improved.The row 5 of table 1 and row 6 provide the various voltages among Fig. 3 C and the value of electric current when attenuator circuit 324 is in bypass mode and the evanescent mode respectively.
As shown in Fig. 3 B and 3C, attenuator circuit 322 be reciprocal (that is symmetry) but and flip horizontal obtaining attenuator circuit 324.Even can be different from corresponding voltage and electric current in the attenuator circuit 322 at the value of voltages and electric current in bypass mode and the evanescent mode attenuator circuit 324, total attenuator circuit 322 still has identical transfer function with 324.
Fig. 4 shows also can provide 0dB or G
AttenThe schematic diagram of the design of the attenuator circuit 420 of decay.Attenuator circuit 420 comprises divider circuit 430 and switch 440, this two be coupled in the mode identical with divider circuit 330 and switch 340 among Fig. 3 C.
The π resistance pad that divider circuit 430 enforcements are formed by three resistors 432,434 and 436.Resistor 432 has a value R
aAnd be coupled between the input and output of divider circuit 430.Resistor 434 has a value R
bAnd be coupled between the input and Centronics port P of divider circuit 430.Resistor 436 1 value R
cAnd be coupled between the output and Centronics port P of divider circuit 430.Can select R
a, R
bAnd R
cMake attenuator circuit 420 that required attenuation G is provided in evanescent mode
AttenCan further select R
a, R
bAnd R
cBoth all have and have suitable input and output termination R at evanescent mode and bypass mode to make attenuator circuit 420
0Input impedance R
0And output impedance R
0
Fig. 5 shows also can provide 0dB or G
AttenThe schematic diagram of the design of the attenuator circuit 520 of decay.Attenuator circuit 520 comprises divider circuit 530 and switch 540 and 542.The T resistance pad that divider circuit 530 enforcements are formed by three resistors 532,534 and 536.Switch 540 has the other end of holding and be coupled to circuit ground of the Centronics port P that is coupled to divider circuit 530.Switch 542 has an other end of holding and be coupled to the output of divider circuit 530 of the input of being coupled to divider circuit 530.
For bypass mode, switch 542 closures, switch 540 disconnects, and divider circuit 530 is in fact by short circuit.In this pattern, V
2=V
1And I
Out=I
2=I
1=I
InFor evanescent mode, switch 542 disconnects, switch 540 closures, and divider circuit 530 is activated.In this pattern, V
2Be V
1Sub-fraction, and I
2Be I
1Sub-fraction.Can select R
1, R
2And R
3Make attenuator circuit 520 (i) that required attenuation G is provided in evanescent mode
AttenAnd (ii) have the input and the output impedance R that have suitable input and output termination
0, as shown in Figure 5.
In the design shown in Fig. 5, when selecting bypass mode, switch 542 is arranged in signal path.Switch 542 can reach to have enough little " connections " resistance that enough little parasitic capacitance is feasible not to make input signal too demote through design.
Fig. 3 B to 5 shows some exemplary design of the attenuator circuit that can operate in bypass mode or evanescent mode.Attenuator circuit also can be designed by other and implement.In general, attenuator circuit can use the divider circuit of arbitrary type
(for example, the resistance pad that forms by some resistors, capacitor pad of forming by some capacitors etc.).Resistance pad can be T resistance pad, π resistance pad etc.Attenuator circuit also can have one or more switches, and described one or more switches can be arranged in described attenuator circuit Anywhere and can arbitrary mode operate to realize required function.
For the purpose of clear, Fig. 3 A to 5 shows the single attenuator circuit that is coupled between input signal source 310 and the signal source output 316.A plurality of attenuator circuits can be through series coupled to support more than two gain settings.
Fig. 6 shows the schematic diagram of the design of the programmable gain circuit 600 with two attenuator circuit 620a and 620b.Each attenuator circuit 620a comprises divider circuit 630 and switch 640, this two to be coupled at divider circuit among Fig. 6 C 330 and switch 340 described modes as mentioned.Attenuator circuit 620a makes its input be coupled to input resistor 612 and makes its output be coupled to the input of attenuator circuit 620b.Attenuator circuit 620b makes its output be coupled to output resistor 614.Input signal source 610 is coupled to resistor 612, and signal source output 616 is coupled to resistor 614.
In each attenuator circuit 620, the T resistance pad that divider circuit 630 enforcements are formed by three resistors 632,634 and 636.Resistor 632,634 in each attenuator circuit 620 and 636 is through designing the decay of 6dB to be provided when described attenuator circuit is chosen and to have R
0/ 3 value.Switch 640a makes its hilted broadsword be coupled to the Centronics port P of divider circuit 630a, make it first throw and be coupled to node Y1 (described node Y1 is a circuit ground), and make it second throw and be coupled to node Z (described node Z is coupled to the virtual ground of output place of signal source 616).Similarly, switch 640b makes its hilted broadsword be coupled to the Centronics port P of divider circuit 630b, makes it first throw and be coupled to node Y2 (described node Y2 is a circuit ground), and makes it second throw and be coupled to node Z.Switch 640a is by S1 control signal control and the intermediate current of I/2 can be directed to node Y1 or node Z from the port P of divider circuit 630a.Switch 640b is by S2 control signal control and the intermediate current of I/4 can be directed to node Y2 or node Z from the port P of divider circuit 630b.
Table 2 shows the gain of the programmable gain circuit of setting at four different gains being determined by S1 and S2 control signal 600.In table 2, for each control signal S1 and S2, value " 0 " corresponding to bypass mode and value " 1 " corresponding to evanescent mode.At each gain setting, provide in the row 3 and provide the dB gain in linear gain and the row 4.
Table 2
| ??S1 | ??S2 | Linear gain | The dB gain | |
| ??0 | ??0 | ??1.00 | ??0 | Use |
| ??1 | ??0 | ??0.50 | ??-6 | Use |
| ??0 | ??1 | ??0.75 | ??-2.5 | Do not use |
| ??1 | ??1 | ??0.25 | ??-1.2 | Use |
Shown in the row 3 of table 2, the gain of programmable gain circuit 600 can change with 0.25 increment by linear unit.Yet, may expect to adjust with the increment of 6dB the gain of programmable gain circuit 600 by log unit.In the case, can abandon the gain setting of S1=1 and S2=0 in the third line of (that is, not using) table 2.Then, programmable gain circuit 600 can provide 0dB gain, S1=0 and the S2=1 (only selecting attenuator circuit 620b) of S1=S2=0 ( attenuator circuit 620a and 620b both all not chosen)-6dB gain and S1=S2=1 ( attenuator circuit 620a and 620b both all chosen)-the 12dB gain.
Fig. 7 shows to have the schematic diagram of a plurality of (K) attenuator circuit 720a of series coupled to the design of the programmable gain circuit 700 of 720k, and wherein K can be the arbitrary integer value greater than 1.Input resistor 712 is at a receiving inputted signal V of end place
InAnd will make its other end be coupled to the input of the first attenuator circuit 720a.Each attenuator circuit 720 (except that last attenuator circuit 720k) makes its output be coupled to the input of next attenuator circuit.Output resistor 714 makes an one output that end is coupled to the output of last attenuator circuit 720k and makes the other end be coupled to circuit 700, and described output can be virtual ground or low-impedance node as shown in Figure 7.
Each attenuator circuit 720 can be implemented by the attenuator circuit among the attenuator circuit among the attenuator circuit among Fig. 3 C 324, Fig. 4 420, Fig. 5 520 or a certain other attenuator circuit.Each attenuator circuit 720 can be in evanescent mode or bypass mode based on its Sk control signal operation, wherein k ∈ 1 ..., K}.Attenuator circuit 720a can be through design you can well imagine for decay G in the chosen time-division to 720k
1To G
KG
1To G
KCan be separately any suitable value and can based on wherein use circuit 700 should be used for select.Attenuator circuit 720a can be feasible through designing to 720k: (i) each attenuator circuit can be described attenuator circuit required attenuation G is provided when chosen
k, the input impedance of (ii) spying on the input of the first attenuator circuit 720a is R at all gain settings
0, and the output impedance of (iii) spying on the output of last attenuator circuit 720k also is R at all gain settings
0, suppose with R
0The suitably input and the output of termination circuit 700, as shown in Figure 7.
In general, programmable gain circuit can comprise the attenuator circuit of arbitrary number series coupled, and each attenuator circuit can provide arbitrary attenuation when chosen.Can be based on the number and the gain step size that should be used for selecting overall gain scope, gain setting that wherein use described programmable gain circuit.
Fig. 8 shows by the schematic diagram of heel with the design of the programmable gain amplifier of being made up of the programmable gain circuit 802 of operational amplifier 830 800.Amplifier 800 provide step-length be 1.5dB 58.5dB the overall gain scope and have 40 gain settings altogether.Amplifier 800 receives by V
InpAnd V
InnThe differential input signal that signal is formed also provides by V
OutThe single-ended output signal that signal is formed.
For V
InpSignal path, programmable gain circuit 802 comprise the attenuator circuit 821a of seven series coupled to 827a.Input resistor 812a receives V at one end
InpSignal and make its other end be coupled to the input of the first attenuator circuit 821a.Output resistor 814a makes an end be coupled to the output of last attenuator circuit 827a and makes the other end be coupled to the noninverting input of operational amplifier 830.For V
InnSignal path, programmable gain circuit 802 comprise the attenuator circuit 821b of seven series coupled to 827b.Input resistor 812b receives V at one end
InnSignal and make its other end be coupled to the input of the first attenuator circuit 821b.Output resistor 814b makes an end be coupled to the output of last attenuator circuit 827b and makes the other end be coupled to the anti-phase input of operational amplifier 830.V
InnSignal path is essentially V
InpThe mirror image of signal path.
In the design shown in Fig. 8, three attenuator circuits 821 to 823 in each input signal path are implemented by binary decoded and are provided different attenuations with 2 multiple (is unit with dB).Attenuator circuit 821 provides the decay of 1.5dB when chosen, attenuator circuit 822 provides the decay of 3dB when chosen, and attenuator circuit 823 provides the decay of 6dB when chosen.Attenuator circuit 821a each in the 823b all can be implemented by the attenuator circuit among Fig. 5 520.The nodes X of attenuator circuit 821a each in the 823b is corresponding to the nodes X among Fig. 5.Attenuator circuit 821a is coupled to common-mode node V to the X node of 823b
Cm, described common-mode node is the low-impedance node with dc voltage, described dc voltage is V
InpWith V
InnThe pact of the average voltage of signal half.Attenuator circuit 821a each in the 823a in bypass mode with its all input current I
1Be directed to output, and in evanescent mode with electric current I in the middle of it
3Be directed to node V
Cm, described at Fig. 5 as mentioned.
In the design shown in Fig. 8, identical attenuation is implemented and provided to four attenuator circuits 824 to 827 in each input signal path by thermometer decoder.Each attenuator circuit provides the decay of 12dB when chosen.Attenuator circuit 824a each in the 827b can be implemented by the attenuator circuit among the attenuator circuit among Fig. 3 C 324 or Fig. 4 420.The node Y of attenuator circuit 824a each in the 827b is corresponding to the node Y among Fig. 3 C or Fig. 4, and node Z is corresponding to the node Z among Fig. 3 C or Fig. 4.Attenuator circuit 824a is coupled to the noninverting input of operational amplifier 830 to the Z node of 827a.Attenuator circuit 824b is coupled to the anti-phase input of operational amplifier 830 to the Z node of 827b.Attenuator circuit 824a is coupled to node V to the Y node of 827b
CmAttenuator circuit 824a each in the 827a in bypass mode with electric current I in the middle of it
3Be directed to the noninverting input of operational amplifier 830 and in evanescent mode, be directed to node V
CmAttenuator circuit 824b each in the 827b in bypass mode with electric current I in the middle of it
3Be directed to the anti-phase input of operational amplifier 830 and in evanescent mode, be directed to node V
Cm
Can and be independent of by arbitrary order and select three couples of attenuator circuit 821a and 821b, 822a and 822b and 823a and 823b each other.Can select attenuator circuit 821a and 821b so that the decay of 1.5dB to be provided, can select attenuator circuit 822a and 822b so that the decay of 3dB to be provided, and can select attenuator circuit 823a and 823b so that the decay of 6dB to be provided.Selected each attenuator circuit is with electric current I in the middle of it
3Be directed to node V
Cm, described node then provides decay.
But four couples of attenuator circuit 824a of predetermined order selection and 824b, 825a and 825b, 826a and 826b and 827a and 827b are the decay of 12dB to obtain step-length.At first can select attenuator circuit 824a and 824b so that the decay of 12dB to be provided, next can further select attenuator circuit 825a and 825b so that the decay of 24dB to be provided, next can further select attenuator circuit 826a and 826b so that the decay of 36dB to be provided, can further select attenuator circuit 827a and 827b at last so that the decay of 48dB to be provided.Selected each attenuator circuit is with electric current I in the middle of it
3Be directed to node V
Cm, described node provides decay subsequently.Unselected each attenuator circuit is with electric current I in the middle of it
3Be directed to the noninverting input or the anti-phase input of operational amplifier 830, described noninverting input or anti-phase input then do not provide decay.
Table 3 provides R at each attenuator circuit among Fig. 8
0, R
1, R
2And R
3Value.Each and as Fig. 3 C as shown in the design of enforcement attenuator circuit 824a to 827b in each of attenuator circuit 821a in the 823b wherein implemented in table 3 supposition as shown in Figure 5.
Table 3
| Parameter | Attenuator circuit 821 | Attenuator circuit 822 | Attenuator circuit 823 | Attenuator circuit 824 | Attenuator circuit 825 | Attenuator circuit 826 | Attenuator circuit 827 |
| Gain | ??-1.5dB | ??-3dB | ??-6dB | ??-12dB | ??-12dB | ??-12dB | ??-12dB |
| ??R 0 | ??15KΩ | ??15KΩ | ??15KΩ | ??15KΩ | ??15KΩ | ??15KΩ | ??15KΩ |
| ??R 1、R 2 | ??1.30KΩ | ??2.57KΩ | ??5KΩ | ??9KΩ | ??9KΩ | ??9KΩ | ??9KΩ |
| ??R 3 | ??86.1KΩ | ??42.4KΩ | ??20KΩ | ??8KΩ | ??8KΩ | ??8KΩ | ??8KΩ |
| Control | Select by arbitrary order | Select by arbitrary order | Select by arbitrary order | First selects | Second selects | The 3rd selects | The 4th selects |
For the design shown in Fig. 8, can use by position b1 and select signal to select one in 40 gain settings to 6 gains that b6 forms.Described gain select signal can between from the b6...b1=000000 (binary system) that sets at the maximum gain of 0dB in scope at the b6...b1=100111 (binary system) of the least gain setting of-58.5dB.For gain setting x (decimal system), attenuation is 1.5xdB, and wherein x is in from 0 to 39 scope.The S1 that is used for seven pairs of attenuator circuits of Fig. 8 can followingly produce to the S7 control signal: S1=b1, S2=b2, S3=b3, S4=b4+b5+b6, S5=b5+b6, S6=b4*b5+b6, and S7=b6, wherein the OR computing of "+" presentation logic and " * " presentation logic AND computing.Therefore, can easily to b6, produce S1 to the S7 control signal from the position b1 that selects signal through the gain of binary decoding.
Binary decoded attenuation circuits 821a can improve gain accuracy to 827b at the use of high attenuation at the attenuator circuit 824a of the use of little decay and thermometer decoder to 823b, reduces the number of attenuator circuit simultaneously.For attenuator circuit,, the small scale of the resistor values due to the change at random in integrated circuit (IC) manufacture process can cause comparing relatively large gain error with the least gain step-length of 1.5dB because of changing with high attenuation.Therefore, thermometer decoder can be used for having the attenuator circuit of high attenuation to improve the gain accuracy.For attenuator circuit,, the same ratio of the resistor values of random process due to changing to cause comparing relative less gain error with the least gain step-length of 1.5dB because of changing with less decay.Therefore, the binary decoded attenuator circuit that can be used for having less decay is not sacrificed the gain accuracy with the number that reduces attenuator circuit.As in circuit 600, in order to obtain with dB to be the simple gain increment of unit, binary decoded attenuation circuits should be placed on the attenuator circuit front of thermometer decoder.
Fig. 8 shows to have the exemplary programmable gain circuit 802 of three couples of binary decoded attenuation circuits 821a to the attenuator circuit 824a of 823b and four pairs of thermometer decoders to 827b.In general, programmable gain circuit can comprise the attenuator circuit of arbitrary number binary decoded attenuation circuits and arbitrary number thermometer decoder.Can select the number of the attenuator circuit of the number of binary decoded attenuation circuits and thermometer decoder based on required overall gain scope, required gain step size, required gain accuracy, desired IC process variable quantity and/or other factors.
Fig. 9 shows the flow chart of the design of the process 900 that is used for conditioning signal.Can from a plurality of gain settings, select gain setting (piece 912).Based on described selected gain setting is that a plurality of attenuator circuits produce a plurality of control signals (piece 914).Each control signal can be the attenuator circuit that is associated and selects first/evanescent mode or second/bypass mode.Can in first pattern, decay input signal and in second pattern, walk around (or unattenuated) described input signal of each attenuator circuit.Can transmit described input signal to obtain gain (piece 916) by described a plurality of attenuator circuits corresponding to described selected gain setting.
Described a plurality of attenuator circuit can comprise one group of binary decoded attenuation circuits.Can produce control signal to select binary decoded attenuation circuits, wherein determine described selected binary decoded attenuation circuits based on described selected gain setting by arbitrary order.Another is chosen as or in addition, described a plurality of attenuator circuits can comprise the attenuator circuit of one group of thermometer decoder.Can produce the attenuator circuit of control signal, wherein determine the number of selected temperature meter decoded attenuation circuits based on selected gain setting with predetermined order selection thermometer decoder.In general, the mode of selection attenuator circuit can be depending on the design of attenuator circuit.
Described herein programmable gain circuit can be used for various application, for example communicates by letter, calculates, networking, personal electronic equipments etc.For instance, programmable gain circuit can be used for radio communication device, cellular phone, PDA(Personal Digital Assistant), handheld apparatus, game device, calculation element, laptop computer, consumer electronic devices, personal computer, radio telephone etc.The exemplary purposes of described programmable gain circuit in radio communication device hereinafter described.
Figure 10 shows the block diagram of the design of the radio communication device 1000 that is used for wireless communication system.Wireless device 1000 can be cellular phone, terminal, mobile phone, radio modem etc.Described wireless communication system can be code division multiple access (CDMA) system, global system for mobile communications (GSM) system etc.
Wireless device 1000 can provide two-way communication via RX path and transmission path.On RX path, antenna 1012 receives by the signal of base station and provides it to receiver (RCVR) 1014.Receiver 1014 is regulated and digitlization received signal and sample offered digital block 1020 for further processing.On transmission path, reflector (TMTR) 1016 receives and will handle and regulate described data from the data of digital block 1020 emissions, and produces through modulation signal, describedly is transmitted into the base station through modulation signal via antenna 1012.Receiver 1014 and reflector 1016 can be the part of the transceiver that can support CDMA, GSM etc.
Digital block 1020 comprises various processing, interface and memory cell, for example, modem processor 1022, Reduced Instruction Set Computer/digital signal processor (RISC/DSP) 1024, controller/processor 1026, memory 1028, audio process 1030, audio driver 1032, External device driver 1034 and display driver 1036.Modem processor 1022 can be carried out the processing at data transmission and reception, for example, and coding, modulation, demodulation, decoding etc.RISC/DSP 1024 can carry out the general and special disposal of wireless device 1000.Controller/processor 1026 can instruct the operation of various unit in the digital block 1020.Memory 1028 can be stored data and/or the instruction that is used for various unit in the digital block 1020.
Audio process 1030 can be carried out coding to the input signal from audio-source 1040, microphone 1042 etc.Audio process 1030 also can be to carrying out decoding and output signal can be offered audio driver 1032 through the voice data of decoding.But audio driver 1032 drive headphones 1044, loud speaker 1046 etc.External device driver 1034 can drive external device (ED) 1048 and/or can be from external device (ED) 1048 received signals.But display driver 1036 driving display unit 1050.
As shown in Figure 10, programmable gain circuit can be used for expecting or requires among various of variable gain.For example, programmable gain circuit can be used in the receiver 1014, in the reflector 1016, in the audio driver 1032, in the External device driver 1034, in the display driver 1036, in the audio-source 1040, external device (ED) 1048 is medium.As instantiation, the programmable gain amplifier 800 among Fig. 8 can be used for audio driver 1032 with drive headphones 1044 and/or loud speaker 1046.
Described herein programmable gain circuit may be implemented on IC, analog IC, RF IC (RFIC), mixed-signal IC, application-specific integrated circuit (ASIC) (ASIC), printed circuit board (PCB) (PCB), the electronic installation etc.Programmable gain circuit also can be made by for example complementary metal oxide semiconductors (CMOS) (CMOS), N-passage MOS (N-MOS), P-passage MOS (P-MOS), ambipolar junction transistors (BJT), bipolar-CMOS (BiCMOS), SiGe (SiGe), GaAs various IC technologies such as (GaAs).
The equipment of described programmable gain circuit herein implemented can be self-contained unit or can be a part than bigger device.Device can be: (i) independent IC; (ii) one group of one or more IC, it can comprise the memory IC that is used to store data and/or instruction; (iii) RFIC, for example RF receiver (RFR) or RF emitter/receiver (RTR); (iv) ASIC, for example travelling carriage modulator-demodulator (MSM); (v) module, it can be embedded in other device; (vi) receiver, cellular phone, wireless device, mobile phone or mobile unit; (vii) or the like.
Provide and be intended to make the those skilled in the art can make or use the present invention previous explanation of the present invention.The those skilled in the art will be easy to understand various modification of the present invention, and the general principle that is defined herein also can be applicable to other variation, and this does not deviate from scope of the present invention.Therefore, the present invention does not plan to be defined in described example and design herein, but should be endowed and principle disclosed herein and the corresponding to broad range of novel feature.
Claims (25)
1. equipment, it comprises:
Divider circuit, it is configured to receiving inputted signal and output signal is provided; And
At least one switch, it is coupled to described divider circuit and is configured to selects first pattern or second pattern for described divider circuit, described divider circuit in described first pattern, decay described input signal and in described second pattern unattenuated described input signal.
2. equipment according to claim 1, wherein said at least one switch comprises single-pole double throw (SPDT) switch, and described single-pole double throw (SPDT) switch is configured in described first pattern intermediate current is directed to ground connection and be directed to circuit output described second pattern from described divider circuit.
3. equipment according to claim 1, wherein said at least one switch comprises
First switch, it is crossed over the input of described divider circuit and output and is coupled, and
Second switch, it is coupled between the Centronics port and ground connection of described divider circuit, and for described first pattern, described first switch disconnects and described second switch closure, and for described second pattern, described first switch closure and described second switch disconnects.
4. equipment according to claim 1, wherein said divider circuit comprises resistor pad, described resistor pad comprises
First resistor, it is coupled between the input and Centroid of described divider circuit,
Second resistor, it is coupled between the described Centroid and output of described divider circuit, and
The 3rd resistor, it is coupled between the described Centroid and Centronics port of described divider circuit.
5. equipment according to claim 1, wherein said divider circuit comprises resistor pad, described resistor pad comprises
First resistor, it is coupled between the input and output of described divider circuit,
Second resistor, it is coupled between the described input and Centronics port of described divider circuit, and
The 3rd resistor, it is coupled between the described output and described Centronics port of described divider circuit.
6. both have predetermined input impedance and predetermined output impedance at described first and second pattern for equipment according to claim 1, wherein said divider circuit.
7. equipment, it comprises:
Programmable gain circuit, it comprises a plurality of attenuator circuits of series coupled, and each attenuator circuit can be operated and be configured in described first pattern decay input signal and unattenuated described input signal in described second pattern in first pattern or second pattern.
8. equipment according to claim 7, it further comprises:
Amplifier, it has the input of being coupled to described programmable gain circuit, and described amplifier provides fixed gain based on the output impedance of described programmable gain circuit.
9. equipment according to claim 7, wherein each attenuator circuit comprises
Divider circuit, the output signal that it is configured to receiving inputted signal and described divider circuit is provided, and
At least one switch, it is coupled to described divider circuit and is configured to selects described first pattern or described second pattern for described attenuator circuit, described divider circuit in described first pattern, decay described input signal and in described second pattern unattenuated described input signal.
10. equipment according to claim 7, wherein said a plurality of attenuator circuits comprise
One group of binary decoded attenuation circuits, it provides different attenuations, and
The attenuator circuit of one group of thermometer decoder, it provides equal attenuation.
11. equipment according to claim 10, wherein said binary decoded attenuation circuits can be selected and the attenuator circuit predetermined order of described thermometer decoder is selected by arbitrary order.
12. equipment according to claim 10, each in the wherein said binary decoded attenuation circuits comprises
Divider circuit, the output signal that it is configured to receiving inputted signal and described divider circuit is provided,
First switch, it is crossed over the input of described divider circuit and output and is coupled, and
Second switch, it is coupled between the Centronics port and ground connection of described divider circuit, and for described first pattern, described first switch disconnects and described second switch closure, and for described second pattern, described first switch closure and described second switch disconnects.
13. equipment according to claim 10, each in the attenuator circuit of wherein said thermometer decoder comprises
Divider circuit, it is configured to receiving inputted signal and output signal is provided, and
Single-pole double throw (SPDT) switch, it is configured to the output that in described first pattern intermediate current is directed to ground connection and is directed to described programmable gain circuit described second pattern from described divider circuit.
14. equipment according to claim 7, wherein said programmable gain circuit support is corresponding to a plurality of gain settings of differential declines amount.
15. equipment according to claim 14, wherein said programmable gain circuit has predetermined input impedance and predetermined output impedance at all described a plurality of gain settings.
16. an integrated circuit, it comprises:
Programmable gain circuit, it comprises a plurality of attenuator circuits of series coupled, and each attenuator circuit can be operated and be configured in described first pattern decay input signal and unattenuated described input signal in described second pattern in first pattern or second pattern.
17. integrated circuit according to claim 16, it further comprises:
Amplifier, it has the input of being coupled to described programmable gain circuit, and described amplifier provides fixed gain based on the output impedance of described programmable gain circuit.
18. integrated circuit according to claim 16, wherein each attenuator circuit comprises
Divider circuit, the output signal that it is configured to receiving inputted signal and described divider circuit is provided, and
At least one switch, it is coupled to described divider circuit and is configured to selects described first pattern or described second pattern for described attenuator circuit, described divider circuit in described first pattern, decay described input signal and in described second pattern unattenuated described input signal.
19. integrated circuit according to claim 16, wherein said a plurality of attenuator circuits comprise
One group of binary decoded attenuation circuits, it provides different attenuations, and
The attenuator circuit of one group of thermometer decoder, it provides equal attenuation.
20. a method, it comprises:
From a plurality of gain settings, select gain setting;
Produce a plurality of control signals that are used for a plurality of attenuator circuits based on described selected gain setting, each control signal is selected first pattern or second pattern for the attenuator circuit that is associated, each attenuator circuit in described first pattern, decay input signal and in described second pattern unattenuated described input signal; And
Transmit described input signal to obtain gain by described a plurality of attenuator circuits corresponding to described selected gain setting.
21. method according to claim 20, wherein said a plurality of attenuator circuit comprises one group of binary decoded attenuation circuits, and the described a plurality of control signals of wherein said generation comprise and produce described a plurality of control signals to select described binary decoded attenuation circuits by arbitrary order, wherein determine described selected binary decoded attenuation circuits based on described selected gain setting.
22. method according to claim 20, wherein said a plurality of attenuator circuit comprises the attenuator circuit of one group of thermometer decoder, and the described a plurality of control signals of wherein said generation comprise that producing described a plurality of control signals selects the attenuator circuit of described thermometer decoder with predetermined order, wherein determines the number of selected temperature meter decoded attenuation circuits based on described selected gain setting.
23. an equipment, it comprises:
Be used for selecting the device of gain setting from a plurality of gain settings;
Be used for producing the device of a plurality of control signals that are used for a plurality of attenuator circuits based on described selected gain setting, each control signal is selected first pattern or second pattern for the attenuator circuit that is associated, each attenuator circuit in described first pattern, decay input signal and in described second pattern unattenuated described input signal; And
Be used for transmitting described input signal to obtain device corresponding to the gain of described selected gain setting by described a plurality of attenuator circuits.
24. equipment according to claim 23, wherein said a plurality of attenuator circuit comprises one group of binary decoded attenuation circuits, and the wherein said device that is used to produce described a plurality of control signals comprises and is used to produce described a plurality of control signal to select the device of described binary decoded attenuation circuits by arbitrary order, wherein determines described selected binary decoded attenuation circuits based on described selected gain setting.
25. equipment according to claim 23, wherein said a plurality of attenuator circuit comprises the attenuator circuit of one group of thermometer decoder, and the wherein said device that is used to produce described a plurality of control signals comprises that being used to produce described a plurality of control signal selects the device of the attenuator circuit of described thermometer decoder with predetermined order, wherein determines the number of selected temperature meter decoded attenuation circuits based on described selected gain setting.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/929,241 US7868681B2 (en) | 2007-10-30 | 2007-10-30 | Programmable gain circuit |
| US11/929,241 | 2007-10-30 | ||
| PCT/US2008/081709 WO2009058948A2 (en) | 2007-10-30 | 2008-10-30 | Programmable gain circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101842979A true CN101842979A (en) | 2010-09-22 |
Family
ID=40316963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200880113762A Pending CN101842979A (en) | 2007-10-30 | 2008-10-30 | Programmable gain circuit |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7868681B2 (en) |
| EP (1) | EP2215717A2 (en) |
| JP (1) | JP2011502442A (en) |
| KR (1) | KR101155836B1 (en) |
| CN (1) | CN101842979A (en) |
| TW (1) | TW200934111A (en) |
| WO (1) | WO2009058948A2 (en) |
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| CN103580633A (en) * | 2012-08-08 | 2014-02-12 | 瑞萨移动公司 | Semiconductor integrated circuit and radio communication terminal including same |
| CN103812463A (en) * | 2014-01-13 | 2014-05-21 | 智坤（江苏）半导体有限公司 | Gain control method for radio frequency power amplifier |
| CN104104345A (en) * | 2013-04-02 | 2014-10-15 | 安凯(广州)微电子技术有限公司 | Low-noise microphone input amplifier |
| CN109792099A (en) * | 2016-08-16 | 2019-05-21 | 天工方案公司 | Digital-switching type attenuator |
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| US7706473B2 (en) * | 2006-03-24 | 2010-04-27 | Freescale Semiconductor, Inc. | Comparative signal strength detection |
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| US20100257574A1 (en) * | 2009-04-01 | 2010-10-07 | Chun-Hsien Pan | Multimedia network splitter |
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| JP2016036180A (en) * | 2015-11-13 | 2016-03-17 | ルネサスエレクトロニクス株式会社 | Wireless communication device |
| US10498383B2 (en) | 2016-02-26 | 2019-12-03 | Skyworks Solutions, Inc. | Attenuation circuits with low insertion loss, and modules and devices using same |
| GB2569714B (en) * | 2016-08-30 | 2022-11-16 | Skyworks Solutions Inc | Multi-input amplifier with programmable embedded attenuators |
| US10396735B2 (en) | 2016-11-11 | 2019-08-27 | Skyworks Solutions, Inc. | Amplifier system with digital switched attenuator |
| US10340892B2 (en) * | 2017-08-22 | 2019-07-02 | Psemi Corporation | Multi-channel digital step attenuator architecture |
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Also Published As
| Publication number | Publication date |
|---|---|
| TW200934111A (en) | 2009-08-01 |
| US7868681B2 (en) | 2011-01-11 |
| JP2011502442A (en) | 2011-01-20 |
| KR101155836B1 (en) | 2012-06-21 |
| EP2215717A2 (en) | 2010-08-11 |
| US20090108931A1 (en) | 2009-04-30 |
| WO2009058948A2 (en) | 2009-05-07 |
| WO2009058948A3 (en) | 2009-11-19 |
| KR20100080849A (en) | 2010-07-12 |
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