CN101840903B - Packaging substrate and chip packaging structure - Google Patents
Packaging substrate and chip packaging structure Download PDFInfo
- Publication number
- CN101840903B CN101840903B CN 200910129666 CN200910129666A CN101840903B CN 101840903 B CN101840903 B CN 101840903B CN 200910129666 CN200910129666 CN 200910129666 CN 200910129666 A CN200910129666 A CN 200910129666A CN 101840903 B CN101840903 B CN 101840903B
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- Prior art keywords
- chip
- breach
- dummy pin
- packaging
- pin
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- Expired - Fee Related
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 65
- 239000000758 substrate Substances 0.000 title abstract description 6
- 238000005530 etching Methods 0.000 claims description 16
- 238000005538 encapsulation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007731 hot pressing Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
The invention provides a packaging substrate and a chip packaging structure. The packaging substrate comprises a flexible dielectric layer and a conducting layer, wherein the flexible dielectric layer is provided with a chip bonding zone for setting a chip; and the conducting layer is arranged on the flexible dielectric layer and comprises a plurality of functional pins and a plurality of nominalpins. The functional pins respectively extend outwards from the chip bonding zone. The nominal pins are adjacently arranged, wherein each nominal pin is provided with a gap, and the gaps are respectively positioned on N datum lines, wherein N is a positive integer not less than 2.
Description
Technical field
The chip-packaging structure that the invention relates to a kind of base plate for packaging and comprise this base plate for packaging; And especially; Base plate for packaging according to the present invention has many adjacent arrangements and has the dummy pin of breach, and the breach of wantonly two adjacent dummy pin stagger arrange non-conterminous.
Background technology
Existing Chip Packaging kenel comprises a kind of substrate with deflection as the automatic bond package of the winding of chip bearing member (Tape Automated Bonding; TAB) technology; It comprises: encapsulation (Tape Carrier Package is carried in winding; TCP), membrane of flip chip encapsulation (Chip On Film, COF) etc.This type of encapsulation kenel is that chip is fixed on the flexible package substrate; And with the projection or the weld pad of chip; Engage with the conductive layer contraposition heating and pressurizing of flexible package substrate,, particularly be applied to the encapsulation of the chip for driving of LCD for one of at present common chip encapsulation technology.
Please consult Fig. 1 and Fig. 2 in the lump, Fig. 1 system illustrates the top view of the base plate for packaging 9 of prior art; Fig. 2 then illustrates the enlarged diagram around the zone of dotted line among Fig. 1.As shown in Figure 1; This base plate for packaging 9 comprises a flexible dielectric layer 90, many root functionalitys pin 920 and many dummy pin 922; And this many root functionalitys pin 920 and many dummy pin 922 are arranged at (in practice, this many root functionalitys pin 920 and many dummy pin 922 are to be formed with for example etching mode patterning by a conductive layer) on this flexible dielectric layer 90.
In addition, one chip bonding area 900, chip are arranged is to be arranged in this chip bonding area 900 in definition on this flexible dielectric layer 90, and the projection of chip or weld pad can engage with these many root functionalitys pin 920 heating and pressurizing.
Further, these dummy pin 922 all comprise a 922a of first and a second portion 922b, and the 922a of this first and this second portion 922b separate and do not link to each other mutually by a breach 922c.Therefore, these dummy pin 922 and unsubstantial signal transfer functions, its setting is not have the white space of laying pin, the intensity of Strengthenable flexible dielectric layer 90 on the flexible dielectric layer 90 in order to reduce.In addition, dummy pin 922 also can be done with chip contact (like aforesaid projection or weld pad) and engage, and with average dispersion activating pressure, and provides support the effect of chip.
In addition, when dummy pin 922 engages with the chip contact, possibly have Partial charge and flow to dummy pin 922, and in dummy pin 922, flow, and then function pin 920 is produced electrically interference from chip.Therefore, the breach 922c of dummy pin 922 can cut off the flow of charge path, avoids function pin 920 is produced electrically interference.Therefore, the position of breach 922c can shorten this first part 922a of these dummy pin 922 as far as possible near chip bonding area 900 as far as possible, and promptly disconnected as early as possible power down lotus circulation path is to reach preferable effect.
In addition, as shown in Figure 1, except the dummy pin 922 of straight line kenel, the base plate for packaging 9 in the prior art has also comprised many loop dummy pin 924.Though loop dummy pin 924 not with chip join, possibly receive the next door has the function pin of electric current to bring out to accumulate electric charge gradually, and because it be the loop shape, electric charge constantly flows in the loop, also possibly produce electrically interference to adjacent function pin 920.Therefore, these loop dummy pin 924 also can be done breach 924c design, to avoid that next door function pin 920 is produced electrically interference.
Further, as shown in Figure 2, in prior art, the breach 922c of these dummy pin 922 all position thereby forms a relief area 96 on same datum line 94.The breach 924c of these loop dummy pin 924 all position forms a relief area 97 on same datum line 95.Yet; In etching process, etching liquid is gathered in this relief area 96,97 easily and forms eddy current, causes function pin 920 over etchings (overetched) adjacent with this relief area 96,97; Cause these function pin 920 attenuation or even fracture, and then influence its function.
Summary of the invention
Therefore; One side of the present invention is to provide a kind of base plate for packaging that has many adjacent arrangements and have the dummy pin of breach; And the breach of wantonly two adjacent dummy pin staggers and arranges non-conterminously, can solve the problem of the function pin over etching that is positioned at the breach both sides in the prior art.
According to a specific embodiment, base plate for packaging of the present invention comprises a flexible dielectric layer and a conductive layer.This flexible dielectric layer definition has a chip bonding area, in order to a chip to be set.This conductive layer is arranged on this flexible dielectric layer, and comprises many root functionalitys pin and many dummy pin.These function pins are respectively by stretching out in this chip bonding area.The adjacent arrangement of these dummy pin, wherein each dummy pin has a breach.Especially, these breach lay respectively on the N bar datum line, and N is the positive integer more than or equal to 2.In other words, these breach can all not be positioned on same the datum line.In addition, in practice, this N bar datum line is parallel to each other haply.
Another aspect of the present invention is to provide a kind of chip-packaging structure, to solve the problem in the prior art.
According to a specific embodiment, this chip-packaging structure comprises a base plate for packaging and a chip.As previously mentioned, this base plate for packaging comprises a flexible dielectric layer and a conductive layer.This flexible dielectric layer definition has a chip bonding area.This conductive layer is arranged on this flexible dielectric layer, and comprises many root functionalitys pin and many dummy pin.These function pins are respectively by stretching out in this chip bonding area.The adjacent arrangement of these dummy pin, and each dummy pin has a breach.Especially, these breach lay respectively on the N bar datum line, and N is the positive integer more than or equal to 2.In other words, these breach can all not be positioned on same the datum line.In addition, in practice, this N bar datum line is parallel to each other haply.In addition, this chip is arranged in this chip bonding area, and this chip comprises a plurality of contacts and couples this many root functionalitys pin respectively.
The breach of wantonly two adjacent many dummy pin that in sum, base plate for packaging of the present invention comprised lays respectively on 2 datum lines at least.In other words, each breach can all not be positioned on same the datum line.By such breach arrangement design, can prevent to be positioned in the prior art function pin over etching of breach both sides, the problem of pin attenuation or fracture is taken place.
Description of drawings
For let above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, elaborate below in conjunction with the accompanying drawing specific embodiments of the invention, wherein:
Fig. 1 system illustrates the top view of the base plate for packaging of prior art.
Fig. 2 then illustrates the enlarged diagram around the zone of dotted line among Fig. 1.
Fig. 3 illustrates the top view according to the base plate for packaging of a specific embodiment of the present invention.
Fig. 4 illustrates the enlarged diagram around the zone of dotted line among Fig. 3.
Fig. 5 illustrates base plate for packaging among Fig. 3 along the profile of O-O ' line.
Fig. 6 illustrates the top view according to the chip-packaging structure of a specific embodiment of the present invention.
Fig. 7 illustrates chip-packaging structure among Fig. 6 along the profile of O-O ' line.
Fig. 8 A and Fig. 8 B illustrate the sketch map that kind attitude is set according to the breach of dummy pin of the present invention respectively.
The main element symbol description:
1: chip-packaging structure 10,9: base plate for packaging
100,90: flexible dielectric layer 1000,900: chip bonding area
102: conductive layer 1020,920: function pin
1022,922: dummy pin 1022a, 922a: first
1022b, 922b: second portion 1022c, 922c, 924c: breach
1024,924: loop dummy pin 104: welding resisting layer
12: chip 120: projection
14,94,95: datum line 96,97: relief area
Embodiment
The chip-packaging structure that the present invention provides a kind of base plate for packaging and comprises this base plate for packaging.Some specific embodiments according to the present invention are to disclose as follows.
Please consult Fig. 3 to Fig. 7 in the lump, Fig. 3 illustrates the top view according to the base plate for packaging 10 of a specific embodiment of the present invention; Fig. 4 illustrates the enlarged diagram around the zone of dotted line among Fig. 3; Fig. 5 illustrates base plate for packaging 10 among Fig. 3 along the profile of O-O ' line; Fig. 6 illustrates the top view according to the chip-packaging structure 1 of a specific embodiment of the present invention; Fig. 7 then illustrates chip-packaging structure 1 among Fig. 6 along the profile of O-O ' line.
As shown in the figure, chip-packaging structure 1 of the present invention comprises this base plate for packaging 10 and is arranged at the chip 12 on this base plate for packaging 10.Further; As shown in the figure; Base plate for packaging 10 of the present invention comprises a flexible dielectric layer 100 and is arranged at a conductive layer 102 on this flexible dielectric layer 100 (note that here illustrated conductive layer 102 form many root functionalitys pin 1020, many dummy pin 1022 and many loop dummy pin 1024 by etching or other suitable mode patterning).In addition, definition has a chip bonding area 1000 on this flexible dielectric layer 100.
In practical application, the material of this flexible dielectric layer 100 can be polyimide (Polyimide, PI), the polyesters compound (polyethylene terephthalate, PET) or other suitable material.In addition, the material of this conductive layer 102 can be metal material (for example, but being not limited to copper) or other suitable material.In practice, in order to strengthen the radiating effect of 10 pairs of chips 12 of base plate for packaging, flexible dielectric layer 100 optional usefulness have the material of high thermal conductivity coefficient and make.
Further, as previously mentioned, this conductive layer 102 forms many root functionalitys pin 1020, many dummy pin 1022 and many loop dummy pin 1024 via etching or other suitable mode patterning.These function pins 1020 and dummy pin 1022 are respectively by stretching out (away from chip bonding area) in this chip bonding area 1000, and these dummy pin 1022 adjacent arrangements.And each dummy pin 1022 is separated into a disjunct 1022a of first and a second portion 1022b mutually by a breach 1022c, and these breach 1022c lays respectively on 3 datum lines that are parallel to each other haply 14.Note that in practice dummy pin 1022 also can can't help to stretch out in the chip bonding area 1000, and all is positioned at outside the chip bonding area 1000.In addition, as shown in the figure, 1024 of these loop dummy pin are positioned at outside the chip bonding area 1000, and the breach of these loop dummy pin 1024 also can be designed to not be positioned on the same datum line as dummy pin 1022.
Note that in practice these breach lay respectively on the N bar datum line, N is the positive integer more than or equal to 2.In other words, these breach can be designed to be positioned on the datum line of 2,5,10 or other quantity according to circumstances, be not limited to here to be given an example 3.In addition, in practice, not necessarily will be parallel to each other between the datum line, the angle between each datum line maybe be less than 180 degree.
In addition, as shown in Figure 5, in this specific embodiment, this base plate for packaging 10 more comprises a welding resisting layer (solder resist layer) 104, and local this conductive layer 102 of covering also appears this chip bonding area 1000.In practical application, welding resisting layer 104 can be protected conductive layer 102, avoids conductive layer 102 to receive outside destroy, and prevents conductive layer 102 from contacting with conductor and produce short circuit.
Like Fig. 6 and shown in Figure 7; In chip-packaging structure 1 of the present invention; Chip 12 can be arranged in this chip bonding area 1000 by modes such as flip chip bondings; And a plurality of projections 120 of chip 12 contact of other patterns such as weld pad (or as) correspond to this many root functionalitys pin 1020 respectively, and each projection 120 engages for example to add the hot pressing mode with pairing function pin 1020.In addition, in practical application, a plurality of projections 120 of chip 12 also can be distinguished corresponding these many dummy pin 1022 of joint, and each projection 120 engages for example to add the hot pressing mode with pairing dummy pin 1022.Dummy pin 1022 is as the usefulness of signal transmission, but when chip 12 is engaged in base plate for packaging 10 on average dispersive pressure and the effect that provides support.
In addition; In practice; Convenience for chip encapsulating manufacturing procedure; Perhaps under the considering of time or money cost or surcharge, or in order under different encapsulation conditions, to solve the problem of the function pin over etching that is positioned at the breach both sides in the prior art more efficiently, suitable adjustment can be done in the position of these breach 1022c.See also Fig. 8 A and Fig. 8 B, Fig. 8 A and Fig. 8 B illustrate the sketch map that kind attitude is set according to the breach 1022c of dummy pin 1022 of the present invention respectively.
Note that for more clearly illustrate dummy pin 1022 breach 1022c a kind attitude is set, Fig. 8 A and Fig. 8 B only draw part pin (comprising function pin 1020 and dummy pin 1022), and do not show complete base plate for packaging or chip-packaging structure.
As shown in the figure, these function pins 1020 are respectively by stretching out in this chip bonding area 1000; These dummy pin 1022 adjacent arrangements; And each dummy pin 1022 is separated into mutually a disjunct 1022a of first and a second portion 1022b by a breach 1022c, and these breach 1022e lays respectively on the datum line 14 that the N bar is parallel to each other haply.
Shown in Fig. 8 A, N equals 2, that is these breach 1022c is staggered on 2 datum lines that are parallel to each other haply 14.Especially, the breach 1022c of wherein wantonly two adjacent dummy pin 1022 stagger arrange non-conterminous.
Further, shown in Fig. 8 B, N equals 4, and these breach 1022c arranges with the mode that descends gradually and rise gradually.The breach 1022c of wherein wantonly two adjacent dummy pin 1022 stagger equally arrange non-conterminous.Especially, by arrangement mode, can make things convenient for the user to calculate these pins like Fig. 8 B.
The design that note that the breach 1022c of aforementioned dummy pin 1022 is intended to avoid 1022 pairs of function pins of dummy pin to cause electrical interference, even chip is caused damage, and etching process causes the problems such as function pin over etching of breach both sides to take place.Therefore, under such purpose, the arrangement mode of the breach of dummy pin of the present invention can reasonably be adjusted according to circumstances, is not limited to the example that take the front.In addition, in practice, not necessarily will be parallel to each other between the datum line, the angle between each datum line maybe be less than 180 degree.
In sum, the adjacent arrangement of the dummy pin on base plate for packaging of the present invention and the chip-packaging structure, and the breach of each dummy pin is positioned on 2 datum lines at least, even the breach of wantonly two adjacent dummy pin stagger arrange non-conterminous.Whereby; Base plate for packaging of the present invention and chip-packaging structure can avoid dummy pin that the function pin is caused electrical interference; Even chip caused damage; Can prevent also in the etching process that etching liquid accumulates in is positioned at the breach on the same datum line and causes the function pin over etching of breach both sides, causes attenuation of function pin or even problem such as fracture.
By the detailed description of above preferred embodiment, be to hope to know more to describe characteristic of the present invention and spirit, and be not to come scope of the present invention is limited with the above-mentioned preferred embodiment that is disclosed.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.
Claims (14)
1. base plate for packaging comprises:
One flexible dielectric layer, definition has a chip bonding area, and this chip bonding area is in order to be provided with a chip; And
One conductive layer is arranged on this flexible dielectric layer, and this conductive layer comprises:
Many root functionalitys pin is respectively by stretching out in this chip bonding area; And
Many dummy pin; Adjacent arrangement, wherein each dummy pin has a breach, and these breach lay respectively on the N bar datum line; N is the positive integer more than or equal to 2, the breach that wherein is close at least two adjacent dummy pin of these function pins stagger arrange non-conterminous.
2. base plate for packaging as claimed in claim 1 is characterized in that, this N bar datum line is parallel to each other.
3. base plate for packaging as claimed in claim 1 is characterized in that, the breach of wantonly two adjacent dummy pin stagger arrange non-conterminous.
4. base plate for packaging as claimed in claim 1 is characterized in that, these dummy pin are separated into a disjunct first and a second portion mutually by this breach respectively, and these dummy pin are respectively by stretching out in this chip bonding area.
5. base plate for packaging as claimed in claim 4 is characterized in that this chip comprises a plurality of contacts, when this chip is arranged at this chip bonding area, and corresponding respectively these function pins and these dummy pin of engaging of these contacts.
6. base plate for packaging as claimed in claim 1 is characterized in that these dummy pin become the loop shape.
7. base plate for packaging as claimed in claim 1 is characterized in that, these function pins, these dummy pin and these breach are to form with etching mode.
8. chip-packaging structure comprises:
One base plate for packaging comprises:
One flexible dielectric layer, definition has a chip bonding area; And
One conductive layer is arranged on this flexible dielectric layer, and this conductive layer comprises:
Many root functionalitys pin is respectively by stretching out in this chip bonding area; And
Many dummy pin; Adjacent arrangement, wherein each dummy pin has a breach, and these breach lay respectively on the N bar datum line; N is the positive integer more than or equal to 2, the breach that wherein is close at least two adjacent dummy pin of these function pins stagger arrange non-conterminous; And
One chip is arranged in this chip bonding area, and this chip comprises a plurality of first contacts and couples this many root functionalitys pin respectively.
9. chip-packaging structure as claimed in claim 8 is characterized in that, this N bar datum line is parallel to each other.
10. chip-packaging structure as claimed in claim 8 is characterized in that, the breach of wantonly two adjacent dummy pin stagger arrange non-conterminous.
11. chip-packaging structure as claimed in claim 8 is characterized in that, these dummy pin are separated into a disjunct first and a second portion mutually by this breach respectively, and these dummy pin are respectively by stretching out in this chip bonding area.
12. chip-packaging structure as claimed in claim 11 is characterized in that, this chip also comprises a plurality of second contacts and couples these dummy pin.
13. chip-packaging structure as claimed in claim 8 is characterized in that, these dummy pin become the loop shape.
14. chip-packaging structure as claimed in claim 8 is characterized in that, these function pins, these dummy pin and these breach are to form with etching mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910129666 CN101840903B (en) | 2009-03-18 | 2009-03-18 | Packaging substrate and chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910129666 CN101840903B (en) | 2009-03-18 | 2009-03-18 | Packaging substrate and chip packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101840903A CN101840903A (en) | 2010-09-22 |
| CN101840903B true CN101840903B (en) | 2012-05-23 |
Family
ID=42744186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910129666 Expired - Fee Related CN101840903B (en) | 2009-03-18 | 2009-03-18 | Packaging substrate and chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101840903B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103715162B (en) * | 2013-12-30 | 2017-09-29 | 日月光封装测试(上海)有限公司 | Lead frame bar for semiconductor packages |
| TWI726675B (en) * | 2020-04-09 | 2021-05-01 | 南茂科技股份有限公司 | Chip-on-film package structure |
| TWI713178B (en) * | 2020-04-16 | 2020-12-11 | 南茂科技股份有限公司 | Chip-on-film package structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1612323A (en) * | 2003-10-28 | 2005-05-04 | 株式会社东芝 | Method for wiring design of semiconductor integrated circuit and semiconductor integrated circuit |
-
2009
- 2009-03-18 CN CN 200910129666 patent/CN101840903B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1612323A (en) * | 2003-10-28 | 2005-05-04 | 株式会社东芝 | Method for wiring design of semiconductor integrated circuit and semiconductor integrated circuit |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2003-270655A 2003.09.25 |
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| Publication number | Publication date |
|---|---|
| CN101840903A (en) | 2010-09-22 |
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