CN101840306A - Method and system for driving SATA (Serial Advanced Technology Attachment) device in VxWorks operating system - Google Patents
Method and system for driving SATA (Serial Advanced Technology Attachment) device in VxWorks operating system Download PDFInfo
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- CN101840306A CN101840306A CN200910106066A CN200910106066A CN101840306A CN 101840306 A CN101840306 A CN 101840306A CN 200910106066 A CN200910106066 A CN 200910106066A CN 200910106066 A CN200910106066 A CN 200910106066A CN 101840306 A CN101840306 A CN 101840306A
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Abstract
The invention provides a method for driving an SATA (Serial Advanced Technology Attachment) device in the VxWorks operating system. The method comprises initialization and DMA (Direct Memory Access) read-write, wherein the initialization comprises the following steps of: (a) initializing an AHCI (Advanced Host Controller Interface) controller; (b) allocating an AHCI memory space; and (c) starting a port of the AHCI controller. The DMA read-write comprises the following steps of: (a) searching an empty command header in a command list; (b) initializing the command header structure of the empty command header; (c) initializing the command structure of one SATA queue; (d) encapsulating a command list; and (e) activating a command to realize the DMA read-write. Meanwhile, the invention also discloses a system for driving the SATA (Serial Advanced Technology Attachment) device in the VxWorks operating system. Through the method and the system provided by the invention, an SATA hard disk is driven by an AHCI mode in latest 6.6 version of VxWorks operating system and all previous versions.
Description
Technical field
The present invention relates to field of computer technology, more particularly, relate to the method and system of realizing driving SATA equipment in a kind of vxworks operating system.
Background technology
(Serial Advanced Technology Attachment is by Intel, IBM, Dell, APT, the hard-disk interface standard that proposes jointly with Seagate Technology of opening up advanced in years SATA) to Serial Advanced Technology Attachment.The appearance of Serial Advanced Technology Attachment standard will replace gradually parallel Advanced Technology Attachment (Parallel AdvancedTechnology Attachment, PATA).Parallel Advanced Technology Attachment adopts the parallel type transmission, and pin number is more, and the cable width is bigger, and makes the length limited of cable in order to reach transmitting synchronous.And the SATA hard disk drive is to adopt the string type transmission, and stitch line is less, and cable also can be longer, make install and use more or less freely.And the speed of SATA hard disk drive is faster, reaches as high as 600MB/S.SATA also possesses stronger error correcting capability, has improved reliability of data transmission to a great extent, also have simple in structure, support advantage such as hot plug.SATA can transmit all ATA and ATAPI agreement, and with ATA and the back compatible of SATA standard.The writing speed of first generation SATA is 150MB/S, and second generation SATA writing speed is up to 300MB/S, and up-to-date third generation SATA standard will realize the maximum data transfer rate of 600MB/S.
Vxworks operating system is that (Real-Time Operating System RTOS), is the key components of embedded-development environment to a kind of embedded real-time operating system of designing and developing in nineteen eighty-three of U.S. WindRiver company.In the high field of smart sharp technology such as its good sustained developing ability, high performance kernel, high reliability and remarkable real-time are widely used in and communicate by letters, military affairs, Aeronautics and Astronautics and real-time requirement.As a computer system, inevitably need to use exterior I/O equipment, the driver of I/O equipment provides accessibility and operability for it just.At present, vxworks operating system provides the support that multiple I/O device driver package is drawn together serial ports, parallel port, network interface card, ATA etc., all versions did not all provide the support with AHCI mode activated SATA equipment before but up-to-date 6.6 versions of vxworks operating system comprised, and, on vxworks operating system, realize it being necessary with AHCI mode activated SATA equipment in view of SATA many superiority and the trend that replaces PATA.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art and defective, a kind of method and system of realizing driving SATA equipment on vxworks operating system with the AHCI pattern is provided.
For achieving the above object, the embodiment of the invention provides following technical scheme: a kind of vxworks operating system realizes driving the method for SATA equipment down, comprises initialization and DMA read-write,
Wherein, described initialization comprises the steps:
A) initialization AHCI controller;
B) distribute the AHCI memory headroom;
C) port of startup AHCI controller;
Described DMA read-write comprises the steps:
A) in command list (CLIST), search a null command head;
B) the command header structure of the described null command head of initialization;
C) a SATA queue command of initialization structure;
D) command list of encapsulation;
E) activation command is realized the DMA read-write.
Described initialization AHCI controller specifically comprises:
The AHCI controller resets;
Start the AHCI function;
HOST CAP register is set;
Port is set realizes register;
The port controlling and the status register of the pci configuration space of configuration SATA controller;
The port of initialization AHCI controller.
The port of described initialization AHCI controller specifically comprises:
Obtain port parameter;
Setting up physical communication connects;
The error register zero clearing;
The interrupt status register zero clearing.
Described interrupt status register zero clearing comprises:
The zero clearing of port interrupt status register;
The zero clearing of controller interrupt status register.
Described distribution AHCI memory headroom specific implementation is:
In the physical memory space, mark off a continuous region of memory, the tabulation of described region of memory memory command, command list and reception FIS.
The port of described startup AHCI controller specifically comprises:
The base address of command list (CLIST) is set;
The base address that receives FIS is set;
Enable FIS Received dma controller;
Enable data transmission dma controller.
Also further comprise after the port of described startup AHCI controller:
The software reset;
Enable to interrupt.
Also further comprise before the described initialization AHCI controller or after enabling to interrupt:
Articulate interrupt service routine.
A kind of vxworks operating system realizes driving the system of SATA equipment down, comprising:
First initialization unit is used for initialization AHCI controller;
The Memory Allocation unit is used to distribute the AHCI memory headroom;
Data transmission unit is used to make and realizes the DMA read-write between AHCI controller and the SATA equipment.
System also further comprises:
Interrupt Process articulates the unit, is used to articulate interrupt service routine.
System also further comprises:
The Interrupt Process unit stores interrupt service routine, is used for handling interrupt requests.
Described data transmission unit comprises:
Search the unit, be used for looking for a null command head in command list (CLIST);
Second initialization unit is used for the command header structure and the SATA queue command structure of the described null command head of initialization;
Encapsulation unit is used to encapsulate a command list;
Activate the unit, be used for activation command.
As seen, the technical scheme that the embodiment of the invention provides has realized going up at vxworks operating system (6.6 and all versions) before and has realized driving the SATA hard disk in the AHCI mode.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is based on the system hardware topological structure synoptic diagram of Intel ICH South Bridge chip in the prior art;
Fig. 2 is a SATA system drive configuration diagram in the prior art;
Fig. 3 is the relational structure synoptic diagram between the data object of SATA;
Fig. 4 is an AHCI internal storage structure synoptic diagram;
Fig. 5 distributes synoptic diagram for a kind of memory headroom that the embodiment of the invention provides;
Fig. 6 drives the initial method process flow diagram for a kind of SATA that the embodiment of the invention provides;
A kind of initialization AHCI controller method process flow diagram that Fig. 6 a provides for the invention process;
A kind of initialization port method flow diagram that Fig. 6 b provides for the invention process;
Fig. 7 is the process flow diagram of a kind of DMA read-write in the prior art;
A kind of DMA read-write process flow diagram that Fig. 8 provides for the embodiment of the invention;
A kind of vxworks operating system that Fig. 9 provides for the embodiment of the invention realizes driving the system architecture synoptic diagram of SATA equipment down.
Embodiment
The embodiment of the invention with on vxworks operating system with AHCI (Serial ATA AdvancedHost Controller Interface, the serial ATA advanced host controller interface) mode activated SATA equipment is that example describes in detail with the AHCI SATA equipment that drives Intel ICH series South Bridge chip particularly.Wherein, described AHCI is under the guidance of Intel, and by the interface standard of many companies cooperative research and development, it allows store driver to enable senior SATA function, as this machine command queue and hot plug.
See also shown in Figure 1ly, Fig. 1 is based on the system hardware topological structure synoptic diagram of Intel ICH South Bridge chip in the prior art.From Fig. 1, can see, the South Bridge chip of Intel ICH7 series is integrated SATA controller, the SATA controller hangs on the pci bus as main equipment, and being articulated in SATA controller on the pci bus all has the pci configuration space register of oneself.The South Bridge chip of Intel ICH7 series is supported 4 ports, and each port articulates a SATA equipment.Each SATA equipment is all monopolized a transmission channel, can carry out independently dma operation, does not have the master/slave notion of PATA.All can carry out independently DMA (Direct Memory Access, directly internal memory operation) operation on each port, second generation SATA standard supports that data transmission rate is 300MB/S to the maximum.
See also shown in Figure 2ly, Fig. 2 is a SATA system drive configuration diagram in the prior art.Described SATA system drive framework comprises application program, I/O system layer, file system layer, SATA Drive Layer, hardware device.The SATA Drive Layer is between file system layer and the hardware device as can be seen from the figure, is articulated on the file system layer, calls each function that SATA drives to be provided by file system layer, such as the DMA read/write, comes operational hardware equipment.File system layer is articulated on the I/O system layer as driver, and the user is by visit I/O system layer access hardware devices.For the I/O system, the driver of SATA hardware device is sightless, and the user gives file system layer to the I/O request of file by the I/O systems communicate, and file system layer is made respective handling according to request.
In embodiments of the present invention, with Intel ICH South Bridge chip is example, described ICH South Bridge chip is integrated SATA controller, and described SATA controller is supported 4 ports, each port connects a memory device, and each equipment supports that depth capacity is 32 command queue.
See also shown in Figure 3ly, Fig. 3 is the relational structure synoptic diagram between the data object of SATA.As can be seen from Figure 3 each SATA controller has a plurality of (in the present embodiment being 4) port, and each port connects a SATA equipment, and it is the command queue of n (1≤n≤32) that each SATA equipment has a depth capacity.A plurality of orders are contained in each command queue, and every corresponding DMA of order asks or the PIO request, and each DMA request is by the command object representative relevant with the DMA object with data structure.PRDT (the Physical Region Descriptor Table that is used for the DMA transmission, the physical region descriptor table) supports maximum 65535 PRD (Physical Region Descriptor, the physical region descriptor), in addition, each controller has a controller registers group, and they have preserved the relevant information of controller; Each port has a port register group, and they have preserved the relevant information of port.Described PIO request is used for the facility information of acquisition request SATA equipment.
See also shown in Figure 4ly, Fig. 4 is an AHCI internal storage structure synoptic diagram.The generic domain of control and state is an AHCI controller register, and 32 ports such as Port 0～Port 31 grades are corresponding port register respectively.All have a command list (CLIST) base address register and one to receive the FIS base address register in each port register, be used for respectively the hold-over command tabulation the base address and receive the base address of FIS.Need to prove that the maximum of stipulating in the AHCI standard is supported 32 ports, and embodiment of the invention ICH7 South Bridge chip is supported 4 ports.
According to AHCI internal storage structure shown in Figure 4, the embodiment of the invention has defined following main data structure: SATA device programming information structure (SATA_ID_INFO), SATA device structure body (SATA_DEV), AHCI controller architecture body (AHCI_CTRL), AHCI port organization body (AHCI_PORT), receive FIS structure (RECIVED_FIS), SATA queue command structure (SATA_QC), command list (CLIST) structure (COMMAND_LIST), command header structure (COMMAND_HEADER), command list structure (COMMAND_TABLE), physical region descriptor structure body (AHCI_PRD).
In the embodiment of the invention, command header structure (COMMAND_HEADER) is defined as follows:
typedef?struct
{
UINT32 opts; / * command header descriptor: comprise the length (PRDTL) of physical region statement symbol table, whether support port Port Multiplier (PMP), the BIST position, the Reset position, order is looked ahead, the transmission direction zone bit, the ATAPI zone bit, order FIS length * such as (CFL)/
UINT32 status; / * coomand mode information: physical region descriptor byte number (PRDBC) */
UINT32 tbl_addr; / * command list base address, necessary 128 bit address alignment */
UINT32 tbl_addr_hi; High 32 * in/* command list base address/
UINT32 reserved[4]; The reservation territory * that/* is 4 32/
}COMMAND_HEADER；
In the embodiment of the invention, physical region descriptor structure body (AHCI_PRD) is defined as follows:
typedef?struct
{
UINT32 addr; / * wants the physical address of data block transmitted, necessary double byte alignment */
UINT32 addr_hi; / * want high 32 * of the physical address of data block transmitted/
UINT32 reserved; / * reservation territory */
UINT32 flags_size; / * descriptor: comprise interrupt complement mark position and data block size */
}AHCI_PRD；
In the embodiment of the invention, receive FIS structure (RECIVED_FIS) and be defined as follows:
typedef?struct
{
UINT8_t dsfis[0x20]; / * [00-20h] DMA set up frame information structure */
UINT8_t psfis[0x20]; / * [20-40h] PIO set up frame information structure */
UINT8_t rfis[0x18]; / * [40-58h] D2HRegister frame information structure */
UINT8_t sdbfis[0x8]; / * [58-60h]: be provided with equipment byte frame information structure */
UINT8_t unfis[0x40]; The unknown frame information structure of/* [60-A0H] */
UINT8_t reserved[0x5F]; / * [A0-FFH] reservation territory */
}RECIVED_FIS；
In the embodiment of the invention, the generic domain of described control and state (Generic Host Control) takies 32 bytes (00h-20h), described port 0 (Port0) takies 100h to 180h (amounting to 128 bytes), be followed successively by port one (Port1) to port 31 (Port31) from 180h to 1100h, each port takies 128 bytes.
Be example with port 0 (Port0) below, preserved the base address value of command list (CLIST) in the command list (CLIST) base address register of port 0, a command list (CLIST) comprises several command header structures (COMMAND_HEADER).In the embodiment of the invention, 32 command header structures (COMMAND_HEADER) are arranged in the command list (CLIST).Each command header structure occupies identical length, and each command header structure takies the length of 32 bytes in the embodiment of the invention.
See also shown in Figure 4, in the embodiment of the invention, each command header comprises PRDTL (PhysicalRegion Descriptor Table Length, the length of physical region descriptor table), CFL (Command FISLength, the length of order FIS), PRDBC (Physical Region Descriptor Byte Count, physical region is described byte count), CTBA0 (Command Table Base Address, represent the command list base address), the reservation position of CTBA_U0 (Command Table Base Address Up 32, represent command list base address high 32) and 16 bytes.Wherein, described COMMAND_TABLE is by CFIS (COMMAND FIS), and ACMD (ATAPI COMMAND) and PRDT form, and wherein, CFIS is the FIS encapsulating structure of main frame to the order of equipment transmission; Described ACMD is optionally, and it only uses when the order that sends is the ATAPI order; Described PRDT is the physical region descriptor table, and it is formed by reaching most the individual PRD of 65535 (64K).Each PRD has specified the pointer of the buffer zone that sends or receive data and the size of data block.
Preserved the base address value that receives FIS in the reception FIS base address register of described port 0.
Described reception FIS structure (RECIVE_FIS) is used for the FIS information that preservation equipment returns to main frame, comprise that specifically DMA sets up frame information structure (DMA SETUP FIS), PIO sets up frame information structure (PIO SETUP FIS), D2HRegister frame information structure (D2HRegisterFIS) and other unknown frame information structures.The length of each frame information structure is inequality.
See also shown in Figure 5, the embodiment of the invention has adopted a kind of unified Memory Distribution Map, promptly in initialization procedure, in physical memory, open up one section continuous space, be used for memory command tabulation (COMMAND_LIST), command list (COMMAND_TABLE) and receive FIS (ReceivedFIS).Wherein, command list (CLIST) (COMMAND_LIST) takies the space of 1024 bytes, the space that command list (COMMAND_TABLE) takies (80h+168*16) * 32 bytes, receives the physical space that FIS (ReceivedFIS) takies 256 bytes.
The internal storage structure that the embodiment of the invention is described at Fig. 4 is opened up one section space by drive software by the described memory allocation method of Fig. 5 and is used for driving in the actual physics internal memory.In driving initialization, finish the AHCI Memory Allocation and make it possible to carry out the DMA read-write operation.
The embodiment of the invention provides the method that realizes driving SATA equipment under a kind of vxworks operating system, comprises initialization and DMA read-write.
See also shown in Figure 6ly, Fig. 6 is a kind of initial method process flow diagram that the embodiment of the invention provides, and comprises step:
Step 601: articulate interrupt service routine (Interrupt Sever Routine, ISR).
In the embodiment of the invention, in the SATA system, the pci configuration space that drive software is read the SATA controller obtains the base address and the interrupt number of AHCI console controller, articulates interrupt service routine ISR.
Need to prove that step 601 also can be carried out, and does not influence the realization of technical scheme provided by the present invention after being arranged on step 606.
Step 602: initialization AHCI controller;
See also shown in Fig. 6 a, in the embodiment of the invention, described initialization AHCI controller specifically may further comprise the steps:
Step 6020:AHCI controller resets;
Refer to the internal reset to the AHCI controller in the embodiment of the invention, all status registers relevant with data transmission are all got back to idle condition, and all ports are reinitialized by the COMRESET signal.The embodiment of the invention realizes that by HR (HBA Reset) position of writing GHC (Global ICH7 Control) register in program AHCI resets.
Step 6021: start the AHCI function;
Step 6022: HOST CAP register is set;
HOST CAP register is one 32 a register.A kind of function that its each corresponding A HCI system device can provide.
In the embodiment of the invention, read described HOST CAP register earlier, do not support staggered the startup if do not support staggered startup (Staggered Spin-up) then to be provided with.
Step 6023: port is set realizes register (Ports Implemented Register);
The port of Intel ICH series South Bridge chip controller inside realizes that register is one 32 a register, wherein a port of low 4 each corresponding controllers (all the other are high-order for keeping the position).Being provided with the corresponding port position is 1, and promptly devices illustrated provides the support of this port, and software programming can be used it.Otherwise illustrating does not provide this port, promptly unavailable, and software just can not be visited this port corresponding port register.This step port realizes that a port of low 4 each the corresponding controllers of register is set to 1.
Step 6024: the port controlling and the status register of the pci configuration space of configuration SATA controller.
(Port Control and Status Register PCS) is 16 bit registers of skew 92h in the SATA configuration space registers for port controlling described in this step and status register.Its low 4 each corresponding ports, it is 1 that corresponding positions is set, and promptly activates corresponding port.After the activation, port just can transmit data and checkout equipment down in half duty (Partial) and sleep power supply status (Slumber).
Step 6025: the port of initialization AHCI controller;
See also shown in Fig. 6 b, in the embodiment of the invention, described step 6025 specifically may further comprise the steps:
Step 60250: obtain port parameter;
In the embodiment of the invention, obtain port parameter and comprise port numbers, register base address and skew, and when the apparatus bound state of front port etc.
Step 60251: set up physical communication and connect;
Step 60252: error register zero clearing;
Step 60253: interrupt status register zero clearing.
In the invention process, step 60253 specifically comprises zero clearing of port interrupt status register and the zero clearing of AHCI controller interrupt status register.
Step 603: distribute the AHCI memory headroom;
Step 604: the port that starts the AHCI controller;
In the embodiment of the invention, 4 AHCI director ports (port 0～port 3) that the South Bridge chip of Intel ICH7 series is supported all start.
Further, in the embodiment of the invention, described step 604 specifically comprises the steps:
Step 6041: the command list (CLIST) base address is set;
Step 6042: be provided with and receive the FIS base address;
Step 6043: enable FIS Received dma controller;
Step 6044: enable data transmission dma controller.
Further, in the embodiment of the invention, also further comprise after the described step 604:
Step 605: software reset;
Step 606: enable to interrupt.
In the step 606, comprise enabling the port interruption that the AHCI controller interrupts and enable the AHCI controller.
After initialization, carry out the DMA read-write, DMA read-write principle comprises: main frame sends write order to SATA equipment; The SATA controller detects order and writes, and with this order and the required parameter packing of fill order, transmits data to SATA equipment by SATA BUS downlink; SATA equipment fill order, and execution result and packing data be sent to the ATA controller by the SATA uplink; ATA controller cache data and update mode signal, waiting for CPU are taken data away or with the dma mode write memory.
See also shown in Figure 7ly, Fig. 7 is a reading and writing data process flow diagram in the prior art, comprises the steps:
Step 701: drive software is by the destination address of the dma controller of PCI setting, and transmission direction starts DMA;
Step 702: drive software is by register write parameters and the order of PCI to controller inside;
Step 703:DMA controller transport layer is provided with the busy sign of status register according to order, puts BSY=1, and establishment COMMAND FIS frame is transferred to equipment;
Step 704: equipment is prepared to receive data, is ready to complete back transmission DMA Active FIS frame and is transferred to equipment, enters step 707 then;
Step 705: if not more multidata reception, equipment sends it back answers FIS frame complete operation, enters step 708 then;
Step 706: write data is made mistakes or other are made mistakes, and then enters step 708;
Need to prove above-mentioned steps 704,705,706th, situation arranged side by side, the not branch of priority.
Step 707:DMA controller transport layer receives and imports data to link layer after DMA starts frame, and starts the real data transmission of DMA, and repeating step 704 is intact until Data Receiving;
Step 708:DMA controller is provided with status register and puts interrupt identification according to content frame after receiving response FIS frame, and removes dma controller, puts BSY=0.
In order to realize purpose of the present invention, the embodiment of the invention had been done relative set to software before the DMA read command sends.
See also shown in Figure 8, a kind of DMA read-write process flow diagram that Fig. 8 provides for the embodiment of the invention.Comprise step:
Step 801: in command list (CLIST), search a null command head;
In the embodiment of the invention, (Port Command IssueRegister) seeks by read port order transmitter register.Described order transmitter register is one 32 a register, each corresponding command header, and the position is 0 promptly to represent the command header of this correspondence for empty.
Step 802: the command header structure of the described null command head of initialization;
Send order to before the equipment, at first need the data structure of the command header structure of this null command head of initialization, each member variable assignment of command header structure.
Step 803: a SATA queue command of initialization structure (SATA_QC);
The SATA_QC structure is defined as follows:
typedef?struct
{
UINT32 flags；
UINT8 protocol；
UINT8 ctl；
UINT8 hob_feature；
UINT8 hob_nsect；
UINT8 hob_lbal；
UINT8 hob_lbam；
UINT8 hob_lbah；
UINT8 feature；
UINT8 nsect；
UINT8 lbal；
UINT8 lbam；
UINT8 lbah；
UINT8 device；
UINT8 command；
}SATA_QC；
Read to be example with DMA, in the embodiment of the invention several important parameters must be set:
Command code: Command=SATA_CMD_READ_DMA1; / * 0xC8, DMA read command */
Host-host protocol: protocol=SATA_PROT_DMA0; / * DMA transmission */
Number of transport blocks: nsect=blocks; The each data block transmitted number of/*, 512 byte * of each piece/and parameter such as feature, ctl, device, lbal, lbam, lbah, hob_lbal, hob_lbam, hob_lbah.
Step 804: encapsulate a command list;
In the embodiment of the invention, this step is filled in the structure that SATA_QC is packaged into an order FIS on the Command FIS position of command list with this FIS structure.
Step 805: activation command, realize the DMA read-write.
In embodiments of the present invention, the AHCI memory headroom is to distribute in initialization procedure, when carrying out data transmission described AHCI memory headroom of having distributed is filled upward suitable value, write order transmitter register more at last, order is sent to SATA equipment, SATA equipment is made corresponding response, thereby finishes the transmission (reading or writing) of data.
By said method, embodiment provided by the invention has realized going up the driving support that realizes the SATA hard disk at vxworks operating system (6.6 and all versions) before.
According to above-mentioned method, the embodiment of the invention also provides the system that realizes driving SATA equipment under a kind of vxworks operating system, and as shown in Figure 9, system comprises:
First initialization unit 901 is used for initialization AHCI controller;
Memory Allocation unit 902 is used to distribute the AHCI memory headroom;
Data transmission unit 903 is used to make and realizes the DMA read-write between AHCI controller and the SATA equipment.
Further, described system also comprises:
Interruption enables unit 904, is used to trigger interruptive command.
Need to prove, in the embodiment of the invention, first initialization unit 901, internal layer allocation units 902 and interruption enable unit 904 and are arranged in a driving initialization unit 905.
Further, described system also comprises:
Interruption articulates unit 906, is used to articulate interrupt service routine.
Interrupt Process unit 907 stores interrupt service routine, is used for handling interrupt requests.
Need to prove that described data transmission unit 903 comprises:
Search unit 9030, be used for looking for a null command head in command list (CLIST);
Second initialization unit 9031 is used for the command header structure and the SATA queue command structure of the described null command head of initialization.
Encapsulation unit 9032 is used to encapsulate a command list;
Activate unit 9033, be used for activation command.
Need to prove that the annexation between each unit that the embodiment of the invention provides is in order clearly to explain the needs of its information interaction control procedure, therefore only to be considered as annexation in logic, and should not only limit to physical connection.
By said system, embodiment provided by the invention has realized going up the driving that realizes the SATA hard disk at vxworks operating system (6.6 and all versions) before.
In sum, the embodiment of the invention is an example with the SATA controller of the compatible AHCI standard of driving Intel ICH series South Bridge chip, and the principle and the embodiment of the embodiment of the invention are set forth.As for the SATA individual chips or the expansion card of other manufacturers, equally all follow the SATA standard, just the definition of controller and some difference of AHCI normalized definition.For present technique field personnel, the technical scheme that provides by the embodiment of the invention can be developed the SATA drive software of other individual chips.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential hardware platform, can certainly all implement, but the former is better embodiment under a lot of situation by hardware.Based on such understanding, all or part of can the embodying that technical scheme of the present invention contributes to background technology with the form of software product, this computer software product can be stored in the storage medium, as ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out the described method of some part of each embodiment of the present invention or embodiment.
The embodiment of the invention has been used specific embodiment the principle and the embodiment of the embodiment of the invention has been set forth, and the explanation of above embodiment just is used to help to understand the method and the core concept thereof of the embodiment of the invention; Simultaneously, for one of ordinary skill in the art, according to the thought of the embodiment of the invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as the restriction to the embodiment of the invention.
Claims (12)
1. the following method that realizes driving SATA equipment of vxworks operating system is characterized in that, comprises initialization and DMA read-write,
Wherein, described initialization comprises the steps:
A) initialization AHCI controller;
B) distribute the AHCI memory headroom;
C) port of startup AHCI controller;
Described DMA read-write comprises the steps:
A) in command list (CLIST), search a null command head;
B) the command header structure of the described null command head of initialization;
C) a SATA queue command of initialization structure;
D) command list of encapsulation;
E) activation command is realized the DMA read-write.
2. method according to claim 1 is characterized in that, described initialization AHCI controller specifically comprises:
The AHCI controller resets;
Start the AHCI function;
HOST CAP register is set;
Port is set realizes register;
The port controlling and the status register of the pci configuration space of configuration SATA controller;
The port of initialization AHCI controller.
3. method according to claim 2 is characterized in that, the port of described initialization AHCI controller specifically comprises:
Obtain port parameter;
Setting up physical communication connects;
The error register zero clearing;
The interrupt status register zero clearing.
4. method according to claim 3 is characterized in that, described interrupt status register zero clearing comprises:
The zero clearing of port interrupt status register;
The zero clearing of controller interrupt status register.
5. method according to claim 1 is characterized in that, described distribution AHCI memory headroom specific implementation is:
In the physical memory space, mark off a continuous region of memory, the tabulation of described region of memory memory command, command list and reception FIS.
6. method according to claim 1 is characterized in that, the port of described startup AHCI controller specifically comprises:
The base address of command list (CLIST) is set;
The base address that receives FIS is set;
Enable FIS Received dma controller;
Enable data transmission dma controller.
7. method according to claim 1 is characterized in that, also further comprises after the port of described startup AHCI controller:
The software reset;
Enable to interrupt.
8. according to each described method of claim 1～7, it is characterized in that, also further comprise before the described initialization AHCI controller or after enabling to interrupt:
Articulate interrupt service routine.
9. the following system that realizes driving SATA equipment of vxworks operating system is characterized in that, comprising:
First initialization unit is used for initialization AHCI controller;
The Memory Allocation unit is used to distribute the AHCI memory headroom;
Data transmission unit is used to make and realizes the DMA read-write between AHCI controller and the SATA equipment.
10. system according to claim 9 is characterized in that, also further comprises:
Interrupt Process articulates the unit, is used to articulate interrupt service routine.
11. system according to claim 9 is characterized in that, also further comprises:
The Interrupt Process unit stores interrupt service routine, is used for handling interrupt requests.
12. system according to claim 9 is characterized in that, described data transmission unit comprises:
Search the unit, be used for looking for a null command head in command list (CLIST);
Second initialization unit is used for the command header structure and the SATA queue command structure of the described null command head of initialization;
Encapsulation unit is used to encapsulate a command list;
Activate the unit, be used for activation command.
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