CN101834185B

CN101834185B - Nitride nonvolatile read-only memory

Info

Publication number: CN101834185B
Application number: CN2009100474365A
Authority: CN
Inventors: 罗双菊; 王永刚; 闫锋; 常建光
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2009-03-12
Filing date: 2009-03-12
Publication date: 2012-05-30
Anticipated expiration: 2029-03-12
Also published as: CN101834185A

Abstract

The invention discloses a nitride nonvolatile read-only memory, comprising a silicon substrate. Bit lines distributed uniformly with equal pitch are embedded in the surface of the silicon substrate, and word lines are distributed with equal pitch on the upper surface of the silicon substrate among the bit lines. The word lines clamped between adjacent bit lines and the adjacent bit lines form an MOS (Metal Oxide Semiconductor) transistor. The adjacent bit lines are used as a source electrode and a drain electrode, respectively. The word lines, from top to bottom, comprise polysilicon layers, upper oxide layers, nitride layers and lower oxide layers which are used as a gate electrode medium layer of the MOS transistor; N adjacent bit lines in sequence are used as a bit line group, and isolating word lines are arranged between the adjacent bit line groups. The width of the isolating word lines is greater than that of the word lines in the group. In the nitride nonvolatile read-only memory, the shallow groove isolation area is cancelled so that side effect which may be brought by the hallow groove isolation area is avoided, and the rate of finished products of the nitride nonvolatile read-only memory is improved.

Description

Nitride nonvolatile read-only memory

Technical field

The present invention relates to the semiconductor memory technologies field, particularly nitride nonvolatile read-only memory.

Background technology

Non-volatile read-only memory device, for example read-only memory (ROM), programmable read-only memory (prom), Erasable Programmable Read Only Memory EPROM (EPROM) and other more senior Nonvolatile memory device have been widely used in fields such as mobile phone, notebook computer, palmtop PC, digital camera.

The key property of nitride nonvolatile read-only memory (NROM) is its dibit memory cell, can be fit to very much make portable mass storage, for example in-line memory in two different data bit of a memory cell storage.The principle of NROM memory cell is that electric charge is caught in the part in the nitrogen layer in ONO (oxygen-nitrogen-oxygen) grid dielectric material.

Fig. 1 is the cross-sectional view of 90 nanometer NROM memory cell in the prior art.The upper surface of silicon base 101 embeds equidistant equally distributed bit line, the equally spaced word line 102 that distributing of silicon base 101 upper surfaces between the bit line, and word line 102 can be made up of amorphous silicon or DOPOS doped polycrystalline silicon.The width of each word line 102 is 130～150 nanometers, and the spacing between the adjacent word line 102 is 50～70 nanometers.Word line folded between adjacent bit lines and the said adjacent bit lines is formed MOS transistor, and said adjacent bit lines is respectively as source electrode and drain electrode.Source/drain generates through the mode of implant impurity, and said impurity can be N type alloy such as phosphonium ion or arsenic ion, can also be P type alloy such as boron ion.Word line 102 comprises polysilicon layer from top to bottom, goes up oxide skin(coating), nitride layer and following oxide skin(coating), the said gate dielectric layer of going up oxide skin(coating), nitride layer and following oxide skin(coating) as MOS transistor.The boundary of each bit line and adjacent word line is called data bit (Edge Bit) 103, and each data bit 103 is used to write down a bit.On 90 nanometer NROM memory cell; Per 34 bit lines are divided into one group, between the adjacent set with shallow trench isolation from (Shallow Trench Isolation, STI) district 107 separates; Be called edge bit line 104 with STI district 107 adjacent bit lines; Be positioned at the effect that the bit line in STI district does not write down bit, therefore be called pseudo-bit line 106, other bit line then is called non-edge bit line 105.

The principle of NROM storage data is exactly that two data bit of bit line can be in two different level states of height.But in fact each level state is not single level value, but a threshold distribution of level value (Voltage Threshold, VT) as shown in Figure 2.On voltage coordinate, be the minimum threshold (VTHL) of low level minimum threshold (VTLL), low level max-thresholds (VTLH), high level and the max-thresholds (VTHH) of high level from small to large successively.If but high level and low level difference are too small, the situation that VTLH and VTHL size is exchanged might appear.And STI district 107 occurs and designs for fear of this situation.

But the existence in STI district; Can bring following problem: owing to the reason of the process aspect of processing the STI district; Can there be difference in height in the upper surface of the upper surface in STI district and silicon base 101; This critical dimension (Critical Dimension) that can cause edge bit line 104 and non-edge bit line 105 is deviation to some extent, and can raise the level threshold of edge bit line 104.Secondly, the STI district can obviously suppress near the electron mobility the STI district, and this also can raise the level threshold of edge bit line 104.In addition, the STI district also can influence the diffusion way of alloy in silicon base, makes dopant profiles become unpredictable.Above factor all can cause harmful effect to rate of finished products.

Summary of the invention

In view of this, the present invention proposes a kind of nitride nonvolatile read-only memory (NROM), in said NROM, has cancelled the STI district, thereby has improved the rate of finished products of NROM.

The embodiment of the invention proposes a kind of nitride nonvolatile read-only memory, comprising: silicon base, there is not shallow channel isolation area in the said silicon base; Upper surface in silicon base embeds equidistant equally distributed bit line, the word line that equidistantly distributes of the silicon base upper surface between the bit line; Word line folded between adjacent bit lines and the said adjacent bit lines is formed MOS transistor; Said adjacent bit lines is respectively as source electrode and drain electrode; Said word line comprises polysilicon layer from top to bottom, goes up oxide skin(coating), nitride layer and following oxide skin(coating), the said gate dielectric layer of going up oxide skin(coating), nitride layer and following oxide skin(coating) as MOS transistor; With an adjacent successively N bit line is a set of bit lines, between the adjacent bit lines group isolation word line is set, and the width of said isolation word line is more than or equal to the overall width at the interval between existing two word lines and this two word lines, and said N is a natural number.

Spacing in the said set of bit lines between the adjacent word line, and the spacing between isolation word line and the word line that is adjacent is 50～70 nanometers.

Preferably, the wordline width in the same said set of bit lines is 130～150 nanometers, and the isolation word line width between the adjacent bit lines group is 330～350 nanometers.

Preferably, said N is 34.

The embodiment of the invention also proposes a kind of nitride nonvolatile read-only memory, comprising: silicon base, there is not shallow channel isolation area in the said silicon base; Upper surface in silicon base embeds equidistant equally distributed bit line, the word line that equidistantly distributes of the silicon base upper surface between the bit line; Word line folded between adjacent bit lines and the said adjacent bit lines is formed MOS transistor; Said adjacent bit lines is respectively as source electrode and drain electrode; Said word line comprises polysilicon layer from top to bottom, goes up oxide skin(coating), nitride layer and following oxide skin(coating), the said gate dielectric layer of going up oxide skin(coating), nitride layer and following oxide skin(coating) as MOS transistor; With an adjacent successively N bit line is a set of bit lines, between the adjacent bit lines group isolation word line is set, and said isolation word line and bit line have a common boundary and be set to high level, and said N is a natural number.

Preferably, the isolation word line width between the said adjacent bit lines group equals the wordline width in the set of bit lines.

Can find out from above technical scheme; Isolation word line width through broad is set or the isolation word line between the adjacent bit lines group and bit line have a common boundary and are set to high level; Can play the effect that the surface electronic between the edge bit line that prevents the isolation word line both sides leaks, thereby substitute the effect of shallow channel isolation area in the prior art.And because the nitride nonvolatile read-only memory that the present invention proposes is not provided with shallow channel isolation area, avoided the negative effect of shallow channel isolation area, can improve the rate of finished products of nitride nonvolatile read-only memory.

Description of drawings

Fig. 1 is the cross-sectional view of 90 nanometer NROM memory cell in the prior art.

Fig. 2 is the level threshold distribution map of the data bit of NROM bit line;

Fig. 3 is the cross-sectional view of 90 nanometer NROM memory cell of the embodiment of the invention.

Embodiment

For making the object of the invention, technical scheme and advantage clearer, the present invention is done further to set forth in detail below in conjunction with accompanying drawing.

Fig. 3 is the cross-sectional view of 90 nanometer NROM memory cell of the embodiment of the invention.Wherein, all the counterpart with shown in Figure 1 is identical for silicon base 101, word line 102, data bit 103, edge bit line 104, non-edge bit line 105.Be that per 34 bit lines are no longer separated through STI, but adopt isolation word line (Isolation Word-line) 306 to replace.Isolation word line 306 is just the same with the structure of word line 102, and just width is bigger than the width of word line 102.If the span of the width of isolation word line polysilicon 306 is too big, then can reduce space availability ratio.

Preferably, the width of isolation word line 306 is equivalent to the overall width at the interval between existing two word lines and this two word lines, i.e. 330～350 nanometers.Isolation word line 306 is called isolation position 307 with the boundary of edge bit line 104.Because the width of isolation word line 306 is enough big, can prevent effectively that the surface electronic between the edge bit line 104 of isolation word line 306 both sides from leaking.

Another embodiment of the present invention can further be dwindled the width of isolation word line 306, can its scope be set to equal the critical size of word line.In this case; Though the width of isolation word line 306 is not enough to prevent that the surface electronic between the edge bit line 104 from leaking; Can place high level all the time with isolating position 307; Be equivalent to improve the potential barrier of electron transfer between the edge bit line 104 of isolation word line 306 both sides, thereby prevent that the electronics between the edge bit line 104 from leaking.The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims

1. nitride nonvolatile read-only memory comprises: silicon base, there is not shallow channel isolation area in the said silicon base; Upper surface in silicon base embeds equidistant equally distributed bit line, the word line that equidistantly distributes of the silicon base upper surface between the bit line; Word line folded between adjacent bit lines and the said adjacent bit lines is formed MOS transistor; Said adjacent bit lines is respectively as source electrode and drain electrode; Said word line comprises polysilicon layer from top to bottom, goes up oxide skin(coating), nitride layer and following oxide skin(coating), the said gate dielectric layer of going up oxide skin(coating), nitride layer and following oxide skin(coating) as MOS transistor; It is characterized in that; With an adjacent successively N bit line is a set of bit lines; Between the adjacent bit lines group isolation word line is set, the width of said isolation word line is more than or equal to the overall width at the interval between existing two word lines and this two word lines, and said N is a natural number.

2. nitride nonvolatile read-only memory according to claim 1 is characterized in that, the spacing in the said set of bit lines between the adjacent word line, and the spacing between isolation word line and the word line that is adjacent is 50～70 nanometers.

3. nitride nonvolatile read-only memory according to claim 1 is characterized in that, the wordline width in the same said set of bit lines is 130～150 nanometers, and the isolation word line width between the adjacent bit lines group is 330～350 nanometers.

4. according to claim 1,2 or 3 described nitride nonvolatile read-only memories, it is characterized in that said N is 34.

5. nitride nonvolatile read-only memory comprises: silicon base, there is not shallow channel isolation area in the said silicon base; Upper surface in silicon base embeds equidistant equally distributed bit line, the word line that equidistantly distributes of the silicon base upper surface between the bit line; Word line folded between adjacent bit lines and the said adjacent bit lines is formed MOS transistor; Said adjacent bit lines is respectively as source electrode and drain electrode; Said word line comprises polysilicon layer from top to bottom, goes up oxide skin(coating), nitride layer and following oxide skin(coating), the said gate dielectric layer of going up oxide skin(coating), nitride layer and following oxide skin(coating) as MOS transistor; It is characterized in that, be a set of bit lines with an adjacent successively N bit line, between the adjacent bit lines group isolation word line is set, and said isolation word line and bit line have a common boundary and be set to high level, and said N is a natural number.

6. nitride nonvolatile read-only memory according to claim 5 is characterized in that, the isolation word line width between the said adjacent bit lines group equals the wordline width in the set of bit lines.