CN101834177B

CN101834177B - SOC (System On a Chip) chip device

Info

Publication number: CN101834177B
Application number: CN 201010178082
Authority: CN
Inventors: 张亮; 罗升龙
Original assignee: RDA MICROELECTRONICS CO Ltd
Current assignee: RDA MICROELECTRONICS CO Ltd
Priority date: 2010-05-20
Filing date: 2010-05-20
Publication date: 2011-11-16
Anticipated expiration: 2030-05-20
Also published as: CN101834177A

Abstract

The present invention discloses an SOC ((System On a Chip)) chip device. The SOC chip device encapsulation comprises a SDRAM (Synchronous Dynamic Random Access Memory) chip, wherein the SDRAM chip is connected with the SOC chip by gold wires. Moreover, a rise and fall time control circuit including an on-off circuit is arranged on a pin connecting the SOC chip and the SDRA chip. The SOC chip device effectively reduces electromagnetic radiation generated by SDRAM signal wires, and the interference of a wireless front end by the SDRAM signal wires is reduced, and the signal to noise ratio of last received signals and the integration level of the device are provided.

Description

The SOC chip device

Technical field

The present invention relates to a kind of semiconductor device, especially a kind of SOC chip device.

Background technology

SDRAM (synchronous dynamic random access memory) synchronous dynamic random access memory is widely used in the hyundai electronics design.Its maximum characteristics are high power capacity, and are high-speed, are used as data space or program's memory space.Its common speed of service is usually tens, even on 100,000,000 frequencies.High speed signal like this, as easy as rolling off a log generation high frequency radiation signal.Add that simultaneously the SDRAM holding wire is various, radiation source also increases thereupon, and plate level EMI (Electro Magnetic Compatibility) has been proposed very high requirement.In the handheld terminal conceptual design, the radiation of high speed devices such as SDRAM and FLASH always all is a stubborn problem.In the prior art, for fear of the interference that radiation brought, SDRAM chip device and SOC chip all are to encapsulate separately, separately are arranged on then on the pcb board, reduce to disturb by increasing by two distances between the chip.

Summary of the invention

Technical problem to be solved by this invention provides a kind of SOC chip device, can reduce the mutual interference mutually of SDRAM chip and radio-frequency module greatly, improves the Signal-to-Noise of whole link, and can improve the integrated level of device.

For solving the problems of the technologies described above, the technical scheme of SOC chip device of the present invention is, in described SOC chip device encapsulation, also comprises the SDRAM chip, and described SDRAM chip is connected by gold thread with described SOC chip; On the pin that connects with the SDRAM chip of SOC chip, also be provided with the rise and fall time control circuit in addition.

Further improvement as SOC chip device of the present invention is, comprise switching circuit in the described rise and fall time control circuit, described switching circuit comprises first resistance successively from the power end to the earth terminal, first switch, the one PMOS pipe, the second switch and second resistance, described first switch is connected to the source electrode of a PMOS pipe, described second switch is connected to the grid and the drain electrode of a PMOS pipe, the grid of a described PMOS pipe is used for the input of SDRAM data, the source electrode of a described PMOS pipe is by a capacity earth, the source electrode of the one PMOS pipe also connects the grid of the 2nd PMOS pipe, the drain electrode of described the 2nd PMOS pipe and substrate terminal ground connection, the source electrode of the 2nd PMOS pipe are used for the output of SDRAM data.

The present invention is very effective to have reduced the electromagnetic radiation that the SDRAM holding wire is produced, and reduces its interference to wireless front end, has improved the signal to noise ratio of last received signal, and has also improved the integrated level of device.

Description of drawings

The present invention is further detailed explanation below in conjunction with drawings and Examples:

The schematic diagram that Fig. 1 refluxes for this ideal signal;

Fig. 2 is the signal backflow schematic diagram in the actual conditions;

Fig. 3 is the magnetic field coupling schematic diagram of signal circuit;

Fig. 4 is the schematic diagram of rise and fall time control circuit in the SOC chip device of the present invention;

Fig. 5 is the schematic diagram of SOC chip device chips of the present invention position.

Embodiment

Electromagnetic interference is EMI (Electromagnetic Interference), refers to that system passes through conduction or radiation, and launching electromagnetic wave also influences other system or the operate as normal of interior other subsystems of native system.For EMI, can be divided into radiated interference, conducted interference and three kinds of forms of induction coupled interference according to the approach of electromagnetic interference.Radiated interference just is meant if the harassing and wrecking source is not to be in the totally enclosed metal shell, and it just can pass through the outside radiated electromagnetic wave in space, and its radiation field intensity depends on the harassing and wrecking current strength of device, the equiva lent impedance of device, and the tranmitting frequency in harassing and wrecking source.If the metal shell in harassing and wrecking source has slit and hole, then the intensity of radiation is relevant with the wavelength of interference signal.When if the size of hole and wavelength can be compared, then can form disturb sub-radiation source to around radiation, metal object can also form secondary radiation in the radiation field; Conducted interference, as its name suggests, the harassing and wrecking source mainly is to utilize coupled lead to external emission, also can be coupled by common impedance, or the grounded circuit coupling, bring interference into other circuit, conducted interference is a kind of important form of electromagnetic interference; The approach of induction coupled interference is the 3rd approach between radiation approach and pathway, and when the frequency in harassing and wrecking source was hanged down, the radianting capacity of harassing and wrecking power supply was limited.Harassing and wrecking simultaneously directly are not connected with other conductor again, and this moment, the electromagnetic disturbance energy then produced the induction coupling by the conductor that is adjacent, and electromagnetic energy is transferred to other conductors get on, and went out to harass electric current or voltage at the proximity conductor internal induction.Induction coupling can occur by the capacity coupled form between conductor, also can be occurred by the form of inductance coupling high or electric capacity, inductance mixed.

The generation of EMI has two kinds of paths usually, mainly is that voltage transient and signal reflux two kinds.

During high-speed figure, the voltage transient when producing high frequency ac signal is a major reason that produces electromagnetic interference.The frequency spectrum that digital signal produces when switch is exported is not single, but merged a lot of higher harmonic components, and the amplitude of these harmonic waves was decided by the rising or the fall time of device, and signal rises and descends fast more, switching frequency is high more, and then the emittance of Chan Shenging is many more.Leaking of this electromagnetic energy will cause electromagnetic interference problem.

The reason that another one produces electromagnetic radiation is exactly that signal refluxes.Ideally, reflux as shown in Figure 1, be present in the reference planes under the signal lead.But it is many-sided that the fact of case signal refluxes: reference planes, and adjacent traces, medium all might become the backflow approach.In the ideal case because the loop area between signal and the ground backflow is very little, so the EMI that produces is also very low.If but when having non-ideal factor such as slit on the adjacent reference planes, the area that can cause refluxing increases, the coupling of low inductance weakens, and will have more electromagnetic energy radiation increases, as shown in Figure 2.

Fig. 3 comes analyzing influence EMI size from the angle of the magnetic line of force.As we can see from the figure: signal and backflow perimeter because the polarity in magnetic field is opposite, can cancel out each other, and recirculating zone, middle part the action of a magnetic field is to strengthen mutually, so it are to extraradial main source.We see as long as the distance between shortening signal and the backflow just can well be offset peripheral influence from this figure, also can suppress the influence of this loop to external circuit greatly simultaneously.

The invention discloses a kind of SOC chip device, as shown in Figure 5, in described SOC chip device encapsulation, also comprise the SDRAM chip, described SDRAM chip is connected by gold thread with described SOC chip.

As shown in Figure 4, on the pin that connects with the SDRAM chip of SOC chip, also be provided with the rise and fall time control circuit, comprise switching circuit in the described rise and fall time control circuit, described switching circuit comprises first resistance successively from the power end to the earth terminal, first switch, the one PMOS pipe, the second switch and second resistance, described first switch is connected to the source electrode of a PMOS pipe, described second switch is connected to the grid and the drain electrode of a PMOS pipe, the grid of a described PMOS pipe is used for the input of SDRAM data, the source electrode of a described PMOS pipe is by a capacity earth, the source electrode of the one PMOS pipe also connects the grid of the 2nd PMOS pipe, the drain electrode of described the 2nd PMOS pipe and substrate terminal ground connection, the source electrode of the 2nd PMOS pipe are used for the output of SDRAM data.

In the embodiment of Fig. 4, comprise the switching circuit that many groups are connected in parallel in the described rise and fall time control circuit, the grid of a PMOS pipe all is used for the input of SDRAM data in each switching circuit, and the source electrode of a PMOS pipe of last switching circuit connects described electric capacity.

Irctrl is one group of rise time control signal.When its switch closure, to the resistance decreasing between the load capacitance Ci, it is big that charging current becomes from power supply, and signal elevating time shortens.By Irctrl＜x:0〉configuration of bus control signal, wherein x is the quantity of switching circuit, can change the rise time of output signal, and closed number of switches is many more, and the rise time of signal is just short more.If the rise time is elongated, mean that then the frequency of radiation signal diminishes, the energy of its high order harmonic component diminishes, to the also corresponding minimizing of the radiation of high band.

In like manner, Ifctrl be one group fall time control signal.When its switch closure, big from the discharging current change of load capacitance Ci, shorten discharge time, and signal shortens fall time.By control Ifctrl＜x:0〉bus signals, can change fall time of output signal, the radiation signal of introducing when effectively control signal descends.

As shown in Figure 5, described SDRAM chip is set at the zone of digital circuit part on the SOC chip.

In the described SOC chip, radio-frequency module is set at the corner of chip.

Described SDRAM chip is connected by short as far as possible gold thread with described SOC chip.

In Fig. 5, bottom chip is the SOC chip, is the SDRAM chip above, and intermediate connection is a gold thread.The SOC chip layout reduces electromagnetic radiation for considering in this embodiment, and done corresponding design: the radio frequency part circuit is arranged at A district among Fig. 5, and the easiest radio frequency input pin that is disturbed is placed on the chip upper left corner.The B district is other analog circuits that receive link, comprises analog filter, phase-locked loop, digital to analog converter, analog to digital converter etc.The numerical portion circuit is arranged at the C district, be positioned at SDRAM under.Be all digital circuit, the interference between them can not exert an influence to circuit function.It is very short to connect gold thread, has only 1～2 millimeter usually, and the current circuit area is very little.Contrast tradition is placed on design on the pcb board with SDRAM, the intensity of its radiation be the plate level 1/tens in addition littler.The power supply of SDRAM and the loop between the ground are also along with this design becomes very little simultaneously, and radiation can be limited in the very little scope.

The present invention starts with from two aspects in order to reduce the holding wire radiated interference of SDRAM, and first reduces the area that holding wire refluxes, and second reduces the rise time and the fall time of holding wire.Consider that from these two starting points the present invention is encapsulated in SDRAM in SOC (System On Chip, the SOC (system on a chip)) chip.The present invention fixedly is stacked in SDRAM chip nude film on the SOC chip, and the pad part is reserved the pad that connects with SDRAM at the SOC chip internal up, with golden line this two chips is linked together then.Because the pad of SDRAM and the pad of SOC are direct-connected with gold thread, the general length of gold thread is 1～2 millimeter, and just the current circuit area is very little, and it is little a lot of to walk line loop than plate level PCB, therefore the EMI radiation that produces also with little a lot, can effectively reduce the interference to the less radio-frequency front-end circuit.On the pad that connects with SDRAM of SOC, added output and driven controlable electric current in addition, can effectively control rise time and the fall time of pad, reduced signal and changed along radiation to peripheral circuit.SDRAM is encapsulated in and makes the control on this time edge can not influence the access speed of SDRAM in the SOC, because the signal lag of SDRAM is because SDRAM is encapsulated in the SOC by corresponding shortening.

In sum, the present invention is very effective to have reduced the electromagnetic radiation that the SDRAM holding wire is produced, and reduces its interference to wireless front end, has improved the signal to noise ratio of last received signal, and has also improved the integrated level of device.

Claims

1. a SOC chip device is characterized in that, in described SOC chip device encapsulation, also comprises the SDRAM chip, and described SDRAM chip is connected by gold thread with described SOC chip; On the pin that connects with the SDRAM chip of SOC chip, also be provided with the rise and fall time control circuit in addition.

2. SOC chip device according to claim 1, it is characterized in that, comprise switching circuit in the described rise and fall time control circuit, described switching circuit comprises first resistance successively from the power end to the earth terminal, first switch, the one PMOS pipe, the second switch and second resistance, described first switch is connected to the source electrode of a PMOS pipe, described second switch is connected to the grid and the drain electrode of a PMOS pipe, the grid of a described PMOS pipe is used for the input of SDRAM data, the source electrode of a described PMOS pipe is by a capacity earth, the source electrode of the one PMOS pipe also connects the grid of the 2nd PMOS pipe, the drain electrode of described the 2nd PMOS pipe and substrate terminal ground connection, the source electrode of the 2nd PMOS pipe are used for the output of SDRAM data.

3. SOC chip device according to claim 2, it is characterized in that, comprise the switching circuit that many groups are connected in parallel in the described rise and fall time control circuit, the grid of a PMOS pipe all is used for the input of SDRAM data in each switching circuit, and the source electrode of a PMOS pipe of last switching circuit connects described electric capacity.

4. according to any described SOC chip device in the claim 1～3, it is characterized in that described SDRAM chip is set at the zone of digital circuit part on the SOC chip.

5. according to any described SOC chip device in the claim 1～3, it is characterized in that in the described SOC chip, also comprise radio-frequency module, described radio-frequency module is set at the corner of chip.