CN101833931A - Liquid crystal display device - Google Patents

Abstract

The invention discloses a liquid crystal display device, comprising a source driver for providing multiple data signals, a gate driver for modulating voltage according to a high-potential gate signal to provide multiple gate signals, and a gate driver for providing multiple Data and gate signals are used to display image pixel array units and gate pulse modulation units. The gate driver can also perform power-off afterimage attenuation operation on the pixel array unit according to the reset signal. The gate pulse modulating unit is used to provide a high-potential gate signal modulating voltage, so as to perform waveform chamfering operation on a plurality of gate signals. The waveform clipping operation has a voltage clamping function controlled by a reset signal, and the voltage clamping function is disabled within a predetermined period of time after the liquid crystal display device is turned on.

Description

Liquid crystal display device

technical field

The invention relates to a liquid crystal display device, in particular to a liquid crystal display device capable of avoiding the phenomenon of noise in the start-up screen.

Background technique

Liquid crystal display (Liquid Crystal Display; LCD) has the advantages of light and thin appearance, power saving and low radiation, so it has been widely used in computer screens, mobile phones, personal digital assistants (PDAs), flat-screen TVs, and other communication/ Electronic products such as entertainment equipment. The working principle of the liquid crystal display device is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference between the two ends of the liquid crystal layer, thereby changing the light transmittance of the liquid crystal layer, and then cooperate with the light source provided by the backlight module to display images. FIG. 1 is a schematic diagram of a conventional liquid crystal display device. As shown in FIG. 1 , the liquid crystal display device 10 includes a pixel array unit 100 having a plurality of pixels PX, a source driver 104 , a gate driver 106 , and a gate pulse modulation (GatePulse Modulation) unit 120 . The source driver 104 is used to provide a plurality of data signals to the pixel array unit 100 . The gate driver 106 is used to modulate the voltage VGHM and the low-potential gate signal reference voltage VGL according to the high-potential gate signal to provide a plurality of gate signals to the pixel array unit 100, and the pixel array unit 100 is based on a plurality of data signals and a reference voltage VGL. Multiple gate signals to display images. The gate driver 106 can also perform power-off afterimage attenuation operation on the pixel array unit 100 according to the reset signal XON.

The gate pulse modulation unit 120 is used for providing a high potential gate signal modulation voltage VGHM. The gate pulse modulation unit 120 includes an inverter 140 , a first transistor 130 , a second transistor 135 , a resistor Rx, and a diode 125 . The inverter 140, the first transistor 130, the second transistor 135 and the resistor Rx are used to pull down the high-potential gate signal modulation voltage VGHM from the high-potential gate signal reference voltage VGH according to the chamfering control signal VFLK, thereby performing gate The waveform clipping operation of the pole signal, and the diode 125 has a voltage clamping function for the waveform clipping operation according to the clamping voltage Vclamp. During the operation of the liquid crystal display device 10, the clamping voltage Vclamp can quickly rise to the input voltage level and be fed into the gate driver 106 through the diode 125 within a predetermined period of time after starting up, but at this time the low potential gate signal reference The voltage VGL has not yet established a working potential, so the gate driver 106 cannot perform normal logic operations, thus generating a plurality of noise-like gate signals. Since the reset signal XON at this time will enable the gate driver 106 to simultaneously output all gate signals to the pixel array unit 100, that is, the multiple noise-like gates generated by the gate driver 106 within a predetermined period of time after power-on. All polar signals will be fed into the pixel array unit 100 , which will cause noise phenomenon in the boot screen. In other words, the noise phenomenon is caused by the voltage clamp function being enabled during the predetermined period of power-on.

Contents of the invention

According to an embodiment of the present invention, a liquid crystal display device capable of avoiding noise in a boot screen is disclosed, which includes a pixel array unit, a source driver, a gate driver, and a gate pulse modulation unit. The pixel array unit is used for performing image display operation. The source driver is electrically connected to the pixel array unit and is used for providing multiple data signals required by the pixel array unit to perform image display operation. The gate driver is electrically connected to the pixel array unit, and is used to modulate the voltage according to the high-potential gate signal to provide multiple gate signals required for the pixel array unit to perform image display operations, and is used to execute the pixel array unit according to the reset signal. Power off afterimage attenuation operation. The gate pulse modulation unit is electrically connected to the gate driver for providing a high-potential gate signal modulation voltage, and the gate pulse modulation unit has a voltage clamping function controlled by a reset signal. In the operation of the liquid crystal display device, within a predetermined period after the liquid crystal display device is turned on, the reset signal is in the first state to disable the voltage clamping function, and after the predetermined period, the reset signal is switched to a state different from the first state In the second state, the voltage clamping function is enabled.

According to the embodiment of the present invention, a liquid crystal display device capable of avoiding noise phenomenon in the start-up screen is disclosed, which includes a source driver, a gate driver, a pixel array unit, and a gate pulse modulation unit. The source driver is used to provide multiple data signals. The gate driver is used to modulate the voltage according to the high potential gate signal to provide multiple gate signals. The pixel array unit is electrically connected to the source driver and the gate driver for displaying images according to a plurality of data signals and a plurality of gate signals. The gate pulse modulation unit is electrically connected to the gate driver for providing a high potential gate signal modulation voltage, and the gate pulse modulation unit has a voltage clamping function controlled by a selection signal. In the operation of the liquid crystal display device, within a predetermined period of time after the liquid crystal display device is powered on, the selection signal is in the first state to disable the voltage clamping function, and after the predetermined time period, the selection signal is switched to a second state different from the first state. state, whereby the voltage clamp function is enabled.

Description of drawings

1 is a schematic diagram of a known liquid crystal display device;

2 is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention;

3 is a schematic structural view of a second embodiment of a liquid crystal display device of the present invention;

4 is a schematic structural view of a third embodiment of a liquid crystal display device of the present invention;

5 is a schematic structural view of a fourth embodiment of a liquid crystal display device of the present invention;

6 is a schematic structural view of a fifth embodiment of a liquid crystal display device of the present invention;

7 is a schematic structural view of a sixth embodiment of the liquid crystal display device of the present invention;

8 is a schematic structural diagram of a seventh embodiment of a liquid crystal display device of the present invention;

FIG. 9 is a schematic structural diagram of an eighth embodiment of the liquid crystal display device of the present invention.

Among them, reference signs

10, 20, 30, 40, 50, 60, 70, 80, 90 Liquid crystal display device

100, 200 Pixel Array Unit

104, 204 Source Driver

106, 206 Gate Drivers

120, 220, 320, 420, 520, 620, 720, 820, 920 grid pulse modulation unit

125, 225, 325 Diodes

130, 230 The first transistor

135, 235 Second transistor

140, 240 Inverter

250, 450, 550, 650, 750, 850, 950 Selector

451, 551, 851, 951 The third transistor

453, 553, 853, 953 Fourth transistor

PX Pixels

Rx Resistance

Ssel selection signal

Vclamp Clamping Voltage

VFLK clipping control signal

VGH High Potential Gate Signal Reference Voltage

VGHM High Potential Gate Signal Modulation Voltage

VGL Low Potential Gate Signal Reference Voltage

Vref Reference potential

XON reset signal

Detailed ways

The specific embodiments of the liquid crystal display device according to the present invention will be described in detail below with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention.

FIG. 2 is a schematic structural diagram of the first embodiment of the liquid crystal display device of the present invention. As shown in FIG. 2 , the liquid crystal display device 20 includes a pixel array unit 200 having a plurality of pixels PX, a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 220 . The source driver 204 is used to provide a plurality of data signals to the pixel array unit 200 . The gate driver 206 is used to modulate the voltage VGHM and the low-potential gate signal reference voltage VGL according to the high-potential gate signal to provide a plurality of gate signals to the pixel array unit 200, and the pixel array unit 200 is based on the plurality of data signals and the reference voltage VGL. Multiple gate signals drive multiple pixels PX to display images. The gate driver 206 can also perform power-off afterimage attenuation operation on the pixel array unit 200 according to the reset signal XON. As for the operation-related waveform of the reset signal XON, it is a known technology and will not be repeated here.

The gate pulse modulation unit 220 is used for providing a high potential gate signal modulation voltage VGHM. The gate pulse modulation unit 220 includes an inverter 240 , a first transistor 230 , a second transistor 235 , a resistor Rx, a diode 225 , and a selector 250 . The first transistor 230 is a P-type thin film transistor or a P-type field effect transistor, and the second transistor 235 is an N-type thin film transistor or an N-type field effect transistor. The inverter 240 includes an input terminal and an output terminal, wherein the input terminal is used for receiving the clipping control signal VFLK. The first transistor 230 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive the high-potential gate signal reference voltage VGH, the gate terminal is electrically connected to the output terminal of the inverter 240, and the second terminal is used for Output the high potential gate signal modulation voltage VGHM to the gate driver 206 . The capacitor Cg is electrically connected between the second terminal of the first transistor 230 and the reference potential Vref. In one embodiment, the reference potential Vref is the ground potential. The second transistor 235 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the second terminal of the first transistor 230, the gate terminal is electrically connected to the output terminal of the inverter 240, and the second terminal is electrically connected to the second terminal of the first transistor 230. In the resistance Rx. The resistor Rx is electrically connected between the second terminal of the second transistor 235 and the reference potential Vref. The selector 250 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to receive the clamp voltage Vclamp, the second input terminal is electrically connected to the reference potential Vref, and the output terminal is electrically connected to the diode 225 . The diode 225 includes an anode and a cathode, wherein the anode is electrically connected to the output end of the selector 250 , and the cathode is electrically connected to the second end of the first transistor 230 .

The inverter 240, the first transistor 230, the second transistor 235, and the resistor Rx are combined to form a waveform clipping circuit, which is used to provide a high-potential gate signal modulation voltage VGHM, so as to perform waveform clipping operations on multiple gate signals . In addition, the unidirectional transmission characteristic of the diode 225 enables the waveform clipping operation performed by the waveform clipping circuit to have a voltage clamping function. The selector 250 performs a selection operation according to the reset signal XON, thereby electrically connecting its first input terminal or the second input terminal to the positive terminal of the diode 225, so as to select the clamping voltage Vclamp or the reference potential Vref and feed it into the diode 225. positive extreme. Therefore, the reset signal XON is not only used to control the power-off afterimage attenuation operation, but also used to control the selection operation of the selector 250, so that the circuit can be simplified to save cost. When the clamping voltage Vclamp is selected to be fed to the positive terminal of the diode 225 , the diode 225 performs a voltage clamping function on the high potential gate signal modulation voltage VGHM according to the clamping voltage Vclamp. When the reference potential Vref is selected to be fed to the positive terminal of the diode 225, the diode 225 performs a voltage clamping function on the high-potential gate signal modulation voltage VGHM according to the reference potential Vref, but due to the high-potential gate signal modulation voltage VGHM The swing range is between the high potential gate signal reference voltage VGH and the reference potential Vref, so the diode 225 is substantially unable to perform the voltage clamping function according to the reference potential Vref. That is to say, the selector 250 can perform a selection operation according to the reset signal XON to enable/disable the voltage clamping function. The high-potential gate signal reference voltage VGH can quickly charge the capacitor Cg through the first transistor 230 , so that the high-potential gate signal modulation voltage VGHM quickly rises to the high-potential gate signal reference voltage VGH. Alternatively, the reference potential Vref can discharge the capacitor Cg through the second transistor 235 and the resistor Rx to reduce the high potential gate signal modulation voltage VGHM, wherein the resistor Rx is used to control the discharge rate. In the discharge operation of the capacitor Cg, the selector 250 selects the clamping voltage Vclamp and feeds it into the positive terminal of the diode 225 to enable the voltage clamping function, so when the high-potential gate signal modulating voltage VGHM drops to the clamping voltage Vclamp, the diode 225 is forward conduction, so that the high-potential gate signal modulation voltage VGHM is substantially maintained at the clamping voltage Vclamp until subsequent charging and discharging operations are performed.

In the operation of the liquid crystal display device 20, the reset signal XON remains in the first state within a predetermined period of time after power-on, so that the selector 250 selects the reference potential Vref to disable the voltage clamping function, so although the clamping voltage Vclamp quickly rises to the input voltage level, but at this time the clamping voltage Vclamp is not fed into the positive terminal of the diode 225, that is, the clamping voltage Vclamp with a high potential cannot be fed into the gate driver within a predetermined period of time 206, so the gate driver 206 will not generate multiple noise-like gate signals. That is to say, even if the reset signal XON having the first state enables the gate driver 206 to output all gate signals to the pixel array unit 200 within a predetermined period of time, the noise phenomenon of the startup screen does not occur. After a predetermined period of time, the reset signal XON switches to a second state different from the first state, so that the selector 250 selects the clamping voltage Vclamp with a high potential to enable the voltage clamping function.

FIG. 3 is a schematic structural diagram of a second embodiment of the liquid crystal display device of the present invention. As shown in FIG. 3 , the liquid crystal display device 30 includes a pixel array unit 200 , a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 320 . The gate pulse modulation unit 320 is similar to the gate pulse modulation unit 220 shown in FIG. 2 , the main difference is that the diode 225 is replaced with a diode 325 . The diode 325 includes a positive terminal and a negative terminal, wherein the positive terminal is electrically connected to the output terminal of the selector 250 , and the negative terminal is electrically connected to the second terminal of the second transistor 235 . That is to say, the cathode terminal of the diode 325 is electrically connected to the connection node between the second transistor 235 and the resistor Rx. In the operation of the liquid crystal display device 30, when performing the discharge operation of the capacitor Cg, the selector 250 selects the clamping voltage Vclamp with a high potential to enable the voltage clamping function. When the node connecting the second transistor 235 and the resistor Rx When the voltage drops to the clamping voltage Vclamp, the diode 325 is forward-conducting, so that the high-potential gate signal modulation voltage VGHM is substantially maintained at the clamping voltage Vclamp until subsequent charging and discharging operations are performed. Except for the above-mentioned operation of the diode 325 , other operations of the liquid crystal display device 30 are the same as those of the liquid crystal display device 20 , and will not be repeated here.

FIG. 4 is a schematic structural diagram of a third embodiment of the liquid crystal display device of the present invention. As shown in FIG. 4 , the liquid crystal display device 40 includes a pixel array unit 200 , a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 420 . The gate pulse modulation unit 420 is similar to the gate pulse modulation unit 220 shown in FIG. 2 , the main difference is that the selector 250 is replaced by the selector 450 . The selector 450 includes a third transistor 451 and a fourth transistor 453 , wherein the third transistor 451 is an N-type thin film transistor or an N-type field effect transistor, and the fourth transistor 453 is a P-type thin film transistor or a P-type field effect transistor. The third transistor 451 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive the clamp voltage Vclamp, the second terminal is electrically connected to the positive terminal of the diode 225 , and the gate terminal is used to receive the reset signal XON. The fourth transistor 453 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the reference potential Vref, the second terminal is electrically connected to the positive terminal of the diode 225 , and the gate terminal is used to receive the reset signal XON. When the reset signal XON remains in the first state, the fourth transistor 453 is turned on and the third transistor 451 is turned off, so that the reference potential Vref is selected and fed to the positive terminal of the diode 225 to disable the voltage clamping function. When the reset signal XON remains in the second state, the third transistor 451 is turned on and the fourth transistor 453 is turned off, so that the clamping voltage Vclamp with a high potential is selected and fed to the positive terminal of the diode 225 to enable voltage clamping. Function. Except for the above-mentioned operations of the third transistor 451 and the fourth transistor 453 , other operations of the liquid crystal display device 40 are the same as those of the liquid crystal display device 20 , and will not be repeated here.

FIG. 5 is a schematic structural diagram of a fourth embodiment of the liquid crystal display device of the present invention. As shown in FIG. 5 , the liquid crystal display device 50 includes a pixel array unit 200 , a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 520 . The gate pulse modulation unit 520 is similar to the gate pulse modulation unit 320 shown in FIG. 3 , the main difference is that the selector 250 is replaced by the selector 550 . The selector 550 includes a third transistor 551 and a fourth transistor 553 , wherein the third transistor 551 is an N-type thin film transistor or an N-type field effect transistor, and the fourth transistor 553 is a P-type thin film transistor or a P-type field effect transistor. The third transistor 551 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive the clamp voltage Vclamp, the second terminal is electrically connected to the positive terminal of the diode 325 , and the gate terminal is used to receive the reset signal XON. The fourth transistor 553 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the reference potential Vref, the second terminal is electrically connected to the positive terminal of the diode 325 , and the gate terminal is used to receive the reset signal XON. When the reset signal XON remains in the first state, the fourth transistor 553 is turned on and the third transistor 551 is turned off, so that the reference potential Vref is selected and fed to the positive terminal of the diode 325 to disable the voltage clamping function. When the reset signal XON remains in the second state, the third transistor 551 is turned on and the fourth transistor 553 is turned off, so that the clamping voltage Vclamp with a high potential is selected and fed to the positive terminal of the diode 325 to enable voltage clamping. Function. Except for the above-mentioned operations of the third transistor 551 and the fourth transistor 553 , other operations of the liquid crystal display device 50 are the same as those of the liquid crystal display device 30 , and will not be repeated here.

FIG. 6 is a schematic structural diagram of a fifth embodiment of the liquid crystal display device of the present invention. As shown in FIG. 6 , the liquid crystal display device 60 includes a pixel array unit 200 , a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 620 . The gate pulse modulation unit 620 is similar to the gate pulse modulation unit 220 shown in FIG. 2 , the main difference is that the selector 250 is replaced by the selector 650 . The selector 650 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to receive the clamp voltage Vclamp, the second input terminal is electrically connected to the reference potential Vref, and the output terminal is electrically connected to the positive electrode of the diode 225. extreme. The selector 650 performs a selection operation according to the selection signal Ssel different from the reset signal XON. When the selection signal Ssel remains in the first state, the selector 650 is electrically connected to its second input terminal and output terminal to select the reference potential Vref to feed into The anode terminal of the diode 225 , when the select signal Ssel remains in the second state, the selector 650 is electrically connected to its first input terminal and output terminal to select the clamp voltage Vclamp and feed it to the anode terminal of the diode 225 . Therefore, in the operation of the liquid crystal display device 60, the predetermined period of the disabling voltage clamping function does not need to be equal to the period during which the reset signal XON maintains the first state when the power is turned on, that is, the disabling voltage clamping function can be adjusted more flexibly. for a predetermined period of time to improve operational performance. Except for the operation of the selection signal Ssel mentioned above, other operations of the liquid crystal display device 60 are the same as those of the liquid crystal display device 20 , and will not be repeated here.

FIG. 7 is a schematic structural diagram of a sixth embodiment of the liquid crystal display device of the present invention. As shown in FIG. 7 , the liquid crystal display device 70 includes a pixel array unit 200 , a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 720 . The gate pulse modulation unit 720 is similar to the gate pulse modulation unit 320 shown in FIG. 3 , the main difference is that the selector 250 is replaced by the selector 750 . The selector 750 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to receive the clamp voltage Vclamp, the second input terminal is electrically connected to the reference potential Vref, and the output terminal is electrically connected to the positive electrode of the diode 325. extreme. The selector 750 performs a selection operation according to the selection signal Ssel different from the reset signal XON, thereby electrically connecting its first input end or second input end to the positive end of the diode 325, thereby selecting the clamping voltage Vclamp or the reference potential Vref is fed into the positive terminal of diode 325 . Therefore, in the operation of the liquid crystal display device 70, the predetermined period of the disabling voltage clamping function does not need to be equal to the period during which the reset signal XON maintains the first state when the power is turned on, that is, the disabling voltage clamping function can be adjusted more flexibly. for a predetermined period of time to improve operational performance. Except for the operation of the selection signal Ssel mentioned above, the rest of the operation of the liquid crystal display device 70 is the same as that of the liquid crystal display device 30 , and will not be repeated here.

FIG. 8 is a schematic structural diagram of a seventh embodiment of the liquid crystal display device of the present invention. As shown in FIG. 8 , the liquid crystal display device 80 includes a pixel array unit 200 , a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 820 . The gate pulse modulation unit 820 is similar to the gate pulse modulation unit 620 shown in FIG. 6 , the main difference is that the selector 650 is replaced by a selector 850 . The selector 850 includes a third transistor 851 and a fourth transistor 853 , wherein the third transistor 851 is an N-type thin film transistor or an N-type field effect transistor, and the fourth transistor 853 is a P-type thin film transistor or a P-type field effect transistor. The third transistor 851 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive the clamp voltage Vclamp, the second terminal is electrically connected to the positive terminal of the diode 225 , and the gate terminal is used to receive the selection signal Ssel. The fourth transistor 853 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the reference potential Vref, the second terminal is electrically connected to the positive terminal of the diode 225 , and the gate terminal is used to receive the selection signal Ssel. When the selection signal Ssel turns on the fourth transistor 853 and turns off the third transistor 851 , the selector 850 selects the reference potential Vref to feed into the positive terminal of the diode 225 to disable the voltage clamping function. When the selection signal Ssel turns on the third transistor 851 and turns off the fourth transistor 853 , the selector 850 selects the clamping voltage Vclamp having a high potential and feeds it into the positive terminal of the diode 225 to enable the voltage clamping function. Except for the above-mentioned operations of the third transistor 851 and the fourth transistor 853 , other operations of the liquid crystal display device 80 are the same as those of the liquid crystal display device 60 , and will not be repeated here.

FIG. 9 is a schematic structural diagram of an eighth embodiment of the liquid crystal display device of the present invention. As shown in FIG. 9 , the liquid crystal display device 90 includes a pixel array unit 200 , a source driver 204 , a gate driver 206 , a capacitor Cg, and a gate pulse modulation unit 920 . The gate pulse modulation unit 920 is similar to the gate pulse modulation unit 720 shown in FIG. 7 , the main difference is that the selector 750 is replaced by the selector 950 . The selector 950 includes a third transistor 951 and a fourth transistor 953 , wherein the third transistor 951 is an N-type thin film transistor or an N-type field effect transistor, and the fourth transistor 953 is a P-type thin film transistor or a P-type field effect transistor. The third transistor 951 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive the clamp voltage Vclamp, the second terminal is electrically connected to the positive terminal of the diode 325 , and the gate terminal is used to receive the selection signal Ssel. The fourth transistor 953 includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the reference potential Vref, the second terminal is electrically connected to the positive terminal of the diode 325 , and the gate terminal is used to receive the selection signal Ssel. When the selection signal Ssel turns on the fourth transistor 953 and turns off the third transistor 951 , the selector 950 selects the reference potential Vref to feed into the positive terminal of the diode 325 to disable the voltage clamping function. When the selection signal Ssel turns on the third transistor 951 and turns off the fourth transistor 953 , the selector 950 selects the clamping voltage Vclamp having a high potential and feeds it into the positive terminal of the diode 325 to enable the voltage clamping function. Except for the above-mentioned operations of the third transistor 951 and the fourth transistor 953 , other operations of the liquid crystal display device 90 are the same as those of the liquid crystal display device 70 , and will not be repeated here.

To sum up, in the operation of the liquid crystal display device of the present invention, within a predetermined period of time after starting up, the operation of the input clamping voltage can be stopped according to the reset signal or the selection signal, thereby disabling the voltage clamping function, so although The clamping voltage rises quickly to the input voltage level, but the clamping voltage with the input voltage level cannot be fed into the gate driver for a predetermined period of time, and the gate driver will not generate multiple noise-like gate signals . Therefore, even if the reset signal used to attenuate the power-off afterimage enables the gate driver to output all the gate signals to the pixel array unit at the same time within a predetermined period of time, the noise phenomenon of the power-on screen will not occur.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (22)

1. A liquid crystal display device, characterized in that, comprising: A pixel array unit for performing an image display operation; A source driver, electrically connected to the pixel array unit, used to provide a plurality of data signals required for the pixel array unit to perform the image display operation; A gate driver, electrically connected to the pixel array unit, is used to adjust the voltage according to a high potential gate signal to provide a plurality of gate signals required for the pixel array unit to perform the image display operation, and is used to adjust the voltage according to a multiple setting the signal to perform a power-off afterimage attenuation operation on the pixel array unit; and A gate pulse modulation unit, electrically connected to the gate driver, used to provide the high potential gate signal modulation voltage, the gate pulse modulation unit has a voltage clamping function controlled by the reset signal ; Wherein within a predetermined period after the liquid crystal display device is turned on, the reset signal is in a first state to disable the voltage clamping function, and after the predetermined period, the reset signal is switched to a state different from the first state A second state for enabling the voltage clamping function. 2. The liquid crystal display device according to claim 1, wherein the gate pulse modulation unit comprises: An inverter includes an input terminal and an output terminal, wherein the input terminal is used to receive a chamfer control signal; A first transistor, including a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive a high-potential gate signal reference voltage, and the gate terminal is electrically connected to the output terminal of the inverter , the second end is used to output the high potential gate signal modulation voltage; A second transistor, including a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the second terminal of the first transistor, and the gate terminal is electrically connected to the output terminal of the inverter ; a resistor electrically connected between the second terminal of the second transistor and a reference potential; a diode comprising a positive terminal and a negative terminal, wherein the negative terminal is electrically connected to the second terminal of the second transistor or the second terminal of the first transistor; and A selector includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to receive a clamping voltage, the second input terminal is electrically connected to the reference potential, and the output terminal electrically connected to the positive terminal of the diode, the selector selects the clamping voltage or the reference potential from the output terminal to the positive terminal of the diode according to the reset signal; Wherein the inverter, the first transistor, the second transistor and the resistor are used to provide the high-potential gate signal modulation voltage according to the chamfering control signal and the high-potential gate signal reference voltage, so as to These gate signals perform a waveform clipping operation, and the unidirectional transfer characteristic of the diode enables the waveform clipping operation to have the voltage clamping function, and the selector is used to enable/disable the voltage clamping according to the reset signal Function. 3. The liquid crystal display device according to claim 2, wherein within the predetermined period of time after the liquid crystal display device is turned on, the first state of the reset signal is used to make the selector select the reference potential to Disable the voltage clamp function. 4. The liquid crystal display device according to claim 2, wherein after the predetermined period of time, the second state of the reset signal is used to make the selector select the clamping voltage to enable the voltage clamping function . 5. The liquid crystal display device according to claim 2, characterized in that: The first transistor is a P-type thin film transistor or a P-type field effect transistor; and The second transistor is an N-type thin film transistor or an N-type field effect transistor. 6. The liquid crystal display device according to claim 2, wherein the selector comprises: A third transistor includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive the clamping voltage, the second terminal is electrically connected to the positive terminal of the diode, and the gate terminal is used for to receive the reset signal; and A fourth transistor, including a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the reference potential, the second terminal is electrically connected to the positive terminal of the diode, and the gate terminal is used for Receive the reset signal. 7. The liquid crystal display device according to claim 6, characterized in that: The third transistor is an N-type thin film transistor or an N-type field effect transistor; and The fourth transistor is a P-type thin film transistor or a P-type field effect transistor. 8. The liquid crystal display device according to claim 6, wherein the first end of the fourth transistor is electrically connected to a ground potential. 9. The liquid crystal display device according to claim 2, wherein the resistor is electrically connected between the second terminal of the second transistor and a ground potential. 10. The liquid crystal display device according to claim 2, further comprising: A capacitor is electrically connected between the second terminal of the first transistor and the reference potential. 11. The liquid crystal display device according to claim 10, wherein the capacitor is electrically connected between the second terminal of the first transistor and a ground potential. 12. A liquid crystal display device, characterized in that it comprises: a source driver, used to provide multiple data signals; a gate driver, used for modulating voltage according to a high potential gate signal to provide multiple gate signals; a pixel array unit electrically connected to the source driver and the gate driver for displaying images according to the data signals and the gate signals; and a gate pulse modulation unit electrically connected to the gate driver for providing the high-potential gate signal modulation voltage, the gate pulse modulation unit has a voltage clamping function controlled by a selection signal; Wherein within a predetermined period after the liquid crystal display device is turned on, the selection signal is in a first state to disable the voltage clamping function, and after the predetermined period, the selection signal is switched to a state different from the first state In the second state, the voltage clamping function is enabled. 13. The liquid crystal display device according to claim 12, wherein the gate pulse modulation unit comprises: An inverter includes an input terminal and an output terminal, wherein the input terminal is used to receive a chamfer control signal; A first transistor, including a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive a high-potential gate signal reference voltage, and the gate terminal is electrically connected to the output terminal of the inverter , the second end is used to output the high potential gate signal modulation voltage; A second transistor, including a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the second terminal of the first transistor, and the gate terminal is electrically connected to the output terminal of the inverter ; a resistor electrically connected between the second terminal of the second transistor and a reference potential; a diode comprising a positive terminal and a negative terminal, wherein the negative terminal is electrically connected to the second terminal of the second transistor or the second terminal of the first transistor; and A selector includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to receive a clamping voltage, the second input terminal is electrically connected to the reference potential, and the output terminal electrically connected to the positive terminal of the diode, the selector selects the clamping voltage or the reference potential from the output terminal to the positive terminal of the diode according to the selection signal; Wherein the inverter, the first transistor, the second transistor and the resistor are used to provide the high-potential gate signal modulation voltage according to the chamfering control signal and the high-potential gate signal reference voltage, so as to These gate signals perform a waveform clipping operation, and the unidirectional transfer characteristic of the diode enables the waveform clipping operation to have the voltage clamping function, and the selector is used to enable/disable the voltage clamping function according to the selection signal . 14. The liquid crystal display device according to claim 13, wherein within the predetermined period of time after the liquid crystal display device is turned on, the first state of the selection signal is used to make the selector select the reference potential to divide capable of the voltage clamp function. 15. The liquid crystal display device according to claim 13, wherein after the predetermined period, the second state of the selection signal is used to make the selector select the clamping voltage to enable the voltage clamping function. 16. The liquid crystal display device according to claim 13, characterized in that: The first transistor is a P-type thin film transistor or a P-type field effect transistor; and The second transistor is an N-type thin film transistor or an N-type field effect transistor. 17. The liquid crystal display device according to claim 13, wherein the selector comprises: A third transistor includes a first terminal, a second terminal and a gate terminal, wherein the first terminal is used to receive the clamping voltage, the second terminal is electrically connected to the positive terminal of the diode, and the gate terminal is used for to receive the selection signal; and A fourth transistor, including a first terminal, a second terminal and a gate terminal, wherein the first terminal is electrically connected to the reference potential, the second terminal is electrically connected to the positive terminal of the diode, and the gate terminal is used for Receive the selection signal. 18. The liquid crystal display device according to claim 17, characterized in that: The third transistor is an N-type thin film transistor or an N-type field effect transistor; and The fourth transistor is a P-type thin film transistor or a P-type field effect transistor. 19. The liquid crystal display device according to claim 17, wherein the first end of the fourth transistor is electrically connected to a ground potential. 20. The liquid crystal display device according to claim 13, wherein the resistor is electrically connected between the second terminal of the second transistor and a ground potential. 21. The liquid crystal display device according to claim 13, further comprising: A capacitor is electrically connected between the second terminal of the first transistor and the reference potential. 22. The liquid crystal display device according to claim 21, wherein the capacitor is electrically connected between the second terminal of the first transistor and a ground potential.

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