CN101833523B - Data access method - Google Patents
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- CN101833523B CN101833523B CN200910127102.9A CN200910127102A CN101833523B CN 101833523 B CN101833523 B CN 101833523B CN 200910127102 A CN200910127102 A CN 200910127102A CN 101833523 B CN101833523 B CN 101833523B
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Abstract
The invention discloses a kind of data access method, the mode that can directly transmit or directly read is adopted by the data access between the controller of main side, it can effectively solve when computer interface equipment room is for mutual data access, its data first must be temporarily stored in storer and produce the problem of losing time, and efficiency when effectively improving data access.
Description
Technical field
The present invention relates to a kind of data access method, particularly direct data access method between the controller of a kind of main side.
Background technology
Up to now, the data access of computer interface equipment room is mostly linked up by main side bridge (HostBridge) and main side controller (Hostcontroller) against CPU (central processing unit) (CPU) or microprocessor (MCU).But, the mode linked up between CPU (central processing unit) and main side controller, except can make the load of CPU (central processing unit) own higher except, the situation that the data access of computer interface equipment room also can be made to have efficiency low occurs.
Please refer to the conventional central processing unit shown in Fig. 1, circuit diagram between main side bridge and interfacing equipment.In general, main side controller 110,120 has direct memory access (DMA) (directlymemoryaccess, DMA) function, namely when for by the data-moving of interfacing equipment A to interfacing equipment B time, main side controller 110 can by first the data of interfacing equipment A being moved to regional systems storer (localsystemmemory) 130 by Memory Controller 125, then by main side controller 120 by temporary interfacing equipment A data-moving in memory 130 to interfacing equipment B.
Under this DMA pattern, CPU (central processing unit) 140 only needs initialization main side controller 110,120 and prepares a few thing instruction to main side controller 110,120, and main side controller 110,120 can start to carry out the work of the data-moving of interfacing equipment A to interfacing equipment B.And after main side controller 110,120 completes its work be delivered, main side controller 110,120 can inform CPU (central processing unit) 140, to wait for lower portion work.Therefore, CPU (central processing unit) 140 can in dma mode, by main side controller 110,120 direct access regional systems storer 130, to reduce the load that it uses.
But, the data access flow process of this DMA pattern truly has its shortcoming, for Fig. 1, when must by the data-moving of interfacing equipment A to interfacing equipment B, CPU (central processing unit) 140 need arrange main side controller 110 first to move the data of interfacing equipment A to the space in storer 130 by Memory Controller 125 by main side bridge 150, and CPU (central processing unit) 140 arranges main side controller 120 the interfacing equipment A data be temporary in storer 130 to be moved to interfacing equipment B by Memory Controller 125 by main side bridge 150 again.
And above-mentioned such flow chart of data processing can be wasted the much time and moved out by storer to storer and by data by data-moving, jointly, if under storer is in a very busy state, this comprises by CPU (central processing unit), main side bridge, main side controller, storer and the system that is made up of interfacing equipment, it will become slowly in the running of data access, and namely the efficiency of its data access is low.
In view of this, the present invention proposes a kind of data access method, and can effectively solve when computer interface equipment room is for mutual data access, its data first must be temporarily stored in storer and produce the problem of losing time, effectively to improve efficiency during data access.
Summary of the invention
Fundamental purpose of the present invention is to solve when computer interface equipment room is for mutual data access, and its data first must be temporarily stored in the puzzlement of storer.In order to reach object of the present invention, the present invention proposes a kind of data access method, it is characterized in that: by the first main side controller the data of keeping in directly transfer in the second main side controller.
In present pre-ferred embodiments, the method comprises the operator schemes such as original state, unprogrammed state and transmission state.
Original state comprises the arithmetic register in the controller of CPU (central processing unit) sequencing first main side, to guarantee the first main side controller normal operation.
Unprogrammed state can comprise when data need transfer to the second main side controller by the first main side controller, CPU (central processing unit) programmable arithmetic register, with the state etc. of the start address of the kind of the length of setting data, data, data, the first main side controller.
Transmission state then also comprises single main write situation, single main reading situation, two main write situations and two main reading situations.
Single main write situation mainly comprises when data need transfer to the second main side controller by the first main side controller, first main side controller sends a dominant period signal to read and to confirm the transmission state of the second main side controller, to determine whether active transmission data.
Single main reading situation mainly comprises when data need transfer to the second main side controller by the first main side controller, start the direct memory access (DMA) function of the second main side controller, and the second main side controller sends the transmission state that dominant period signal removes reading first main side controller, with determine to make no initiatively access the first main side controller the data of keeping in.
Two main write situations are then when data need transfer to the second main side controller by the first main side controller, start the function of a direct memory access (DMA) of the first main side controller and the second main side controller simultaneously, a dominant period signal is sent by the second main side controller, to notify the transmission state of the first main side controller second main side controller, to determine whether the first main side controller can start to transmit data.
Two main reading situations then comprise when data need transfer to the second main side controller by the first main side controller, start the function of a direct memory access (DMA) of the first main side controller and the second main side controller simultaneously, a dominant period signal is sent to notify the transmission state of the second main side controller first main side controller, to determine whether the second main side controller can start to read data by the first main side controller.
For the ease of understanding feature of the present invention, object and function further, below in conjunction with accompanying drawing, the present invention is described in detail.
Accompanying drawing explanation
Fig. 1 is known CPU (central processing unit), circuit diagram between main side bridge and interfacing equipment;
Fig. 2 A is the schematic diagram of the data access method of present pre-ferred embodiments;
Fig. 2 B is that the data access method of present pre-ferred embodiments is in the schematic diagram of original state operator scheme;
Fig. 2 C is that the data access method of present pre-ferred embodiments is in the schematic diagram of unprogrammed state operator scheme;
Fig. 2 D is that the data access method of present pre-ferred embodiments is in the schematic diagram of the operator scheme of single write transmission state;
Fig. 2 E is that the data access method of present pre-ferred embodiments is in the schematic diagram of the operator scheme of single main reading transmission state.
Description of reference numerals: 110,120 main side controllers; 125 Memory Controllers; 130 regional systems storeies; 140 CPU (central processing unit); 150 main side bridges; 213,223 arithmetic registers; 215,225 transmission states; 217,227 transmission data buffers.
Embodiment
Please refer to the schematic diagram of the data access method of the present pre-ferred embodiments shown in Fig. 2.In fig. 2, the present invention mainly changes the data access method on existing motherboard between main side controller 110 and main side controller 120, and the data changed between employing main side controller 110 and main side controller 120 can direct access.In other words, namely make external bus 230,240 data each other respective coupled between main side controller 110 and main side controller 120 can direct access.
The data access method of the present invention between main side controller 110 and main side controller 120 can be divided into several operator scheme, as operator schemes such as original state, unprogrammed state and transmission states.
Please refer to the data access method of the present pre-ferred embodiments shown in Fig. 2 B in the schematic diagram of original state operator scheme.During original state, the arithmetic register 213 of CPU (central processing unit) 140 sequencing main side controller 110, to guarantee that main side controller 110 can normal operation.For example, CPU (central processing unit) 140 sequencing arithmetic register 213, with the partial function making arithmetic register 213 start main side buffer, as started, postponing, restart, stopping etc.Suppose that CPU (central processing unit) 140 starts direct memory access (DMA) function (DMA) for sequencing arithmetic register 213, CPU (central processing unit) 140 sends the dominant period signal of direct memory access (DMA) function to arithmetic register 213.
And when there being data need transfer to this main side controller 120 by main side controller 110, namely enter the operator scheme of unprogrammed state.Please refer to the data access method of the present pre-ferred embodiments shown in Fig. 2 C in the schematic diagram of unprogrammed state operator scheme.The arithmetic register 213 of CPU (central processing unit) 140 sequencing main side controller 110, to set the state etc. of the length of tendency to develop transmission of data, kind, start address, main side controller, namely sets up the transmission state 215 of main side controller 110.That is, main side controller 110 can set up the transmission state 215 of corresponding main side controller 120.
In present pre-ferred embodiments, the status transmission of data access method comprises single main write situation, single main reading situation, two main write situations and two main reading situations.Please refer to the data access method of the present pre-ferred embodiments shown in Fig. 2 D in the schematic diagram of the operator scheme of single write transmission state.When data need transfer to main side controller 120 by main side controller 110, main side controller 110 sends dominant period signal, to read and to confirm the transmission state 225 of main side controller 120, to determine whether active transmission data.Certainly, the transmission state 225 of main side controller 120 comprises the capacity of the transmission data buffer 227 of main side controller 120, transmits the start address etc. of data buffer 227 capacity status, transmission data buffer 227.
If the transmission state of main side controller 120 belongs to the state preparing to transmit, then the data of external bus 230 are prepared by transmission data buffer 217 itself the transmission data buffer 227 transferring to main side controller 120 by main side controller 110.And after main side controller 120 receives data, data are moved to the external bus 240 corresponding to main side controller 120 by transmitting data buffer 227 by main side controller 120, to complete data transmission.
In addition, after data are transmitted, main side controller 110 and main side controller 120 upgrade the transmission state of its inside automatically, and according to required, main side controller 110 also can remove according to the state of its arithmetic register 213 content the transmission state upgrading main side controller 120.
If the transmission state 225 encountering main side controller 120 belongs to the state of transmission buffer 227 off-capacity, main side controller 110 can select the transmission data buffer 227 data being transferred to main side controller 120 with cutting mode gradation.And main side controller 110 can when external bus 230 gets out lower part tendency to develop transmission of data, continuous transmission data are to main side controller 120.
Otherwise if the transmission state 225 of main side controller 120 belongs to the state that not yet preparation can be transmitted, then main side controller 110 again reads after a while and confirms the transmission state 225 of this main side controller 120.
Please continue to refer to the data access method of the present pre-ferred embodiments shown in Fig. 2 E in the schematic diagram of the operator scheme of single main reading transmission state.The mode of data transmission, except initiatively sending data to except main side controller 120 at single main write transmission state with main side controller 110, also has the operator scheme of the single main reading transmission state initiatively reading main side controller 110 data with main side controller 120.
When data still need transfer to main side controller 120 by main side controller 110, CPU (central processing unit) 140 starts main side controller 120 direct memory access (DMA) function, and main side controller 120 sends the transmission state 215 that dominant period signal removes to read main side controller 110, with determine to make no initiatively access main side controller 110 the data of keeping in.
If the transmission state 215 of main side controller 110 belongs to and prepares to transmit and the capacity of the transmission data buffer 227 of main side controller 120 is enough states, then main side controller 120 reads the data being temporary in main side controller 110.Similarly, if the transmission data buffer 227 of main side controller 120 is for belonging to the state of off-capacity, main side controller 120 still can be selected to read data with cutting mode gradation by main side controller 110.Further, main side controller 120 can, when transmitting data buffer 227 and having space, continue to read data by main side controller 110.
Otherwise if the transmission state of main side controller 110 belongs to the state that not yet preparation can transmit, then the transmission state 215 of main side controller 110 reaffirmed after a while by main side controller 120.
And when main side controller 120 reads main side controller 110 temporal data and after having read, main side controller 110 and main side controller 120 upgrade the transmission state 215,225 of its inside all automatically, and according to required, main side controller 120 also can remove according to the state of its arithmetic register 223 content the transmission state 215 upgrading main side controller 110.
And its maximum difference of operator scheme of the operator scheme of two main write transmission states and aforementioned transmission state is, when data need transfer to main side controller 120 by main side controller 110, start the function of the direct memory access (DMA) of main side controller 110 and main side controller 120 simultaneously, and send dominant period signal to notify the transmission state 225 of main side controller 110 main side controller 120, to determine whether main side controller 110 starts active transmission data to main side controller 120 by main side controller 120.
The operator scheme of two main reading transmission states, then by chance the operator scheme of write transmission state main with two is contrary, when data need transfer to main side controller 120 by main side controller 110, under starting the direct memory access (DMA) function situation of main side controller 110 and main side controller 120 at the same time, change and send dominant period signal to notify the transmission state of main side controller 120 main side controller 110, to determine whether main side controller 120 starts initiatively to read the data of main side controller 110 by main side controller 110.
According to the concept of data access method of the present invention, i.e. main side controller 110, data contact between 220 adopts directly transmission, therefore, extend the operator scheme of aforementioned transmission state, the operator scheme having mixing direct read/write transmission state is also proposed, namely when data need to come and go between main side controller 110 and main side controller 120, start the direct memory access (DMA) function of main side controller 110 and main side controller 120 simultaneously, and initiatively data are transferred to the destination of data by the source place of data, or initiatively read data by destination to the source place of data of data.
Comprehensively above-mentioned, the present invention proposes a kind of data access method, the mode that can directly transmit or directly read is adopted by the data access between the controller of main side, it can effectively solve when computer interface equipment room is for mutual data access, its data first must be temporarily stored in storer and produce the problem of losing time, and efficiency when effectively improving data access.
The foregoing is only preferred embodiment of the present invention, can not limit the scope of the invention with this.Therefore, all equalization changes of doing according to the claims in the present invention and modifying, will not lose main idea place of the present invention, also do not depart from the spirit and scope of the present invention, all should be considered as further enforcement of the present invention.
Claims (9)
1. a data access method, is characterized in that:
By in the first main side controller the data of keeping in directly transfer in the second main side controller;
Wherein also comprise the operator scheme of an original state, a unprogrammed state and a transmission state; And
Wherein at this unprogrammed state, when these data need transfer to this second main side controller by this first main side controller, the arithmetic register of this first main side controller of CPU (central processing unit) programmable, to set length, the kind of these data, the start address of these data, the state of this first main side controller of these data;
Wherein this first main side controller goes to set to should the transmission state of this first main side controller of the second main side controller according to the setting of this arithmetic register;
Wherein this transmission state also comprises single main write situation, single main reading situation, two main write situations and two main reading situations.
2. data access method as claimed in claim 1, wherein this original state comprises:
An arithmetic register in one CPU (central processing unit) sequencing first main side controller, to guarantee this first main side controller normal operation.
3. data access method as claimed in claim 2, wherein this CPU (central processing unit) can make this arithmetic register come into operation and postpone, restarts, stops the partial function of this first main side controller.
4. data access method as claimed in claim 1, wherein when this CPU (central processing unit) is for sequencing one direct memory access (DMA) function, this CPU (central processing unit) then sends a dominant period signal of this direct memory access (DMA) function to this arithmetic register.
5. data access method as claimed in claim 1, wherein this single main write situation comprises:
When these data need transfer to this second main side controller by this first main side controller, this first main side controller sends dominant period signal, to read and to confirm the transmission state of this second main side controller, to determine whether these data of active transmission.
6. data access method as claimed in claim 1, wherein this single main reading situation comprises:
When these data need transfer to this second main side controller by this first main side controller, start the direct memory access (DMA) function of this second main side controller, and this second main side controller sends the transmission state that a dominant period signal removes to read this first main side controller, with determine to make no initiatively access this first main side controller this data of keeping in.
7. data access method as claimed in claim 1, wherein this two main write situation comprises:
When these data need transfer to this second main side controller by this first main side controller, start the function of the direct memory access (DMA) of this first main side controller and this second main side controller simultaneously, dominant period signal is sent by this second main side controller, to notify the transmission state of this this second main side controller of the first main side controller, to determine whether this first main side controller can start to transmit this data.
8. data access method as claimed in claim 1, wherein this two main reading situation comprises:
When these data need transfer to this second main side controller by this first main side controller, start the function of a direct memory access (DMA) of this first main side controller and this second main side controller simultaneously, a dominant period signal is sent to notify the transmission state of this this first main side controller of the second main side controller, to determine whether this second main side controller can start to read this data by this first main side controller.
9. data access method as claimed in claim 1, also comprise a mixing direct read/write situation, this mixing direct read/write situation is:
When these data need come and go between this first main side controller and this second main side controller, start the function of the direct memory access (DMA) of this first main side controller and this second main side controller simultaneously, and in initiatively these data being transmitted the destination of these data by the source place of these data and initiatively being read between these data by destination to the source place of these data of these data and select one.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 200410091600 CN1779666A (en) | 2004-11-19 | 2004-11-19 | Data access method |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200410091600 Division CN1779666A (en) | 2004-11-19 | 2004-11-19 | Data access method |
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| Publication Number | Publication Date |
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| CN101833523A CN101833523A (en) | 2010-09-15 |
| CN101833523B true CN101833523B (en) | 2016-01-20 |
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| CN 200410091600 Pending CN1779666A (en) | 2004-11-19 | 2004-11-19 | Data access method |
| CN200910127102.9A Active CN101833523B (en) | 2004-11-19 | 2004-11-19 | Data access method |
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| CN 200410091600 Pending CN1779666A (en) | 2004-11-19 | 2004-11-19 | Data access method |
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| CN104598405B (en) * | 2015-02-03 | 2018-05-11 | 杭州士兰控股有限公司 | Extended chip and expansible chip system and control method |
| CN104598404B (en) * | 2015-02-03 | 2018-09-04 | 杭州士兰控股有限公司 | Computing device extended method and device and expansible computing system |
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| CN1150674A (en) * | 1994-12-02 | 1997-05-28 | 索尼公司 | Method of producing image data, image data processing apparatus, and recording medium |
| CN1218227A (en) * | 1997-11-06 | 1999-06-02 | 株式会社日立制作所 | Data processing system and microcomputer |
| CN2352982Y (en) * | 1998-06-22 | 1999-12-08 | 北京恒业世纪电气技术有限公司 | Kernel anti-jamming circuit for direct digital control device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7114019B2 (en) * | 2000-09-08 | 2006-09-26 | Standard Microsystems Corporation | System and method for data transmission |
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- 2004-11-19 CN CN 200410091600 patent/CN1779666A/en active Pending
- 2004-11-19 CN CN200910127102.9A patent/CN101833523B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1150674A (en) * | 1994-12-02 | 1997-05-28 | 索尼公司 | Method of producing image data, image data processing apparatus, and recording medium |
| CN1218227A (en) * | 1997-11-06 | 1999-06-02 | 株式会社日立制作所 | Data processing system and microcomputer |
| CN2352982Y (en) * | 1998-06-22 | 1999-12-08 | 北京恒业世纪电气技术有限公司 | Kernel anti-jamming circuit for direct digital control device |
Non-Patent Citations (1)
| Title |
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| "0.18μm CMOS 工艺784Mb/s 的数据发送器设计";朱江等;《系统工程与电子技术》;20010331;第102-104页 * |
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| Publication number | Publication date |
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| CN101833523A (en) | 2010-09-15 |
| CN1779666A (en) | 2006-05-31 |
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