CN101826526A

CN101826526A - Semiconductor memory unit, driving method thereof and semiconductor memory

Info

Publication number: CN101826526A
Application number: CN200910047222A
Authority: CN
Inventors: 季明华
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2009-03-06
Filing date: 2009-03-06
Publication date: 2010-09-08
Anticipated expiration: 2029-03-06
Also published as: CN101826526B

Abstract

The invention relates to a semiconductor memory unit, a driving method thereof and a semiconductor memory, wherein the semiconductor memory unit comprises a first diffusion region, a second diffusion region, a grid dielectric layer, a grid electrode, a first electric charge storage region and/or a second electric charge storage region, wherein the first diffusion region and the second diffusion region are positioned in a semiconductor substrate and separated from each other, and the conduction types of the first diffusion region and the second diffusion region are the same; the grid dielectric layer is positioned on the semiconductor substrate above a channel region; the grid electrode is positioned on the grid dielectric layer; and the first electric charge storage region and/or the second electric charge storage region are/is respectively positioned in the grid dielectric layer and close to the part between the channel region and the first diffusion region and in the grid dielectric layer and close to the part between the channel region and the second diffusion region, and electric charges stored in the first electric charge storage region and/or the second electric charge storage region are injected through electric field force. In the invention, the first electric charge storage region and/or the second electric charge storage region are/is formed in grid dielectric layer through the electric field force to form the memory unit, and the memory unit is compatible with a traditional logic circuit forming process, thereby improving the performance of an integrated circuit and reducing the power consumption.

Description

Semiconductor memory cell, the method that drives it and semiconductor memory

Technical field

The present invention relates to technical field of semiconductors, particularly the method and the semiconductor memory of semiconductor memory cell, driving semiconductor memory cell.

Background technology

Occur scaledly along with CMOS continues the development of highly integrated and high-performance, very lagre scale integrated circuit (VLSIC) (VLSI) occurred.As everyone knows, existing C MOS technology is scaled in 65nm node and the following restriction that faces the balance between speed and the power.Fortunately, improve the stress engineering of mobility and new grid stack material (high k and metal gate) and can below the 32nm node, extend CMOS is scaled, and technology becomes more complicated.Simultaneously, scaled also the making on memory cell electric capacity, selection transistor and the charge storage layer of DRAM and flash memory continues to dwindle.Unfortunately, CMOS logical circuit and memory scaled makes that being integrated in the difficulty that forms system level chip (SoC) together strengthens, and this impels CMOS logical circuit and memory to integrate.Interesting is how many this development trends has reduced the purpose of VLSI as system-on-a-chip.

Existing mos transistor structure comprise fleet plough groove isolation structure, as nitriding and oxidizing layer, the nickle silicide polysilicon gate of gate dielectric layer pile up, multilayer (as ONO) clearance wall, more shallow source/leakage (S/D) extension area, nickle silicide S/D tie deeply.The transistor operating voltage of core logic circuit is usually at 1～1.3V, raceway groove short (be about 40～60nm), gate dielectric layer thin (equivalent electrical thickness EOT is about 20～

), S/D extension area junction depth more shallow (200～

).The transistor of I/O circuit (being used for and chip external circuitry interface) is worked under different external voltage Vcc (for example 1.8V, 2.5V or 3.3V), raceway groove long (about 100～300nm), gate dielectric layer thicker (equivalent electrical thickness EOT, about 40～

), S/D extension area junction depth dark (about 300～

).Core logic circuit can reduce operand power than low operating voltage.Present 65/45nmCMOS makes node and all adopts strained silicon technology to strengthen electronics and the mobility of hole in raceway groove.In the future 32nm and lower cmos circuit may further comprise new strain Si technology and extra feature, such as new high k material as gate dielectric layer, metal gate pile up, SOI substrate or non plane channel transistor (FinFET) or the like.

Traditionally, flash memory and CMOS logical circuit integrated adopt the logic-based cmos circuit or based on the method for flash memory, however these methods and unsuccessful.In the whole CMOS logic process integrated based on SoC, logic polysilicon/grid pile up, gate oxide and clearance wall be forced to flash memory shared, the result, the flash cell area is excessive usually, operating voltage is higher, and the array design complexity.Conversely, owing to need high voltage technology and circuit to cause in low-density (such as＜about 0.5Mb) application, being restricted.In based on the SoC integrated circuit of flash memory, also have problems, the high density flash memory of the dual poly floating boom ETox of this technology, charge trap unit (SONOS, NROM... etc.) are forced to the CMOS logical circuit shared, this method comparatively complexity, costliness and rate of finished products is low, those thermal cycles that the characteristic of logic transistor is formed memory inevitably change, and can not adopt existing C MOS storehouse and IP storehouse.

In a word, present CMOS technology is impelled advanced logic and the further separate development of memory technology, has reduced the purpose that integrated circuit (VLSI) is used for system-on-a-chip really.Nonetheless, because in system-on-a-chip, logic and memory function integrate and can realize high-performance and low-power consumption, Given this advantage, people have paid a large amount of work in order to reach this purpose, are published in such as people such as Yu Hsien Lin in the 782nd to 788 page of article of 2006 the 53rd phases the 4th periodical of " IEEE Transactions on Electron Devices " magazine and disclose employing hafnium oxide (HfO ₂) research of the nanocrystalline storage organization that forms as the charge trap layer.

But in technique scheme, form hafnium oxide (HfO ₂) nanocrystalline technology is still immature at present, is difficult to control, can influence the rate of finished products of semiconductor memory, this research does not simultaneously have to disclose method how to utilize this structure formation system-on-a-chip yet.

Therefore, the method that memory cell and logical circuit are integrated that needs a kind of advanced person.

Summary of the invention

The problem that the present invention solves provides a kind of semiconductor memory cell, drives the method and the semiconductor memory of semiconductor memory cell, integrates with memory cell and logical device with memory, improves the performance of integrated circuit and reduces power consumption.

For addressing the above problem, the invention provides a kind of non-volatility semiconductor memory unit, comprising: Semiconductor substrate, described Semiconductor substrate has first conduction type; First diffusion region is positioned at Semiconductor substrate, and described first diffusion region has second conduction type with first conductivity type opposite; Second diffusion region is positioned at Semiconductor substrate and separates with first diffusion region, forms channel region between described first diffusion region and second diffusion region, and described second diffusion region is identical with the first diffusion region conduction type; Gate dielectric layer is positioned on the Semiconductor substrate of channel region top; Gate electrode is positioned on the described gate dielectric layer; Also comprise: first electric charge storage region and/or second electric charge storage region, described first electric charge storage region is in gate dielectric layer and near the part between the channel region and first diffusion region, described second electric charge storage region is in gate dielectric layer and near the part between the channel region and second diffusion region, the electric charge of described first electric charge storage region and/or the second electric charge storage region stored injects by electric field force.

Described electric field force is to form by apply different voltages to gate electrode, first diffusion region, second diffusion region or Semiconductor substrate, between the described gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage of the PN junction that forms between the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate and second diffusion region and the Semiconductor substrate.

Described voltage difference be not more than the external voltage source 1.5 times of external voltage.

Described gate dielectric layer is that silica, silicon oxynitride, silicon nitride or high K medium material constitute.Described high K medium is H _fO ₂, Al ₂O ₃, La ₂O ₃, H _fSiON or H _fAlO ₂

Described first diffusion region and second diffusion region form by injecting, and described injection comprises that low doping source/drain electrode is injected and heavy-doped source/drain electrode is injected.

Correspondingly, the present invention also provides a kind of method that drives aforesaid semiconductor memory cell, comprise described semiconductor memory cell carried out programming step that described programming step comprises by first electric charge storage region and/or the second electric charge storage region iunjected charge of electric field force in gate dielectric layer.

Described electric field force forms by apply different voltages to gate electrode, first diffusion region, second diffusion region or Semiconductor substrate, between the described gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage of the PN junction that forms between the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate and second diffusion region and the Semiconductor substrate.

Described voltage difference is not more than 1.5 times of external voltage in external voltage source.

The electric charge of described first electric charge storage region, the second electric charge storage region stored produces by band-band tunnelling principle and quickened by the PN junction internal electric field is that the hot charge injection forms.

Described first conduction type is the p type, and described second conduction type is the n type; The condition of the described first electric charge storage region stored charge is: gate electrode connect half of 0V～external voltage, external voltage that Semiconductor substrate meets 0V～negative half, first diffusion region connects external voltage, second diffusion region is vacant and keeps the above-mentioned condition long enough time about 1 μ s～10ms; The condition of the described second electric charge storage region stored charge is: gate electrode connect half of 0～external voltage, external voltage that Semiconductor substrate meets 0V～negative half, vacant, second diffusion region, first diffusion region connects external voltage and keeps above-mentioned condition 1 μ s～10ms; Described first electric charge storage region, second electric charge storage region condition of stored charge simultaneously are: gate electrode connect 0～external voltage half, Semiconductor substrate connects 0～negative external voltage half, first diffusion region and second diffusion region connect external voltage simultaneously and keep the above-mentioned condition long enough time about 1 μ s～10ms.

Described first conduction type is the n type, and described second conduction type is the p type; The condition of the described first electric charge storage region stored charge is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region connect 0V～negative external voltage half, second diffusion region is vacant and keep the above-mentioned condition long enough time about 1 μ s～10ms; The condition of the described second electric charge storage region stored charge is: gate electrode connect external voltage half～0V, Semiconductor substrate connect that external voltage, first diffusion region are vacant, second diffusion region meets 0V～negative external voltage half and keep the above-mentioned condition long enough time about 1 μ s～10ms; Described first electric charge storage region, second electric charge storage region condition of stored charge simultaneously are: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region and second diffusion region and connect 0 simultaneously～negative external voltage half and keep the above-mentioned condition long enough time about 1 μ s～10ms.

The electric charge of described first electric charge storage region, the second electric charge storage region stored quickens to inject formation for hot charge at the PN junction internal electric field by channel current.

Described first conduction type is the p type, and described second conduction type is the n type; The condition of the described first electric charge storage region stored charge is: gate electrode connects 1.5 times of external voltage～external voltage, Semiconductor substrate and connects that 0V, first diffusion region connect external voltage, second diffusion region meets 0V and keeps above-mentioned condition 1 μ s～10ms; The condition of the described second electric charge storage region stored charge is: gate electrode connects 1.5 times of external voltage～external voltage, Semiconductor substrate and connects that 0V, first diffusion region meet 0V, second diffusion region connects external voltage and keeps the above-mentioned condition long enough time about 1 μ s～10ms.

Described first conduction type is the n type, and described second conduction type is the p type; The condition of the described first electric charge storage region stored charge is: gate electrode connect 0V～negative external voltage half, Semiconductor substrate connects that external voltage, first diffusion region meet 0V, second diffusion region connects external voltage and keeps the above-mentioned condition long enough time about 1 μ s～10ms; The condition of the described second electric charge storage region stored charge is: gate electrode connect 0V～negative external voltage half, Semiconductor substrate connects that external voltage, first diffusion region connect external voltage, second diffusion region meets 0V and keeps the above-mentioned condition long enough time about 1 μ s～10ms.

The method of the semiconductor memory cell that described driving is above-mentioned further comprises reads information step in the described semiconductor memory cell, and described sense information obtains by detect the channel current that flows between first diffusion region and second diffusion region.

Described first conduction type is the p type, and described second conduction type is the n type; The described first electric charge storage region canned data of reading is by detecting the electric current acquisition of flowing to first diffusion region in second diffusion region, testing conditions is: gate electrode connect external voltage half～external voltage, Semiconductor substrate meet 0V, first diffusion region and meet 0V, second diffusion region and meet 0.1～1V and keep the above-mentioned condition long enough time, about 1ns～1 μ s also detects channel current; The described second electric charge storage region canned data of reading is by detecting the electric current acquisition of flowing to second diffusion region in first diffusion region, testing conditions is: gate electrode connect external voltage half～external voltage, Semiconductor substrate meet 0V, first diffusion region and meet 0.1～1V, second diffusion region and meet 0V and keep the above-mentioned condition long enough time, about 1ns～1 μ s also detects channel current.

Described first conduction type is the n type, and described second conduction type is the p type; The described first electric charge storage region canned data of reading is by detecting the electric current acquisition of flowing to first diffusion region in second diffusion region, testing conditions is: gate electrode connect negative external voltage half～negative external voltage, Semiconductor substrate meet 0V, first diffusion region and meet 0V, second diffusion region and connect-1～-0.1V and keeping the above-mentioned condition long enough time, about 1ns～1 μ s also detects channel current; The described second electric charge storage region canned data of reading is by detecting the electric current acquisition of flowing to second diffusion region in first diffusion region, testing conditions is: gate electrode connect negative external voltage half～negative external voltage, Semiconductor substrate meet 0V, first diffusion region and connect-1～-0.1V, second diffusion region meet 0V and keep the above-mentioned condition long enough time, about 1ns～1 μ s also detects channel current.

The method of the semiconductor memory cell that described driving is above-mentioned further comprises reads information step in the described semiconductor memory cell, described sense information by detect between first diffusion region and the Semiconductor substrate, grid between second diffusion region and the Semiconductor substrate introduce leakage current and obtain.

Described first conduction type is the p type, and described second conduction type is the n type; The condition that detects the electric current that flows to Semiconductor substrate first diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, first diffusion region connect 1V～external voltage half, second diffusion region is vacant and keep above-mentioned condition 1ns～1 μ s to detect electric current; The condition that detects the electric current that flows to Semiconductor substrate second diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, second diffusion region connect 1V～external voltage half, first diffusion region is vacant and keep above-mentioned condition 1ns～1 μ s to detect electric current; Detecting first diffusion region simultaneously to the Semiconductor substrate and second diffusion region to the condition of the mobile electric current of Semiconductor substrate is: gate electrode meets 0V, Semiconductor substrate connects 0V, first diffusion region and second diffusion region and connects half of 1V～external voltage simultaneously and keep above-mentioned condition 1ns～1 μ s to detect electric current.

Described first conduction type is the n type, and described second conduction type is the p type; The condition that detects the electric current that flows to Semiconductor substrate first diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, first diffusion region connect negative external voltage half～-1V, second diffusion region is vacant and keep above-mentioned condition 1ns～1 μ s to detect electric current; The condition that detects the electric current that flows to Semiconductor substrate second diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, second diffusion region connect negative external voltage half～-1V, first diffusion region is vacant and keep above-mentioned condition 1ns～μ s to detect electric current; The condition that detects the electric current that flows to Semiconductor substrate to Semiconductor substrate and second diffusion region first diffusion region simultaneously is: gate electrode connect 0V, Semiconductor substrate connect 0V, first diffusion region and second diffusion region connect simultaneously negative external voltage half～-1V and keep above-mentioned condition 1ns～1 μ s to detect electric current.

Mobile electric current between Semiconductor substrate adopts the difference current amplifier circuit to detect to the Semiconductor substrate and second diffusion region to detect first diffusion region.

If described memory will be stored analog information, the method of the semiconductor memory cell that described driving is above-mentioned further comprises wipes original information step in the described semiconductor memory cell, and described erasure information step is injected into first electric charge storage region and/or second electric charge storage region with first electric charge storage region and/or the second electric charge storage region charge stored of neutralizing by the electric charge that kind is opposite.

Described first conduction type is the p type, and described second conduction type is the n type; The described first electric charge storage region charge stored is an electronics, the condition of wiping the first electric charge storage region electric charge is: gate electrode connect negative external voltage half～0V, Semiconductor substrate connect 0V, first diffusion region connect external voltage half, second diffusion region is vacant and keep the above-mentioned condition long enough time about 1 μ s～10ms; The described second electric charge storage region charge stored is an electronics, the condition of wiping the second electric charge storage region electric charge is: gate electrode connect negative external voltage half～0V, Semiconductor substrate connect 0V, second diffusion region connect external voltage half, first diffusion region is vacant and keep the above-mentioned condition long enough time about 1 μ s～10ms; Described first electric charge storage region and the second electric charge storage region charge stored are electronics, the condition of wiping first electric charge storage region and the second electric charge storage region charge stored simultaneously is: gate electrode connect negative external voltage half～0V, Semiconductor substrate connect 0V, first diffusion region and second diffusion region and connect half of external voltage simultaneously and keep the above-mentioned condition long enough time about 1 μ s～10ms.

Described first conduction type is the n type, and described second conduction type is the p type; The described first electric charge storage region charge stored is the hole, the condition of wiping the first electric charge storage region charge stored is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region connect negative external voltage half, second diffusion region is vacant and keep the above-mentioned condition long enough time about 1 μ s～10ms; The described second electric charge storage region charge stored is the hole, the condition of wiping the second electric charge storage region charge stored is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, second diffusion region connect negative external voltage half, first diffusion region is vacant and keep the above-mentioned condition long enough time about 1 μ s～10ms; Described first electric charge storage region and the second electric charge storage region charge stored are the hole, the condition of wiping first electric charge storage region and the second electric charge storage region charge stored simultaneously is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region and second diffusion region and connect half of negative external voltage simultaneously and keep the above-mentioned condition long enough time about 1 μ s～10ms.

A kind of semiconductor memory that comprises aforesaid semiconductor memory cell.

The layout type of described semiconductor memory is NOR, NAND, AND or virtual ground.

Compared with prior art, the technical program has the following advantages: utilize existing mos transistor structure, in the gate dielectric layer of MOS transistor, form first electric charge storage region and/or second electric charge storage region by electric field force, constitute required semiconductor memory cell, need not the technology of the extra formation memory cell of prior art, compatible mutually with existing formation logical circuit technology, improve the performance of integrated circuit and reduced power consumption;

The electric field force of the technical program by in first diffusion region, second diffusion region and gate electrode and Semiconductor substrate (being equivalent to body) go up and insert different voltages and form, between the described gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage of the PN junction that forms between the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate and second diffusion region and the Semiconductor substrate.This voltage can make the electric charge in the Semiconductor substrate under the effect of electric field force, enter in the gate dielectric layer near near first diffusion region and/or second diffusion region, form first electric charge storage region and/or second electric charge storage region, information to be stored is preserved into first electric charge storage region and/or second electric charge storage region, realized the function of programming;

The voltage of the gate electrode of the semiconductor memory cell that the access of the technical program is required, first diffusion region, second diffusion region and Semiconductor substrate is realized by the charge pump in the existing integrated circuits, only need change the charge pump progression (stage) that inserts semiconductor memory cell, just can make the output voltage of charge pump reach the voltage range of the technical program, need not to change the structure of other peripheral circuit, can with existing CMOS process compatible, can not cause the technology cost to increase;

The technical program is introduced leakage current or channel current and is read the electric current that flows between first diffusion region and/or second diffusion region by detecting grid, thereby determine the charge information of first electric charge storage region and/or the second electric charge storage region stored, realize the function of reading;

The technical program is injected into first electric charge storage region and/or second electric charge storage region by the electric charge that kind is opposite, eliminates first electric charge storage region and the second electric charge storage region charge stored, thereby realizes programming and erasable purpose repeatedly.

Description of drawings

Fig. 1 is a semiconductor memory cell structural representation of the present invention;

Fig. 2 A, 2B, 2C are the programming principle schematic that employing band of the present invention-band tunnelling principle drives the semiconductor memory cell of n type raceway groove;

Fig. 3 A, 3B, 3C are the programming principle schematic that employing band of the present invention-band tunnelling principle drives the semiconductor memory cell of p type raceway groove;

Fig. 4 A, 4B are the programming principle schematic that employing channel hot electron principle of the present invention drives the semiconductor memory cell of n type raceway groove;

Fig. 5 A, 5B are the programming principle schematic that employing raceway groove hot hole principle of the present invention drives the semiconductor memory cell of p type raceway groove;

Fig. 6 A, 6B are principle schematic of reading the semiconductor memory cell stored information of n type raceway groove by the detection channel current of the present invention;

Fig. 7 A, 7B are principle schematic of reading the semiconductor memory cell stored information of p type raceway groove by the detection channel current of the present invention;

Fig. 8 is principle schematic of reading the semiconductor memory cell stored information of n type raceway groove by detection GIDL of the present invention;

Fig. 9 is principle schematic of reading the semiconductor memory cell stored information of p type raceway groove by detection GIDL of the present invention;

Figure 10 reads the principle schematic of stored information that first electric charge storage region and second electric charge storage region store the memory cell of opposite charges for of the present invention;

Figure 11 wipes the principle schematic of stored information of the semiconductor memory cell of n type raceway groove for employing of the present invention GIDL principle;

Figure 12 wipes the principle schematic of stored information of the semiconductor memory cell of p type raceway groove for employing of the present invention GIDL principle.

Embodiment

The present invention utilizes existing mos transistor structure, in gate dielectric layer, form first electric charge storage region and/or second electric charge storage region by electric field force, constitute required semiconductor memory cell, need not the technology of the extra formation memory cell of prior art, compatible mutually with existing formation logical circuit technology, improve the performance of integrated circuit and reduced power consumption;

Electric field force of the present invention by in first diffusion region, second diffusion region and gate electrode and Semiconductor substrate (being equivalent to body) go up and insert different voltages and form, between described gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage that reaches the PN junction that forms between second diffusion region and the Semiconductor substrate between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate.This voltage can make the electric charge in the Semiconductor substrate under the effect of electric field force, enter in the gate dielectric layer near near first diffusion region and/or second diffusion region, form first electric charge storage region and/or second electric charge storage region, information to be stored is preserved into first electric charge storage region and/or second electric charge storage region, realized the function of programming;

The voltage of the gate electrode of the semiconductor memory cell that access of the present invention is required, first diffusion region, second diffusion region and Semiconductor substrate is realized by the charge pump in the existing integrated circuits, only need change the charge pump progression (stage) that inserts semiconductor memory cell, just can make the output voltage of charge pump reach the voltage range of the technical program, need not to change the structure of other peripheral circuit, can with existing CMOS process compatible, can not cause the technology cost to increase;

The present invention introduces leakage current or channel current and reads the electric current that flows between first diffusion region and/or second diffusion region by detecting grid, thereby determine first electric charge storage region of MOS transistor and/or the charge information of the second electric charge storage region stored, realize the function of reading;

The present invention is injected into first electric charge storage region and/or second electric charge storage region by the electric charge that kind is opposite, eliminates first electric charge storage region and the second electric charge storage region charge stored, thereby realizes programming and erasable purpose repeatedly.

Below describe specific embodiment in detail by the foundation accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:

The present invention at first provides a kind of non-volatility semiconductor memory unit, is used to store two digits information, please refer to Fig. 1, comprising: Semiconductor substrate 100, and described Semiconductor substrate 100 has first conduction type; First diffusion region 102 is positioned at Semiconductor substrate 100, and described first diffusion region 102 has second conduction type with first conductivity type opposite; Second diffusion region 103, be positioned at Semiconductor substrate 100 and with 102 spaces, first diffusion region, be formed with channel region between described first diffusion region 102 and second diffusion region 103, described second diffusion region 103 is identical with first diffusion region, 102 conduction types; Gate dielectric layer 104 is positioned on the Semiconductor substrate 100 of channel region top; Gate electrode 105 is positioned on the described gate dielectric layer 104; First electric charge storage region 106 is in gate dielectric layer 104 and near the part between the channel region and first diffusion region 102; Second electric charge storage region 107 is in gate dielectric layer 104 and near the part between channel region and second diffusion region 103, the electric charge of described first electric charge storage region 106 and/or second electric charge storage region, 107 stored injects by electric field force.

Above-mentioned first electric charge storage region 106, second electric charge storage region 107 can have simultaneously, and the electric charge of described first electric charge storage region 106 or second electric charge storage region, 107 stored injects by electric field force equally.

Described semiconductor memory cell also comprises isolation structure 101, and described isolation structure 101 can be isolated (FOX), carrying out local oxide isolation (LOCOS) or shallow trench isolation for field oxide from (STI), is used for and will realizes lateral isolation between the active device.

Also may be formed with various dopant wells (well) in the described Semiconductor substrate 100; such as being n type dopant well or p type dopant well; the memory cell of n type raceway groove is formed in the p type dopant well; the memory cell of p type raceway groove is formed in the n type dopant well; herein for simplified schematic; not shown, should too not limit protection scope of the present invention at this.

Described gate dielectric layer 104 is that silica, silicon oxynitride, silicon nitride or high K medium material constitute.Usually the high K medium material that adopts is H at present _fO ₂, Al ₂O ₃, La ₂O ₃, H _fSiON or HfAlO ₂Especially at 32nm node and following, adopt the high K medium material usually, and the intrinsic highdensity defective of high K medium material itself can be used as trap and is used for stored charge.

Described first diffusion region 102 and second diffusion region 103 are injected by multistep and are formed, and comprise light gray areas (unmarked) that low doping source among the figure/drain electrode injection forms and the zone (unmarked) that heavily doped source/leakage injection forms.

Above-mentioned semiconductor memory is distinguished with mos transistor structure commonly used and is to exist first electric charge storage region 106 and/or second electric charge storage region 107, and is compatible mutually with existing formation logical circuit technology, improved the performance of integrated circuit and reduced power consumption;

The electric charge of described first electric charge storage region 106 and/or second electric charge storage region, 107 stored injects by first diffusion region, second diffusion region, Semiconductor substrate and gate electrode being applied voltage, between the described gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage of the PN junction that forms between the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate and second diffusion region and the Semiconductor substrate.

The scope of described voltage difference is 1.5 times of external voltage that are not more than external voltage source (Vcc).The external voltage in described external voltage source is corresponding to the operating voltage of the MOS transistor in each generation, and the operating voltage of the MOS transistor in each generation is corresponding to the gate dielectric layer thickness of the MOS transistor in each generation, such as can for

Deng, correspondingly, external voltage can be 3.3V, 2.5V, 1.8V, 1.0V.

And, if required voltage is higher than or when being lower than external voltage, can adopt the charge pump in the existing integrated circuits to drive the memory cell required voltage with realization, such as the progression (stage) of the charge pump by change inserting described memory cell thus reach required voltage of the present invention, and need not to change the structure of other peripheral circuit, even when required voltage is higher than external voltage, also need not additionally to increase the external voltage source, therefore can with existing CMOS process compatible, can not cause the technology cost to increase.

The present invention gives the method that drives above-mentioned semiconductor memory cell, comprise described semiconductor memory cell is carried out programming step, described programming step forms first electric charge storage region by electric field force in gate dielectric layer and/or the second electric charge storage region iunjected charge is carried out, described electric field force passes through to gate electrode, first diffusion region, second diffusion region or Semiconductor substrate apply different voltages and form, between the described gate electrode and first diffusion region, between the gate electrode and second diffusion region, perhaps the voltage difference between first diffusion region and second diffusion region is no more than the puncture voltage of the PN junction that forms between the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate and second diffusion region and the Semiconductor substrate.Provide detailed description at the method that drives semiconductor memory cell of the present invention with reference to the accompanying drawings.

One, adopts band-band tunnelling (BBT, band-to-band transition) principle semiconductor memory cell of the present invention is programmed.

Described driving semiconductor memory of the present invention comprises the method that semiconductor memory cell of the present invention is programmed, promptly in the method for the electric charge of first electric charge storage region and/or the second electric charge storage region stored, described electric charge in first electric charge storage region and/or the second electric charge storage region stored produces by band-band tunnelling principle and quickened by the PN junction internal electric field is that hot charge is injected and formed.

1.n the programming principle of the semiconductor memory cell of type raceway groove

Fig. 2 A to 2C has provided the programming principle schematic that employing band of the present invention-band tunnelling principle drives the semiconductor memory cell of n type raceway groove.This moment, described first conduction type was the p type, and described second conduction type is the n type.

If desire deposits data in semiconductor memory cell, the voltage Vg of gate electrode 105 is 0～Vcc/2, the voltage Vb of Semiconductor substrate 100 be 0V～-Vcc/2, therefore in raceway groove, do not form the transoid electronics; Then, peripheral circuit will need the data of storing to add positive voltage V1 or V2 to bit line respectively by row on first diffusion region 102 of semiconductor memory cell or second diffusion region 103, so the formation reverse biased junction between first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100; Band-band tunnelling by the valence band electronics, in Semiconductor substrate 100, produce the hole near the low doped region of first diffusion region 102 or near the low doped region of second diffusion region 103 and the interface of gate dielectric layer, under the voltage Vb of Semiconductor substrate 100, can move in Semiconductor substrate 100 in described hole, owing to form narrow PN junction between the low doped region of first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100, therefore near the electric field the PN junction is stronger, in first diffusion region 102 or the hole on 103 surfaces, second diffusion region when the PN junction, can under the highfield of PN junction, acceleration obtain kinetic energy, form hot hole, hot hole produces more electron-hole pair by the ionization effect simultaneously, wherein, the thermionic energy that produces is enough big, under the voltage Vg of gate electrode 105, can overcome the interface potential barrier between gate dielectric layer 104 and the Semiconductor substrate 100, enter close channel region and the part between first diffusion region in the gate dielectric layer 104 or enter close channel region in the gate dielectric layer 104 and the part between second diffusion region, promptly be injected into first electric charge storage region 106 or second electric charge storage region 107.

In order to make electronics inject fully, the present invention keeps the time long enough of above-mentioned voltage conditions, and the present invention is set to 1 μ s～10ms.The described retention time is relevant, promptly relevant with the thickness of MOS transistor gate dielectric layer with driving memory cell required voltage.In practical operation, if the retention time is long, may cause the puncture or the state of gate dielectric layer or PN junction to be degenerated, it is too short that time is set, and may cause stored charge to determine to cause upset to what subsequent reads did well inadequately, and the thickness that the present invention is based on concrete gate dielectric layer 104 is considered, above-mentioned condition is kept the long enough time, such as being arranged in 1 μ s～10ms scope, both can reach the purpose of abundant iunjected charge, can prevent from again to puncture or the state upset.The described retention time is relevant with the material of the gate dielectric layer that drives memory cell simultaneously, for gate dielectric layer with trap (traps), the retention time of above-mentioned voltage conditions can be very short, even and the present invention is provided with the purpose of this time and is for there not being trap in the gate dielectric layer, by applying electric field force and keeping certain hour can reach the purpose that forms memory equally.

Among the present invention, the voltage V1 of described first diffusion region 102 is Vcc, this voltage with the access of existing common MOS transistor is different, main purpose is the low doped region of enhancing first diffusion region 102 and the electric field between the Semiconductor substrate 100, thereby the energy that improves the hole makes its acceleration, ionization generate more electron-hole pair, make the electronics of generation have sufficiently high energy, can overcome the interface potential barrier between Semiconductor substrate 100 and the gate dielectric layer 104, enter gate dielectric layer 104, inject first electric charge storage region 106.

As one embodiment of the present of invention, with reference to Fig. 2 A, charge storage is gone into the principle schematic of first electric charge storage region of the semiconductor memory cell of n type raceway groove for adopting band-band tunnelling principle, as shown in the figure, condition at described first electric charge storage region, 106 stored charges is: the voltage Vg of gate electrode 105 is that the voltage Vb of Vcc/2, Semiconductor substrate 100 is that the voltage V1 that connects 0V, first diffusion region 102 is Vcc, second diffusion region 103 for vacant (floating), to keep the time of above-mentioned condition be 1 μ s～10ms, specifically determines according to the thickness of gate dielectric layer.The solid arrow direction indication flows to the direction of the hole stream of Semiconductor substrate 100 among Fig. 2 A.

As an alternative embodiment of the invention, with reference to Fig. 2 B, on the connection basis of Fig. 2 A, the voltage V1 of first diffusion region 102 and the voltage V2 of second diffusion region 103 are inverted, promptly the voltage V1 of first diffusion region 102 is vacant (floating) and the voltage V2 of second diffusion region 103 is that Vcc and the time that keeps above-mentioned condition are 1 μ s～10ms, electric charge can be injected second electric charge storage region 107, this principle is similar to the embodiment of Fig. 2 A, does not add detailed description at this.The solid arrow direction indication flows to the direction of the hole stream of Semiconductor substrate 100 among Fig. 2 B.

Equally, the voltage V2 of second diffusion region 103 is that Vcc has effect and the purpose same with Fig. 2 A, does not also add detailed description at this.

As another embodiment of the present invention, with reference to Fig. 2 C, on the connection basis of Fig. 2 A the voltage V2 of the voltage V1 of first diffusion region 102 and second diffusion region 103 being met Vcc simultaneously and keeps the time of above-mentioned condition is 1 μ s～10ms, electric charge can be stored into simultaneously first electric charge storage region 106 and second electric charge storage region 107, this principle is similar to the embodiment of Fig. 2 A, does not add detailed description at this.The solid arrow direction indication flows to the direction of the hole stream of Semiconductor substrate 100 among Fig. 2 C.

By applying Vcc or apply Vcc simultaneously in first diffusion region 102 and second diffusion region 103 in succession, semiconductor memory cell of the present invention can be realized the programming of two bytes.

2.p the programming principle of the semiconductor memory cell of type raceway groove

Fig. 3 A to 3C has provided the programming principle schematic that employing band of the present invention-band tunnelling principle drives the semiconductor memory cell of p type raceway groove.This moment, described first conduction type was the n type, and described second conduction type is the p type.The programming principle and the aforementioned driving n type channel semiconductor memory cell of the semiconductor memory cell of described driving p type raceway groove are similar.

If desire deposits data in semiconductor memory cell, the voltage Vg of gate electrode 105 is Vcc/2～0V; The voltage Vb of Semiconductor substrate 100 is Vcc; Then, peripheral circuit will need the data of storing to apply voltage to bit line respectively by row on first diffusion region 102 of semiconductor memory cell or second diffusion region 103, the voltage V2 of the voltage V1 of first diffusion region 102 or second diffusion region 103 be 0V～-Vcc/2.Under above-mentioned bias voltage, there is not the transoid hole in the raceway groove, therefore between first diffusion region 102 and second diffusion region 103, there is not channel current.Under voltage V1 or V2, form reverse biased junction between first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100, by the band-band tunnelling of valence band electronics, in Semiconductor substrate 100, produce electronics near the low doped region of first diffusion region 102 or near the low doped region of second diffusion region 103 and the interface of gate dielectric layer.Under the voltage Vb of Semiconductor substrate 100, this electronics can move in Semiconductor substrate 100, again owing to form narrow PN junction between the low doped region of first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100, therefore near the electric field the PN junction is stronger, in first diffusion region 102 or the electronics on 103 surfaces, second diffusion region when the PN junction, can under the highfield of PN junction, quicken, form hot electron, hot electron produces the enough big electron-hole pair of more energy by the ionization effect simultaneously, under the voltage Vg of gate electrode 105, these hot holes can overcome the interface potential barrier between gate dielectric layer 104 and the Semiconductor substrate 100, enter close channel region and the part between first diffusion region 102 in the gate dielectric layer 104 or enter close channel region in the gate dielectric layer 104 and the part between second diffusion region 103, promptly inject first electric charge storage region 106 or second electric charge storage region 107.

Equally, inject fully in order to make the hole, the present invention keeps the above-mentioned voltage conditions long enough time, and the present invention is set to 1 μ s～10ms.

In the present embodiment, the voltage Vb of described Semiconductor substrate 100 is Vcc, the voltage V2 of the voltage V1 of first diffusion region 102 or second diffusion region 103 be 0V～-Vcc/2, this voltage with the access of existing common MOS transistor is different, main purpose makes the high energy of the easier acquisition of charge carrier for the PN junction electric field of formation between the low doped region that increases by first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100.

As one embodiment of the present of invention, with reference to Fig. 3 A, charge storage is gone into the principle schematic of first electric charge storage region of the semiconductor memory cell of p type raceway groove for adopting band-band tunnelling principle, as shown in the figure, condition at described first electric charge storage region, 106 stored charges is: gate electrode 105 voltage Vg are Vcc/2, the voltage Vb of Semiconductor substrate 100 is Vcc, the voltage V1 of first diffusion region 102 is for meeting 0V, the voltage V2 of second diffusion region 103 is vacant (floating) and keep the above-mentioned condition long enough time, about 1 μ s～10ms can be stored into the hole first electric charge storage region 106.

As an alternative embodiment of the invention, with reference to Fig. 3 B, on the connection basis of Fig. 3 A, the voltage V1 of first diffusion region 102 and the voltage V2 of second diffusion region 103 are inverted, be that V1 is that vacant, V2 is for meeting 0V and keeping this condition long enough time, about 1 μ s～10ms, the hole can be stored into second electric charge storage region 107, this principle is similar to the embodiment of Fig. 3 A, does not add detailed description at this.

As another embodiment of the present invention, with reference to Fig. 3 C, the voltage Vb that gate electrode 105 voltage Vg is connect Vcc/2, Semiconductor substrate 100 on the connection basis of Fig. 3 A meets the voltage V1 of Vcc, first diffusion region 102 and the voltage V2 of second diffusion region 103 all meets 0V and keeps this condition long enough time, about 1 μ s～10ms, the hole can be stored into simultaneously first electric charge storage region 106 and second electric charge storage region 107, this principle is similar to the embodiment of Fig. 3 A, does not add detailed description at this.

By in succession first diffusion region 102 and second diffusion region 103 being met 0V or meet 0V simultaneously, semiconductor memory cell of the present invention can be realized the programming of two bytes.

In the method that semiconductor memory cell of the present invention is programmed of above-mentioned employing band-band tunnelling principle, for the memory cell of n type raceway groove, the electric charge that is stored into is an electronics; For the memory cell of p type raceway groove, the electric charge that is stored into is the hole.Yet those skilled in the art understand; by changing grid voltage Vg and Semiconductor substrate voltage Vb height with respect to the first diffusion region voltage V1 or the second diffusion region voltage V2; in the memory cell of n type raceway groove, also can be stored into the hole; also can store electrons in the memory cell of p type raceway groove; these situations all belong to the scope of protection of the present invention, should too not limited at this.

Two, the method that adopts channel hot carrier (Channel-hot carriers) principle that semiconductor memory cell of the present invention is programmed.

Semiconductor memory cell of the present invention programmed to pass through channel hot carrier (Channel-hot carriers) and inject to realize that the electric charge of described first electric charge storage region, the second electric charge storage region stored quickens to inject formation for hot charge by near channel current electric field PN junction.

Fig. 4 A, 4B are the programming principle schematic that employing channel hot electron principle of the present invention drives the semiconductor memory cell of n type raceway groove.This moment, described first conduction type was the p type, and described second conduction type is the n type.

If desire deposits data in shown in Fig. 4 A semiconductor memory cell, then peripheral circuit at first is added to Vcc～1.5Vcc on the gate electrode 105 by row to word line, the voltage of Semiconductor substrate 100 is 0V, makes in the Semiconductor substrate 100 below the gate electrode 105 and produces n type electron channel; The data that peripheral circuit will need to store are by row making alive on first diffusion region 102 of bit line at memory cell or on second diffusion region 103, wherein the voltage V2 of the voltage V1 of first diffusion region 102 or second diffusion region 103 is Vcc, under voltage V1 or V2, form reverse biased junction between first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100.Because the PN junction that forms between the low doped region of first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100 is narrow, near the electric field of the formation PN junction is very strong, the electronics that forms in raceway groove is quickened by the highfield in the PN junction near PN junction the time, form hot electron, hot electron is by the ionization effect then, being progression near first diffusion region 102 or second diffusion region 103 increases, these thermionic energy are enough big, according to heat emission mechanism, the potential barrier that these hot electrons can overcome Semiconductor substrate 100 and gate dielectric layer 104 interfaces enters in first electric charge storage region 106 or second electric charge storage region 107 in the gate dielectric layer 104, simultaneously, at the voltage Vb of Semiconductor substrate 100 is under the 0V condition, and near the hole that produces first diffusion region 102 or second diffusion region 103 is removed.

In order to make electronics inject fully, the present invention keeps the time long enough of above-mentioned voltage conditions, is provided with to be about 1 μ s～10ms.

Among the present invention, the voltage Vg of described gate electrode is Vcc～1.5Vc, the voltage V1 of first diffusion region 102 is Vcc, this is bigger than the voltage that existing common MOS transistor inserts, main purpose is for strengthening the voltage V1 of first diffusion region 102, strengthen the low doped region of first diffusion region 102 and the electric field between the Semiconductor substrate 100, thereby the energy that improves electronics makes its acceleration, ionization generates more electron-hole pair, this moment, electronics had sufficiently high energy, can overcome the interface potential barrier between Semiconductor substrate 100 and the gate dielectric layer 104, enter gate dielectric layer 104, inject first electric charge storage region 106.

As one embodiment of the present of invention, with reference to Fig. 4 A, charge storage is gone into the principle schematic of first electric charge storage region of the semiconductor memory cell of n type raceway groove for adopting raceway groove hot charge principle, as shown in the figure, the condition at described first electric charge storage region, 106 stored charges is: gate electrode 105 voltage Vg are that the voltage Vb of Vcc, Semiconductor substrate 100 is that the voltage V1 of 0V, first diffusion region 102 is that the voltage V2 of Vcc, second diffusion region 103 is 0V and keeps above-mentioned condition 1 μ s～10ms.The solid arrow direction indication flows to the direction of the electron stream in first electric charge storage region 106 among Fig. 4 A.

As another embodiment of the invention, with reference to Fig. 4 B, on the basis of Fig. 4 A connection, the voltage V1 of first diffusion region 102 and the voltage V2 of second diffusion region 103 are inverted, be that V1 is that 0V, V2 are Vcc and keep above-mentioned condition 1 μ s～10ms, charge storage can be gone into second electric charge storage region 107, this principle is similar to the embodiment of Fig. 4 A, does not add detailed description at this.The solid arrow direction indication flows to the direction of the electron stream in second electric charge storage region 107 among Fig. 4 B.

By in succession Vcc being inserted in first diffusion region 102 and second diffusion region 103, semiconductor memory cell of the present invention can be realized the programming of two bytes.

Fig. 5 A, 5B are the programming principle schematic that employing channel hot electron principle of the present invention drives the semiconductor memory cell of p type raceway groove.This moment, described first conduction type was the n type, and described second conduction type is the p type.

If desire deposits data in shown in Fig. 5 A semiconductor memory cell, then peripheral circuit at first by row to word line with the voltage Vg of gate electrode 105 connect 0V～-Vcc/2, the voltage of Semiconductor substrate 100 is Vcc, makes in the Semiconductor substrate 100 below the gate electrode 105 and produces p type electron channel; Peripheral circuit will need the data of storing by row to first diffusion region 102 and second diffusion region 103 making alives of bit line to memory cell, the voltage V1 of first diffusion region 102 is that the voltage V2 of the 0V and second diffusion region 103 is Vcc or with its inversion.Under the voltage of V1 or V2, form reverse biased junction between first diffusion region 102 or second diffusion region 103 and the Semiconductor substrate 100.Because the PN junction that forms between the low doped region of first diffusion region 102 or second diffusion region 103 and the substrate 100 is narrow, electric field in PN junction is very strong, the hole that forms in raceway groove is quickened by the highfield in the PN junction near PN junction the time, form hot hole, hot hole is by the ionization effect then, being progression near first diffusion region 102 or second diffusion region 103 increases, the energy of these hot holes is enough big, according to heat emission mechanism, the potential barrier that these hot holes can overcome Semiconductor substrate 100 and gate dielectric layer 104 interfaces enters first electric charge storage region 106 or second electric charge storage region 107 in the gate dielectric layer 104, be under the condition of Vcc at Semiconductor substrate voltage Vb simultaneously, near the electronics that produces first diffusion region 102 or second diffusion region 103 is removed.

In order to make the hole inject fully, the present invention keeps the time long enough of above-mentioned voltage conditions, is provided with to be about 1 μ s～10ms.

Among the present invention, the voltage Vg of gate electrode 105 meets 0～Vcc/2, the voltage Vb of described Semiconductor substrate 100 is Vcc, this voltage with the access of existing common MOS transistor is different, main purpose is the low doped region of enhancing first diffusion region 102 and the electric field between the Semiconductor substrate 100, thereby the energy that improves the hole makes its acceleration, ionization generate more electron-hole pair, this moment, the hole had sufficiently high energy, can overcome the interface potential barrier between Semiconductor substrate 100 and the gate dielectric layer 104, enter gate dielectric layer 104, inject first electric charge storage region 106.

As one embodiment of the present of invention, with reference to Fig. 5 A, charge storage is gone into the principle schematic of first electric charge storage region of the semiconductor memory cell of p type raceway groove for adopting raceway groove hot charge principle, as shown in Figure 5, the condition at described first electric charge storage region, 106 stored charges is: gate electrode 105 voltage Vg are that the voltage Vb of 0V, Semiconductor substrate 100 is that the voltage V1 of Vcc, first diffusion region 102 is that the voltage V2 of 0V, second diffusion region 103 is Vcc and keeps this condition 1 μ s～10ms.The solid arrow direction indication flows to the direction of the hole stream in first electric charge storage region 106 among Fig. 5 A.

As another embodiment of the invention, with reference to Fig. 5 B, on the basis of Fig. 5 A connection, the voltage V1 of first diffusion region 102 and the voltage V2 of second diffusion region 103 are inverted, be that V1 is that Vcc, V2 are 0V and keep this condition 1 μ s～10ms, charge storage can be gone into second electric charge storage region 107, this principle is similar to the embodiment of Fig. 5 A, does not add detailed description at this.The solid arrow direction indication flows to the direction of the hole stream in second electric charge storage region 107 among Fig. 5 B.

By in succession first diffusion region 102 and second diffusion region 103 being met 0V, semiconductor memory cell of the present invention can be realized the programming of two bytes.

Utilize in channel hot carrier and the method that band-band tunnelling principle is programmed to semiconductor memory cell of the present invention above-mentioned; the electric charge of n type channel transistor structure unit or p type memory cell stores is respectively electronics or hole; but those skilled in the art understand; the polarity of the voltage that applies by change can be injected into the kind of the electric charge of electric charge storage region by change; promptly the electric charge for n type channel transistor structure unit or p type memory cell stores can also be respectively hole or electronics, should too not limit protection scope of the present invention at this.

Among the present invention, during no matter employing band-band tunnelling principle or channel hot carrier principle are programmed, the time long enough that the voltage conditions of required electric field force of programming keeps, such as being 1 μ s～10ms, can in gate dielectric layer, iunjected charge form electric charge storage region, constitute semiconductor memory, need not the ion formation charge trap that injects of the prior art and catch electric charge in gate dielectric layer, technology is simple relatively.And this time that keeps electric field force though reduced storage speed, should still be lower than user's reaction speed for the user time for the user, did not therefore influence actual use.

Three, read the method that is stored in the information in the semiconductor memory cell by detecting channel current (channel).

Described driving semiconductor memory cell of the present invention comprises that also electric current that detection flows is to read the step that is stored in the information in the semiconductor memory cell between first diffusion region and second diffusion region.Described sense information obtains by detect the channel current that flows between first diffusion region and second diffusion region, and the electric current between described detection first diffusion region and second diffusion region comprises electric current that detection is flowed to first diffusion region by second diffusion region and the electric current that is flowed to second diffusion region by first diffusion region.

1. read the principle of the semiconductor memory cell stored information of n type raceway groove

Fig. 6 A, 6B provide and of the present inventionly read the principle schematic of the semiconductor memory cell stored information of n type raceway groove by detecting channel current, and in the case, described first conduction type is the p type, and described second conduction type is the n type.

The principle that detects channel current is: peripheral circuit adds grid voltage Vg by row to word line, and described grid voltage Vg scope is Vcc/2～Vcc, and Semiconductor substrate 100 meets 0V, makes channel region produce electron channel; Peripheral circuit by row to bit line to first diffusion region, 102 making alive V1, and second diffusion region 103 meets 0V; Or second diffusion region, 103 making alive V2, and first diffusion region 102 meets 0V, described V1 or V2 are 0.1～1V, if first electric charge storage region 106 of memory cell or second electric charge storage region 107 were programmed, promptly store electronics, owing in gate dielectric layer 104, store negative electrical charge threshold voltage is raise, therefore from second diffusion region to first diffusion region or the current ratio less (＜1 μ A) that flows to second diffusion region from first diffusion region; If be not programmed, then the current ratio of Liu Donging is than bigger (＞10 μ A).Described bigger or less by current comparison circuit with the acquisition of comparing with above-mentioned electric current of a reference current, then with the big I of above-mentioned channel current to judge whether first or second electric charge storage region stores negative electrical charge separately.

Among the present invention,, keep the condition of above-mentioned read current to be about 1ns～1 μ s and get final product, then the size of read current for the size of fast detecting channel current.

As one embodiment of the present of invention, with reference to Fig. 6 A, provide the schematic diagram of the electric current that detection flows to first diffusion region 102 from second diffusion region 103, actual conditions is: gate electrode 105 voltage Vg are that Vcc, Semiconductor substrate 100 voltage Vb are that the voltage V1 of 0V, first diffusion region 102 is that the voltage V2 of 0V, second diffusion region 103 is 0.1V, and keep this condition 1ns～1 μ s, detect the size of current of first diffusion region 102 then.The direction of the electron stream that the solid arrow direction indication flows to first diffusion region 102 from second diffusion region 103 among Fig. 6 A.

As an alternative embodiment of the invention, on the basis of Fig. 6 A connection, the voltage of first diffusion region 102 and second diffusion region 103 is inverted, promptly V1 is 0.1V, V2 is 0V, and keep this condition 1ns～1 μ s, and can detect the size of current of second diffusion region 103, specifically please refer to Fig. 6 B.Realize among Fig. 6 B that the direction of arrow represents the direction of the electron stream that flows to second diffusion region 103 from first diffusion region 102.

By testing electric current that flows to first diffusion region 102 from second diffusion region 103 or the electric current that flows to second diffusion region 103 from first diffusion region 102 in succession, can read two byte information of memory cell.

2. read the principle of stored information of the semiconductor memory cell of p type raceway groove

With reference to Fig. 7 A, 7B, be the principle schematic of the memory cell stores information that reads p type raceway groove, in the case, described first conduction type is the p type, described second conduction type is the n type.

The principle that detects channel current is: peripheral circuit adds grid voltage Vg by row to word line, and described grid voltage Vg scope be-Vcc/2～-Vcc, Semiconductor substrate 100 meets 0V, makes channel region generation hole channel; Peripheral circuit by row to bit line to first diffusion region, 102 making alive V1 or second diffusion region, 103 making alive V2, described V1 or V2 be-1～-0.1V, if first electric charge storage region 106 of memory cell or second electric charge storage region 107 were programmed, promptly store the hole, owing in gate dielectric layer 104, store the hole threshold voltage is raise (absolute value that is threshold voltage increases), therefore from first diffusion region to second diffusion region or the current ratio less (＜1 μ A) that flows to first diffusion region from second diffusion region; If be not programmed, the current ratio of Liu Donging big (＞10 μ A) then.Described bigger or lessly a reference current and above-mentioned channel current are compared by the difference current amplifier, can judge thus whether first or second electric charge storage region stores negative electrical charge separately.

Among the present invention,, keep the condition of above-mentioned read current to be about 1ns～1 μ s, size of read current then for the size of fast detecting channel current.

As one embodiment of the present of invention, with reference to Fig. 7 A, provide the schematic diagram of the electric current that detection flows to first diffusion region 102 from second diffusion region 103, actual conditions is: gate electrode 104 voltage Vg for-Vcc, Semiconductor substrate 100 voltage Vb are that the voltage V1 of 0V, first diffusion region 102 is that the voltage V2 of 0V, second diffusion region 103 is for-0.1V and keep this condition 1ns～1 μ s.The direction that the direction that arrow is represented among Fig. 7 A flows for the hole of flowing to first diffusion region 102 from second diffusion region 103.

Simultaneously, on the basis of Fig. 7 A connection the voltage of first diffusion region 102 and second diffusion region 103 being inverted and being kept this condition is 1ns～1 μ s, can obtain the electric current that flows to second diffusion region 103 from first diffusion region 102, please refer to Fig. 7 B, the direction of the hole stream that the direction indication of arrow flows to second diffusion region 103 from first diffusion region 102 among Fig. 7 B.

The present invention can read two byte information of memory cell by testing electric current that flows to first diffusion region 102 from second diffusion region 103 or the electric current that flows to second diffusion region 103 from first diffusion region 102 in succession.

In the embodiment of above-mentioned method by detecting the channel current sense information, electric charge for n type channel transistor structure unit or p type memory cell stores is respectively electronics or hole, but be not limited thereto, according to above-mentioned storage principle, electric charge for n type channel transistor structure unit or p type memory cell stores can also be respectively hole or electronics, and those skilled in the art can be by detecting the channel current sense information by the polarity of the voltage that change applies; And if n type channel transistor structure unit charge stored is the hole, then Cun Chu hole can help to attract electronics, and threshold voltage is reduced, and therefore stores the channel current bigger (＞10 μ A) that flows between the diffusion region of cuniculate n type channel transistor structure unit; If p type channel transistor structure unit charge stored is an electronics, same channel current bigger (＞10 μ A).

And above-mentioned by the method that detects the channel current sense information in the electric charge storage region charge stored be not limited to inject by the channel hot carrier mode, can also be by the injection of band-band tunnelling principle, should too not limit protection scope of the present invention at this.

Simultaneously, in the embodiment of above-mentioned method by detecting the channel current sense information, big (＞10 μ A) or less (＜1 μ A) of the electric current that flows between first diffusion region and second diffusion region that described electronics or hole form is relatively and obtains, the described relatively memory cell by this being had memory function and the reference current of reference unit relatively obtain, described reference unit and memory cell have same technology and structure, and do not have electric charge storage region in the gate dielectric layer of reference unit.

In the embodiment of above-mentioned method by detecting the channel current sense information, for n type channel transistor structure unit, the voltage V1 or the V2 of described first diffusion region 102 or second diffusion region 103 are 0.1V～1V; For p type channel transistor structure unit, the voltage V1 of described first diffusion region 103 or second diffusion region 102 or V2 be-1～-0.1V, it is relevant with external voltage Vcc that the size of this voltage is chosen, promptly relevant with the thickness of gate dielectric layer, under the thicker situation of gate dielectric layer, the voltage V1 or the V2 of described first diffusion region 103 or second diffusion region 102 are bigger; Under the thin situation of gate dielectric layer, the voltage V1 or the V2 of described first diffusion region 102 or second diffusion region 103 are less.

At the above-mentioned voltage that applies all with respect to ground connection or 0V voltage, if all voltages comprise gate electrode, Semiconductor substrate, first diffusion region, the voltage of second diffusion region certain numerical value that all raises, the embodiment such as the electric current of the raceway groove that flows to first diffusion region 102 from second diffusion region 103 in above-mentioned detection, the Vcc if all voltages all raise, the voltage Vg scope that is gate electrode is Vcc/2～0V, Semiconductor substrate 100 meets Vcc, the voltage V1 of first diffusion region 102 is Vcc, the voltage V2 of second diffusion region 102 is Vcc-1V～Vcc-0.1V, equally also is feasible.In all embodiment of the present invention, all this change can be made, protection scope of the present invention should be too do not limited at this.

Four, read the method that is stored in the information in the semiconductor memory cell by detecting grid introducing leakage currents (GIDL).

Described sense information can also by detect between first diffusion region and the Semiconductor substrate, grid between second diffusion region and the Semiconductor substrate introduce leakage current and obtain.

The present invention gives by detecting grid and introduces the principle that leakage current is read the semiconductor memory cell stored information of n type raceway groove, and described in the case first conduction type is that p type, second conduction type are the n type.

If the stored information that desire is read first electric charge storage region 106 and second electric charge storage region 107 simultaneously, at this moment, the voltage Vg of gate electrode 105 is 0V, and the voltage Vb of Semiconductor substrate 100 is 0V, does not therefore have the transoid electronics in raceway groove.Peripheral circuit simultaneously adds positive voltage 1V～Vcc/2 to bit line in first diffusion region 102 and second diffusion region 103 of memory cell by row, if first electric charge storage region 106 or second electric charge storage region 107 were programmed, storing negative electrical charge is electronics, then Cun Chu electronics can make near strengthening with interior electric field in first and/or second diffusion region of gate dielectric layer, attract more hole to accumulate in this diffusion region, therefore, between first diffusion region 102 and the Semiconductor substrate 100 and the grid between second diffusion region 103 and the Semiconductor substrate 100 introduce leakage current bigger (＞1 μ A); If it is the hole that first electric charge storage region 106 and second electric charge storage region 107 store positive charge, then between first diffusion region 102 and the Semiconductor substrate 100, the current ratio between second diffusion region 103 and the Semiconductor substrate 100 less (＜0.1uA), promptly among this embodiment, semiconductor memory cell for n type raceway groove, detect the bigger end of gained electric current, illustrate that more negative electrical charge is stored in the electric charge storage region of this end.

Equally, the other end does not have stored charge if first electric charge storage region 106 and second electric charge storage region 107 store that the electric charge of identical type or an end store electric charge, or the amount of the first and second electric charge storage region storages differs bigger, then between first diffusion region 102 and the Semiconductor substrate 100 and the grid between second diffusion region 103 and the Semiconductor substrate 100 introduce leakage current bigger difference (such as differing more than 10 times) arranged, therefore come reference current of comparison and above-mentioned grid to introduce the relative size of leakage current by the difference current amplifier, can judge also whether first or second electric charge storage region stores negative electrical charge separately.

For the size of fast detecting grid introducing leakage current, the time set that keeps above-mentioned test condition is 1ns～1 μ s, reads difference current amplifier output result then.

Pass through said method, can obtain between first diffusion region 102 and the Semiconductor substrate 100 simultaneously, the grid between second diffusion region 103 and the Semiconductor substrate 100 introduce leakage current, the stored information that promptly can read first electric charge storage region 106 and second electric charge storage region 107 simultaneously.

Simultaneously, if first diffusion region 102 or second diffusion region, the 103 non-positive voltages that add 1V～Vcc/2 simultaneously, but there is an end vacant, then can obtain the stored information of an end, meet 1V～Vcc/2 such as first diffusion region 102, and second diffusion region is vacant, and the grid that keep this test condition 1ns～1 μ s can obtain between first diffusion region 102 and the Semiconductor substrate 100 are introduced leakage current (as shown in Figure 8); Perhaps that first diffusion region 102 is vacant, second diffusion region connects 1V～Vcc/2 positive voltage, and keeps this test condition 1ns～1 μ s, can obtain the electric current between second diffusion region 102 and the Semiconductor substrate 100.

2. read the principle of the semiconductor memory cell stored information of p type raceway groove

For the memory cell of p raceway groove, can by on first diffusion region 102 and second diffusion region 103, add-Vcc/2～-negative voltage of 1V obtains the electric current of first diffusion region 102 and second diffusion region 103.

If the stored information that desire is read first electric charge storage region 106 and second electric charge storage region 107 simultaneously, at this moment, the voltage Vg of gate electrode 105 is 0V, and the voltage Vb of Semiconductor substrate 100 is 0V, does not therefore have the transoid hole in raceway groove.If first electric charge storage region 106 of memory cell and second electric charge storage region 107 were programmed, store the hole, then Cun Chu hole can strengthen near the electric field in first and/or second diffusion region of gate dielectric layer, therefore attract more electronics to accumulate in this diffusion region, therefore, between first diffusion region 102 and the Semiconductor substrate 100 and the current ratio between second diffusion region 103 and the Semiconductor substrate 100 big (＞1 μ A); If it is electronics that first electric charge storage region 106 and second electric charge storage region 107 store negative electrical charge, then between first diffusion region 102 and the Semiconductor substrate 100, the current ratio between second diffusion region 103 and the Semiconductor substrate 100 less (＜0.1uA), promptly among this embodiment, semiconductor memory cell for p type raceway groove, detect the bigger end of gained electric current, illustrate that more positive charge is stored in the electric charge storage region of this end.

Equally, if first electric charge storage region 106 and second electric charge storage region 107 store the electric charge of identical type or an end and store the electric charge other end and do not have stored charge, perhaps the amount of first and second electric charge storage regions storage differs bigger, then between first diffusion region 102 and the Semiconductor substrate 100 and the electric current between second diffusion region 103 and the Semiconductor substrate 100 bigger difference (such as differing more than 10 times) is arranged, come reference current of comparison and above-mentioned grid to introduce the relative size of leakage current by the difference current amplifier, can judge also whether first or second electric charge storage region stores positive charge separately

Simultaneously, if first diffusion region 102 or second diffusion region 103 be not add simultaneously-Vcc/2～-negative voltage of 1V, but there is an end vacant, then can read the stored information of an end by the electric current that detects an end, such as first diffusion region 102 connect-Vcc/2～-1V, and second diffusion region 103 is vacant, and keeps this test condition 1ns～1 μ s, can obtain the electric current (as shown in Figure 9) between first diffusion region 102 and the Semiconductor substrate 100; Perhaps voltage is inverted, first diffusion region 102 is vacant, and second diffusion region 103 connects-Vcc/2～-1V, and keep this test condition 1ns～1 μ s, can obtain the electric current between second diffusion region 102 and the Semiconductor substrate 100.

above-mentionedly pass through between first diffusion region and the Semiconductor substrate, grid between second diffusion region and the Semiconductor substrate introduce among the embodiment of leakage current, electric charge for n type channel transistor structure unit or p type memory cell stores is respectively electronics or hole, but be not limited thereto, according to above-mentioned storage principle, can also be respectively hole or electronics for n type channel transistor structure unit or p type channel transistor structure unit charge stored, those skilled in the art can introduce the leakage current sense information by detecting grid by the polarity of the voltage that change applies; And the electric charge storage region canned data is not limited to inject by band-band tunnelling principle in above-mentioned employing grid introducing leakage current method of reading information, can also be to inject by the channel hot carrier mode, should too not limit protection scope of the present invention at this.

Simultaneously, introduce among the embodiment of method of leakage current (GIDL) sense information by detecting grid above-mentioned, big (＞1 μ A) or less (＜0.1 μ A) of the electric current that flows between first diffusion region 102 and second diffusion region 103 that described electronics or hole form is relatively and obtains, the described relatively memory cell by this being had memory function and the reference current of reference unit relatively obtain, described reference unit has same technology and structure with the memory cell with memory function, and does not have electric charge storage region in the gate dielectric layer of reference unit.

Introduce among the embodiment of method of leakage current (GIDL) sense information by detecting grid above-mentioned, for n type channel transistor structure unit, the voltage V1 or the V2 of described first diffusion region 102 or second diffusion region 103 are 1V～Vcc/2; For p type channel transistor structure unit, the voltage V1 or the V2 of described first diffusion region 102 or second diffusion region 103 be-Vcc/2～-1V, it is relevant with external voltage Vcc that the size of this voltage is chosen, promptly relevant with the thickness of gate dielectric layer, under the thicker situation of gate dielectric layer, the voltage V1 or the V2 of described first diffusion region 102 or second diffusion region 103 are bigger; Under the thin situation of gate dielectric layer, the voltage V1 or the V2 of described first diffusion region 102 or second diffusion region 103 are less.

3. the stored information that adopts the difference current amplifier circuit to read semiconductor memory cell

In order to read data on file fast, can detect the electric current relative size that first diffusion region and second diffusion region flow to Semiconductor substrate 100 separately by the difference current amplifier, in the case, a memory cell can be used as byte information of storage, and concrete test philosophy please refer to Figure 10.Semiconductor memory cell is the memory cell of n type raceway groove among Figure 10, promptly first conduction type is the p type, second conduction type is the n type, the gate electrode 105 and the Semiconductor substrate 100 of semiconductor memory cell all meet 0V, first diffusion region 102 and second diffusion region 103 input to two inputs of differential amplifier respectively, the reference voltage of differential amplifier inserts 1V～Vcc/2, the relative size of reference source end and drain terminal electric current, to judge stored information, be defined as " 0 " such as source end electric current greater than the drain terminal current conditions, the drain terminal electric current is given a definition greater than source end current conditions and is " 1 ", described reference voltage level can be in 1V～Vcc/2 scope dynamic optimization, to reach bigger, detect and compare the purpose of grid introducing leakage current and less ground disturbance stored charge quickly.This kind connection with in static random access memory (SRAM), adopted usually similar, in other words, if memory cell stores of the present invention has different types of electric charge, adopt differential amplifier circuit to detect simultaneously, memory cell of the present invention can have the speed of the equally fast sense data of SRAM.

Above-mentioned connection is the semiconductor memory cell at n type raceway groove, semiconductor memory cell for p type raceway groove has similar connection, the voltage Vg of gate electrode 105 is 0V in the time of test, the voltage Vb of Semiconductor substrate 100 is 0V, and first diffusion region 102 and second diffusion region 103 input to two inputs of differential amplifier respectively. the reference voltage access-1V～Vcc/2 of differential amplifier.

The method of the stored information of above-mentioned employing difference current amplifier circuit read semiconductor memory cell is specially adapted to first electric charge storage region and the second electric charge storage region charge stored amount is little but situation that charge species is opposite.

Five, the method for deleting of the stored information of semiconductor memory cell of the present invention

If described memory will be stored analog information, comprise further and wipe original information step in the described semiconductor memory cell that described erasure information step is injected into first electric charge storage region and/or second electric charge storage region with first electric charge storage region and/or the second electric charge storage region charge stored of neutralizing by the electric charge that kind is opposite.

1.n the method for deleting of the stored information of N-type semiconductor N memory cell

If semiconductor memory cell of the present invention is the n type, be that described first conduction type is the p type, described second conduction type is the n type, and described first electric charge storage region or the second electric charge storage region charge stored of wiping can adopt band-band tunnelling (BBT) principle to inject the opposite types electric charge to first electric charge storage region or second electric charge storage region to neutralize and achieve the goal.

If first electric charge storage region 106 stores electronics, concrete erased conditions please refer to Figure 11: gate electrode 105 connects-Vcc/2～0V (in the diagram for-Vcc/2), Semiconductor substrate 100 connects that 0V, first diffusion region 102 meet Vcc/2 and second diffusion region 103 is vacant, and keep this condition 1 μ s～10ms, utilize herein and adopt band-band tunnelling (BBT) principle injected hole to first electric charge storage region 106 in similar principle of programming, specifically principle please refer to the part correlation description of programming.

Equally, if second electric charge storage region 107 stores electronics, and first electric charge storage region 106 does not have store electrons, then gate electrode 105 connect-Vcc/2～0V, Semiconductor substrate 100 meet 0V, second diffusion region 103 is met Vcc/2 and first diffusion region 102 is vacant, and keep this condition 1 μ s～10ms, wipe.

If first electric charge storage region 106 and second electric charge storage region 107 store electronics simultaneously, then can simultaneously first diffusion region 102 and second diffusion region 103 be met Vcc/2, all the other conditions remain unchanged, and injected hole is wiped simultaneously.

2.p the method for deleting of the stored information of N-type semiconductor N memory cell

If semiconductor memory cell of the present invention is the p type, be that described first conduction type is the n type, described second conduction type is the p type, and described first electric charge storage region or the second electric charge storage region charge stored of wiping also can adopt band-band tunnelling (BBT) principle to inject the opposite types electric charge to first electric charge storage region or second electric charge storage region to neutralize and achieve the goal.

If first electric charge storage region 106 stores the hole, concrete erased conditions please refer to Figure 12: and gate electrode 105 meets Vcc/2～0V (being Vcc/2 in the diagram), Semiconductor substrate 100 and meets Vcc, first diffusion region 102 and connect-and Vcc/2 and second diffusion region 103 are vacant and keep this condition 1 μ s～10ms, utilize with adopting band-band tunnelling (BBT) principle herein and inject the electronics similar principle of programming to first electric charge storage region 106 in, specifically principle please refer to the part correlation description of programming.

Equally, if second electric charge storage region 107 stores the hole, and first electric charge storage region 106 is not stored the hole, and then gate electrode 105 meets Vcc/2～0V, Semiconductor substrate 100 and meets Vcc, second diffusion region 103 and connect-Vcc/2 and first diffusion region 102 is vacant and keep this condition 1 μ s～10ms to wipe.

If first electric charge storage region 106 and second electric charge storage region 107 store the hole simultaneously, then gate electrode 105 meets Vcc/2～0V, Semiconductor substrate 100 meets Vcc, simultaneously first diffusion region 102 and second diffusion region 103 connect-Vcc/2, injects electronics simultaneously and wipes.

In the method for deleting of the stored information of said n type or p N-type semiconductor N memory cell, described erasure information step is carried out gradually, such as can (introducing leakage current by the electric current that after injecting opposite kind electric charge a period of time, detects first diffusion region 102 and/or second diffusion region 103 such as passing through detection channel current or grid, similar above-mentioned method of reading information), whether to continue to inject opposite kind electric charge to neutralize fully to judge.If not, then continue to inject the kind opposite charges until neutralization fully, promptly first electric charge storage region 106 and/or second electric charge storage region 107 not the accounts show a surplus of the accumulate lotus.

In the method for deleting of the stored information of said n type or p N-type semiconductor N memory cell, inject if continue the electric charge that kind is opposite, then can reach purpose at the opposite electric charge of electric charge storage region storage kind.

Above-mentioned method for deleting is applicable to semiconductor memory storage analog information, if described semiconductor memory is with storing digital information, the step of then only need writing direct is about to that required electric charge (opposite or identical) is directly a large amount of to inject the erase step when need not to store analog information.

Six, the memory that comprises memory cell of the present invention

Utilize memory cell of the present invention can be combined into semiconductor memory, the layout type of described semiconductor memory can adopt the layout type of existing memory array can satisfy the operation that makes things convenient for reading and writing, wiping simultaneously.Existing many flash arrays comprise NOR, NAND, AND, and the mode of virtual ground etc. is all applicable.

Simultaneously, the present invention does not adopt Fu Le-Nuo Ding (Fowler-Nordheim, F-N) tunnelling mechanism is programmed and erasable, can reduce the voltage of use like this, reduces power consumption.

The present invention adopts band-band tunnelling mechanism to programme or erasure information, can maximize the GIDL electric current by the doping type that does not adopt low doping source/drain extension region (LDD) injection or change polysilicon, these methods can realize by revising domain, need not extra mask step, promptly can not increase the technology cost.

Although adopt logical circuit technology to form memory cell, do not add special technology, if but allow, can more simplify the size of memory cell and the layout of array, such as adopting flush type diffuse source/drain electrode (as source/drain region germanium silicon solid phase epitaxy).

Between the described in the above-described embodiments gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and second diffusion region and the Semiconductor substrate.The safe range of described voltage difference is that external voltage is to 1.5 times of external voltages.Described external voltage (Vcc) can be 3.3V, 2.5V, 1.8V, 1.0V etc. corresponding to the operating voltage of the MOS transistor in each generation.Along with dwindling of dimensions of semiconductor devices, might further reduce, but these all fall into protection scope of the present invention, should too not limited at this.

Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims

1. non-volatility semiconductor memory unit comprises:

Semiconductor substrate, described Semiconductor substrate has first conduction type;

First diffusion region is positioned at Semiconductor substrate, and described first diffusion region has second conduction type with first conductivity type opposite;

Second diffusion region is positioned at Semiconductor substrate and separates with first diffusion region, forms channel region between described first diffusion region and second diffusion region, and described second diffusion region is identical with the first diffusion region conduction type;

Gate dielectric layer is positioned on the Semiconductor substrate of channel region top;

Gate electrode is positioned on the described gate dielectric layer;

It is characterized in that, also comprise:

First electric charge storage region and/or second electric charge storage region, described first electric charge storage region is in gate dielectric layer and near the part between the channel region and first diffusion region, described second electric charge storage region is in gate dielectric layer and near the part between the channel region and second diffusion region, the electric charge of described first electric charge storage region and/or the second electric charge storage region stored injects by electric field force.

2. semiconductor memory cell according to claim 1, described electric field force is to form by apply different voltages to gate electrode, first diffusion region, second diffusion region or Semiconductor substrate, between the described gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage of the PN junction that forms between the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate and second diffusion region and the Semiconductor substrate.

3. semiconductor memory cell according to claim 2, described voltage difference are not more than 1.5 times of external voltage in external voltage source.

4. semiconductor memory cell according to claim 1, described gate dielectric layer are that silica, silicon oxynitride, silicon nitride or high K medium material constitute.

5. semiconductor memory cell according to claim 4, described high K medium are H _fO ₂, Al ₂O ₃, La ₂O ₃, H _fSiON or H _fAlO ₂

6. semiconductor memory cell according to claim 1, described first diffusion region and second diffusion region form by injecting, and described injection comprises that low doping source/drain electrode is injected and heavy-doped source/drain electrode is injected.

7. a method that drives semiconductor memory cell as claimed in claim 1 comprises by first electric charge storage region and/or the second electric charge storage region iunjected charge of electric field force in gate dielectric layer and carries out programming step.

8. the method for driving semiconductor memory cell according to claim 7, described electric field force forms by apply different voltages to gate electrode, first diffusion region, second diffusion region or Semiconductor substrate, between the described gate electrode and first diffusion region, between gate electrode and second diffusion region or the voltage difference between first diffusion region and second diffusion region be no more than the puncture voltage of the PN junction that forms between the puncture voltage of the PN junction that forms between the puncture voltage of gate dielectric layer and first diffusion region and the Semiconductor substrate and second diffusion region and the Semiconductor substrate.

9. the method for driving semiconductor memory cell according to claim 8, described voltage difference are not more than 1.5 times of external voltage in external voltage source.

10. the method for driving semiconductor memory cell according to claim 9, the electric charge of described first electric charge storage region, the second electric charge storage region stored produce by band-band tunnelling principle and quickened by near the electric field PN junction is that the hot charge injection forms.

11. the method for driving semiconductor memory cell according to claim 10, described first conduction type is the p type, and described second conduction type is the n type;

The condition of the described first electric charge storage region stored charge is: gate electrode connect half of 0V～external voltage, external voltage that Semiconductor substrate meets 0V～negative half, first diffusion region connects external voltage, second diffusion region is vacant and keeps above-mentioned condition 1 μ s～10ms;

The condition of the described second electric charge storage region stored charge is: gate electrode connect half of 0～external voltage, external voltage that Semiconductor substrate meets 0V～negative half, vacant, second diffusion region, first diffusion region connects external voltage and keeps above-mentioned condition 1 μ s～10ms;

Described first electric charge storage region, second electric charge storage region condition of stored charge simultaneously are: gate electrode connect 0～external voltage half, Semiconductor substrate connects 0～negative external voltage half, first diffusion region and second diffusion region connect external voltage simultaneously and keep above-mentioned condition 1 μ s～10ms.

12. the method for driving semiconductor memory cell according to claim 10, described first conduction type is the n type, and described second conduction type is the p type;

The condition of the described first electric charge storage region stored charge is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region connect 0V～negative external voltage half, second diffusion region is vacant and keep above-mentioned condition 1 μ s～10ms;

The condition of the described second electric charge storage region stored charge is: gate electrode connect external voltage half～0V, Semiconductor substrate connect that external voltage, first diffusion region are vacant, second diffusion region meets 0V～negative external voltage half and keep above-mentioned condition 1 μ s～10ms;

Described first electric charge storage region, second electric charge storage region condition of stored charge simultaneously are: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region and second diffusion region and connect 0 simultaneously～negative external voltage half and keep above-mentioned condition 1 μ s～10ms.

13. the method for driving semiconductor memory cell according to claim 9, the electric charge of described first electric charge storage region, the second electric charge storage region stored quickens to inject formation for hot charge at the PN junction internal electric field by channel current.

14. the method for the driving semiconductor memory cell of stating according to claim 13, described first conduction type is the p type, and described second conduction type is the n type;

The condition of the described first electric charge storage region stored charge is: gate electrode connects 1.5 times of external voltage～external voltage, Semiconductor substrate and connects that 0V, first diffusion region connect external voltage, second diffusion region meets 0V and keeps above-mentioned condition 1 μ s～10ms;

The condition of the described second electric charge storage region stored charge is: gate electrode connects 1.5 times of external voltage～external voltage, Semiconductor substrate and connects that 0V, first diffusion region meet 0V, second diffusion region connects external voltage and keeps above-mentioned condition 1 μ s～10ms.

15. the method for driving semiconductor memory cell according to claim 13, described first conduction type is the n type, and described second conduction type is the p type;

The condition of the described first electric charge storage region stored charge is: gate electrode connect 0V～negative external voltage half, Semiconductor substrate connects that external voltage, first diffusion region meet 0V, second diffusion region connects external voltage and keeps above-mentioned condition 1 μ s～10ms;

The condition of the described second electric charge storage region stored charge is: gate electrode connect 0V～negative external voltage half, Semiconductor substrate connects that external voltage, first diffusion region connect external voltage, second diffusion region meets 0V and keeps above-mentioned condition 1 μ s～10ms.

16. the method for driving semiconductor memory cell according to claim 9 further comprises by detect the channel current that flows between first diffusion region and second diffusion region and reads information step in the described semiconductor memory cell.

17. the method for driving semiconductor memory cell according to claim 16, described first conduction type is the p type, and described second conduction type is the n type;

The described first electric charge storage region canned data of reading obtains by the electric current that detects second diffusion region and flow to first diffusion region, and testing conditions is: gate electrode connect external voltage half～external voltage, Semiconductor substrate meet 0V, first diffusion region and meet 0V, second diffusion region and meet 0.1～1V and keep above-mentioned condition 1ns～1 μ s and detect channel current;

The described second electric charge storage region canned data of reading obtains by the electric current that detects first diffusion region and flow to second diffusion region, and testing conditions is: gate electrode connect external voltage half～external voltage, Semiconductor substrate meet 0V, first diffusion region and meet 0.1～1V, second diffusion region and meet 0V and keep above-mentioned condition 1ns～1 μ s and detect channel current.

18. the method for driving semiconductor memory cell according to claim 16, described first conduction type is the n type, and described second conduction type is the p type;

The described first electric charge storage region canned data of reading obtains by the electric current that detects second diffusion region and flow to first diffusion region, and testing conditions is: gate electrode connect negative external voltage half～negative external voltage, Semiconductor substrate meet 0V, first diffusion region and meet 0V, second diffusion region and connect-1～-0.1V and keep above-mentioned condition 1ns～1 μ s and detect channel current;

The described second electric charge storage region canned data of reading obtains by the electric current that detects first diffusion region and flow to second diffusion region, and testing conditions is: gate electrode connect negative external voltage half～negative external voltage, Semiconductor substrate meet 0V, first diffusion region and connect-1～-0.1V, second diffusion region meet 0V and keep above-mentioned condition 1ns～1 μ s and detect channel current.

19. the method for driving semiconductor memory cell according to claim 9, further comprise by detect between first diffusion region and the Semiconductor substrate, grid between second diffusion region and the Semiconductor substrate introduce leakage current and read information step in the described semiconductor memory cell.

20. the method for driving semiconductor memory cell according to claim 19, described first conduction type is the p type, and described second conduction type is the n type;

The condition that detects the electric current that flows to Semiconductor substrate first diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, first diffusion region connect 1V～external voltage half, second diffusion region is vacant and keep above-mentioned condition 1ns～1 μ s to detect electric current;

The condition that detects the electric current that flows to Semiconductor substrate second diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, second diffusion region connect 1V～external voltage half, first diffusion region is vacant and keep above-mentioned condition 1ns～1 μ s to detect electric current;

Detecting first diffusion region simultaneously to the Semiconductor substrate and second diffusion region to the condition of the mobile electric current of Semiconductor substrate is: gate electrode meets 0V, Semiconductor substrate connects 0V, first diffusion region and second diffusion region and connects half of 1V～external voltage simultaneously and keep above-mentioned condition 1ns～1 μ s to detect electric current.

21. the method for driving semiconductor memory cell according to claim 19, described first conduction type is the n type, and described second conduction type is the p type;

The condition that detects the electric current that flows to Semiconductor substrate first diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, first diffusion region connect negative external voltage half～-1V, second diffusion region is vacant and keep above-mentioned condition 1ns～1 μ s to detect electric current;

The condition that detects the electric current that flows to Semiconductor substrate second diffusion region is: gate electrode connect 0V, Semiconductor substrate connect 0V, second diffusion region connect negative external voltage half～-1V, first diffusion region is vacant and keep above-mentioned condition 1ns～1 μ s to detect electric current;

The condition that detects the electric current that flows to Semiconductor substrate to Semiconductor substrate and second diffusion region first diffusion region simultaneously is: gate electrode connect 0V, Semiconductor substrate connect 0V, first diffusion region and second diffusion region connect simultaneously negative external voltage half～-1V and keep above-mentioned condition 1ns～1 μ s to detect electric current.

22. the method for driving semiconductor memory cell according to claim 19, mobile electric current between Semiconductor substrate adopts the difference current amplifier circuit to detect to the Semiconductor substrate and second diffusion region to detect first diffusion region.

23. the method for driving semiconductor memory cell according to claim 9, if described memory will store analog information, further comprise by the electric charge that kind is opposite being injected into first electric charge storage region and/or second electric charge storage region is wiped information step in the described semiconductor memory cell with neutralize first electric charge storage region and/or the second electric charge storage region charge stored.

24. the method for driving semiconductor memory cell according to claim 23, described first conduction type is the p type, and described second conduction type is the n type;

The described first electric charge storage region charge stored is an electronics, and the condition of wiping the first electric charge storage region electric charge is: gate electrode connect negative external voltage half～0V, Semiconductor substrate connect 0V, first diffusion region connect external voltage half, second diffusion region is vacant and keep above-mentioned condition 1 μ s～10ms;

The described second electric charge storage region charge stored is an electronics, and the condition of wiping the second electric charge storage region electric charge is: gate electrode connect negative external voltage half～0V, Semiconductor substrate connect 0V, second diffusion region connect external voltage half, first diffusion region is vacant and keep above-mentioned condition 1 μ s～10ms;

Described first electric charge storage region and the second electric charge storage region charge stored are electronics, and the condition of wiping first electric charge storage region and the second electric charge storage region charge stored simultaneously is: gate electrode connect negative external voltage half～0V, Semiconductor substrate connect 0V, first diffusion region and second diffusion region and connect half of external voltage simultaneously and keep above-mentioned condition 1 μ s～10ms.

25. the method for driving semiconductor memory cell according to claim 23, described first conduction type is the n type, and described second conduction type is the p type;

The described first electric charge storage region charge stored is the hole, and the condition of wiping the first electric charge storage region charge stored is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region connect negative external voltage half, second diffusion region is vacant and keep above-mentioned condition 1 μ s～10ms;

The described second electric charge storage region charge stored is the hole, and the condition of wiping the second electric charge storage region charge stored is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, second diffusion region connect negative external voltage half, first diffusion region is vacant and keep above-mentioned condition 1 μ s～10ms;

Described first electric charge storage region and the second electric charge storage region charge stored are the hole, and the condition of wiping first electric charge storage region and the second electric charge storage region charge stored simultaneously is: gate electrode connect external voltage half～0V, Semiconductor substrate connect external voltage, first diffusion region and second diffusion region and connect half of negative external voltage simultaneously and keep above-mentioned condition 1 μ s～10ms.

26. semiconductor memory that comprises semiconductor memory cell as claimed in claim 1.

27. semiconductor memory according to claim 26, the layout type of described semiconductor memory are NOR, NAND, AND or virtual ground.