CN101826123A - Method for promoting chip finished product rate through increasing standard cell through hole - Google Patents

Abstract

The invention discloses a method for promoting chip finished product rate through increasing standard cell through holes. The method comprises the following steps: taking a greatest common divisor (lambada) regulated in chip design rules as a basic unit, evenly dividing a standard cell layout into rectangular grids, and setting grid point attribute structures and grid point attribute matrixes; through wave propagation operation and the and operation of the layout grid point attribute matrixes, dividing the through holes into through holes for connecting polysilicon and metals and through holes for connecting active regions and metals; conducting the wave propagation operations to the two kinds of through holes respectively at a through hole layer, a polysilicon layer, an active region layer and a metal layer, and conducting the and operations to the results of the wave propagation operations to obtain extensible subregions; and evenly increasing the through holes in the extensible subregions and modifying the layout grid point attribute matrixes to complete the increase of the standard cell through holes. On the premise that the area of the standard cell layout is unchanged, through increasing redundant through holes, the invention has the advantages that the probability of defects caused by through hole failure to standard cells is reduced, and the finished product rate of the standard cells can be obviously improved at low cost.

Description

A kind of method that increases standard cell through holes lifting chip yield

Technical field

The present invention relates to promote the method for chip yield, especially, belong to the integrated circuit (IC) design field by increasing the method that standard cell through holes promotes chip yield.

Background technology

In ic manufacturing process, defective appears owing to various uncertain reasons cause through hole in the chip production process (Contact), and cause resistance to increase unusually, even open defect occurs.The change of through hole electric property will influence the function of chip, influences the yield rate of chip.

Defective hole shows as probability event at random, and the reason that causes random defect to produce has: exist photoresist impurity, deposit to cause cavity, levels to be aimed to make mistakes, ambient impurities particle, cmp (CMP) cross and grind etc.These defectives show as the random chance incident that meets certain distribution, can reduce defective hole from two aspects, improve production technology on the one hand, reduce the defective workmanship probability density; The another one aspect increases redundant domain, reduces the susceptibility of domain to defective.

Distribute if single defective hole satisfies Poisson (Poisson), all defective hole incidents all are separate, then obtain the chip single-pass hole yield model of industry member:

Y _Contact=e ^{-N* λ}, λ is a single-pass hole defect probability, N is single-pass number of perforations (1)

If the increase redundant via converts the single-pass hole to doubled via, the probability that defective appears in doubled via simultaneously be the single-pass hole defective appears and 1/4.Increase redundant via, can reduce the susceptibility of domain, improve the yield rate of chip defective.

Standard block is the foundation stone of ASIC/SoC design, is used by thousands of in design inferiorly.Through discovering, the white space that exists in the standard unit picture can increase redundant via, do not increasing under the prerequisite that the standard block area do not change standard block technology characteristics parameter, the unit that can debase the standard improves the yield rate of product to the susceptibility of defective.

Summary of the invention

The purpose of this invention is to provide a kind of method that standard cell through holes promotes chip yield that increases,, improve yield rate to be implemented in the cell via shortage probability that debases the standard under the prerequisite that does not increase the standard block area and do not change the technology characteristics parameter.

Increase standard cell through holes of the present invention promotes the method for chip yield, may further comprise the steps:

1) will pass through Stein algorithm cycle calculations after the chip design regular integerization, obtain the highest common factor λ of design rule; With λ is base unit, standard block polysilicon layer, active region layer, via layer and metal level domain evenly are divided into rectangular node, no figure then is provided with the lattice point attribute for " 0 " on the lattice point, has figure that the lattice point attribute then is set on the lattice point and is " 1 ", constitutes each layer lattice point attribute matrix;

2) do the ripple propagation operation from the set point of domain: from the set point of lattice point attribute matrix, up and down, left and right four direction searches the lattice point that equals this set point property value, to around expansion till the lattice point that does not equal this set point property value;

Domain lattice point attribute matrix is done and operated: the corresponding property value of each lattice point of domain lattice point attribute matrix of two identical sizes is done the logical and operation respectively, rule equals " 0 " for " 0 " and " 0 ", " 0 " equals " 0 " with " 1 ", " 1 " equals " 0 " with " 0 ", and " 1 " equals " 1 " with " 1 ";

3) through-hole type of division via layer: do the ripple propagation operation of lattice point attribute for " 1 " at polysilicon layer, do the ripple propagation operation of lattice point attribute at active region layer for " 0 ", twice wave-propagation results carried out " with computing ", there is " 1 " in " with computing " result's sub-attribute matrix, judges that through hole is the through hole that connects polysilicon and metal; Do the ripple propagation operation of lattice point attribute at polysilicon layer for " 0 ", do the ripple propagation operation of lattice point attribute at active region layer for " 1 ", twice wave-propagation results carried out " with computing ", there is " 1 " in " with computing " result's sub-attribute matrix, judges that through hole is the through hole that is connected with source region and metal;

Calculating via-first power: the through hole that the sub-attribute matrix of via layer through-hole type partition process is equated is labeled as and linked hole, the number of calculating " 1 " in the sub-attribute matrix with and the inverse of linked hole number product, obtain via-first power;

4) weigh according to via-first, under the chip design rule constrain, calculate the subregion expanded of the through hole of connection polysilicon and metal: propagate, after polysilicon layer elder generation does the propagation of " 1 " ripple, do the propagation of " 0 " ripple at via layer work " 0 " ripple, do the propagation of " 0 " ripple, do work " 0 " ripple propagation of " 1 " ripple propagation back in metal level elder generation at active region layer, each subwave propagation operation result is done and operates, and acquisition can be expanded subregion;

Weigh according to via-first, under the chip design rule constrain, calculating is connected with the subregion expanded of the through hole of source region and metal: propagate, propagate at polysilicon layer work " 0 " ripple, do the propagation of " 0 " ripple at via layer work " 0 " ripple after active region layer elder generation work " 1 " ripple is propagated, do work " 0 " ripple propagation of " 1 " ripple propagation back in metal level elder generation, each subwave propagation operation result is done and operates, and acquisition can be expanded subregion;

In the subregion expanded of through hole, evenly increase through hole, in corresponding domain layer, increase domain according to the chip design rule, and revision figure lattice point attribute matrix, the increase of standard cell through holes finished.

The present invention has the following advantages:

1) scope that the through hole maximum extent has been dwindled the ripple propagation operation effectively is set, has improved the domain search efficiency;

2) by increasing redundant via at the standard unit picture white space, not sacrificing chip area, do not change under the prerequisite of technology characteristics parameter, the cell via that debases the standard shortage probability improves yield rate.

Description of drawings

Fig. 1 is two inputs and door domain, and wherein (a) is the active region layer domain, (b) is polysilicon domain layer by layer, (c) is the via layer domain, (d) is the metal level domain;

Fig. 2 is an active region layer lattice point attribute matrix synoptic diagram;

Fig. 3 is a ripple propagation operation synoptic diagram;

Fig. 4 is domain and operation chart, and wherein (a) and (b) are and the operation input, (c) are and the operation result;

Fig. 5 is a through hole expansion process synoptic diagram, wherein (a) is via layer expansion process synoptic diagram, and (b) active region layer expansion process synoptic diagram (c) is polysilicon layer expansion process synoptic diagram, (d) be metal level expansion process synoptic diagram, (e) for can expand the subregion synoptic diagram

Embodiment

Be example with standard block two inputs with door below, the present invention is described.The domain of two inputs and door (a) is active area (Active) layer domain as shown in Figure 1, (b) is polysilicon layer (Poly) layer domain, (c) is through hole (Contact) layer domain, (d) is metal (Metal) layer domain.It is example with the through hole that " 1 " among Fig. 1 (c) indicates that this routine through hole increases process.

1, will pass through Stein algorithm cycle calculations after the chip design regular integerization, obtain the highest common factor λ of design rule; With λ is base unit, standard block polysilicon layer, active region layer, via layer and metal level domain evenly are divided into rectangular node, no figure then is provided with the lattice point attribute for " 0 " on the lattice point, has figure that the lattice point attribute then is set on the lattice point and is " 1 ", constitutes each layer lattice point attribute matrix;

With design rule parameter multiplication by constants 1000, the design rule parameter is converted to natural number from floating number.The highest common factor of design rule parameter calculates by following steps:

(1) the design rule parameter is sorted by size, the design rule parameter that deletion ordering back equates with previous value constitutes the collating sequence DR that does not comprise repetition values;

(2) set K ₀Equal DR ₀Recycling Stein algorithm computation design rule DR _iWith K _I-1Highest common factor K _i, i=1 ..., n; K _nBe exactly the highest common factor λ of all design rules.

The accurate cell layout horizontal direction size of bidding is SizeX, and vertically size is SizeY.For making the domain operation meet design rule, reduce operand, this example is a base unit with the highest common factor λ of design rule, standard block polysilicon layer, active region layer, via layer and metal level domain are divided into (SizeX/ λ) * (SizeY/ λ) rectangular node respectively, and basic grid is the square of λ * λ.The lattice point attribute is set during no figure on the lattice point and is " 0 ", the lattice point attribute is set when on the lattice point figure being arranged is " 1 ".Each layer of standard block domain can be expressed as the lattice point attribute matrix of (SizeX/ λ, SizeY/ λ) after lattice point is divided.The corresponding identical domain planimetric position of the lattice point of same index index in each layer domain lattice point attribute matrix.Fig. 2 is the lattice point attribute matrix of the active region layer domain of two inputs and door, and the oblique line lattice are represented " 1 ", and white square is represented " 0 ".

If submatrix SubMetr _{(iMin, jMin), (iMax, jMax)}Horizontal subscript is not less than iMin, is not more than iMax in the corresponding domain lattice point attribute matrix, and vertical subscript is not less than jMin, is not more than the rectangular area of the lattice point composition of jMax.

2, do the ripple propagation operation from the set point of domain: from the set point of lattice point attribute matrix, up and down, left and right four direction searches the lattice point that equals this set point property value, to around expansion till the lattice point that does not equal this set point property value; Domain lattice point attribute matrix is done and operated: the corresponding property value of each lattice point of domain lattice point attribute matrix of two identical sizes is done the logical and operation respectively, rule equals " 0 " for " 0 " and " 0 ", " 0 " equals " 0 " with " 1 ", " 1 " equals " 0 " with " 0 ", and " 1 " equals " 1 " with " 1 ";

Domain ripple propagation operation is from certain point (or some point) of lattice point attribute matrix, respectively up and down, left and right four direction searches set-point, circulation from equivalent point to around expansion, up to around do not equal the lattice point of set-point till.The ripple propagation operation can obtain the maximum continuum that comprises set-point that begins from set point." 0 " is worth continuous white space on the region representation domain continuously; " 1 " value region representation domain has the zone of figure continuously.If be designated as imin under the minimum of the horizontal direction of the lattice point that expands in the ripple expansion process, be designated as imax under the maximum of horizontal direction, vertically be designated as jmin under the minimum, be designated as jmax under the maximum longitudinally.The result of ripple propagation operation is a sub-lattice point attribute matrix, is expressed as SubMetr _{(iMin, jMin), (iMax, jMax)}, the attribute of the point that this submatrix medium wave propagation arrives is " 1 ", does not have the attribute of the lattice point of arrival to be " 0 ".

Domain ripple propagation operation as shown in Figure 3, " S " is that ripple propagates starting point, numeral is indicated the ripple communication process.

Domain is that the corresponding property value of each lattice point of domain lattice point attribute matrix of two identical sizes is done the logical and operation respectively with operation, rule equals " 0 " for " 0 " and " 0 ", " 0 " equals " 0 " " 1 " with " 1 " and equals " 0 " with " 0 ", and " 1 " equals " 1 " with " 1 ".“ ﹠amp among the present invention; " symbol all represents domain and operation.

Domain and operation chart as shown in Figure 4, lattice point attribute matrix (a) and (b) be and the operation input, (c) be and the operation result.

3, divide the through-hole type of via layer: do the ripple propagation operation of lattice point attribute for " 1 " at polysilicon layer, do the ripple propagation operation of lattice point attribute at active region layer for " 0 ", twice wave-propagation results carried out " with computing ", there is " 1 " in " with computing " result's sub-attribute matrix, judges that through hole is the through hole that connects polysilicon and metal; Do the ripple propagation operation of lattice point attribute at polysilicon layer for " 0 ", do the ripple propagation operation of lattice point attribute at active region layer for " 1 ", twice wave-propagation results carried out " with computing ", there is " 1 " in " with computing " result's sub-attribute matrix, judges that through hole is the through hole that is connected with source region and metal; Calculating via-first power: the through hole that the sub-attribute matrix of via layer through-hole type partition process is equated is labeled as and linked hole, the number of calculating " 1 " in the sub-attribute matrix with and the inverse of linked hole number product, obtain via-first power;

Through hole can be divided into two classes by the target domain difference that connects: connect polysilicon and metal, be connected with source region and metal.The problem difference that the expansion of these two kinds of through holes will be considered need be treated with a certain discrimination.

The determination methods of through-hole type is as follows:

From the center of through hole, do " 1 " value ripple propagation operation at polysilicon layer lattice point attribute matrix, obtain submatrix SubMetr _{Poly_1}From the center of through hole, do " 0 " value ripple propagation operation at active region layer lattice point attribute matrix, obtain submatrix SubMetr _{Active_0}With SubMetr _{Poly_1}With SubMetr _{Active_0}Do domain and operation:

SubMetr _{cnt_poly}＝SubMetr _{poly_1}?&?SubMetr _{active_0}(2)

If SubMetr _{Cnt_poly}There is the lattice point of lattice point attribute, show that through hole is to connect polysilicon and upper strata metal, establishes submatrix SubMetr for " 1 " _CntEqual SubMetr _{Cnt_poly}

Otherwise, begin to do the operation of " 1 " value ripple from the through hole center at active region layer, obtain submatrix SubMetr _{Active_1}Begin to do the operation of " 0 " value ripple from the through hole center and obtain submatrix SubMetr at polysilicon layer _{Poly_0}With SubMetr _{Active_1}With SubMetr _{Poly_0}Do domain and operation:

SubMetr _{cnt_active}＝SubMetr _{active_1}?&?SubMetr _{poly_0}。(3)

If SubMetr _{Cnt_active}There is the lattice point of lattice point attribute, show that through hole is connected with source region and upper strata metal, establish SubMetr for " 1 " _CntEqual SubMetr _{Cnt_active}

SubMetr _CntThe through hole that equates connects same area polysilicon or active area, and is identical on electric property, is called and linked hole.And linked hole is merged into the calculating of a virtual through hole participation right of priority.If SubMetr _CntIn the number of " 1 " be Count ₁, and the linked hole number is Cnt _Par(the Cnt in single-pass hole _ParEqual 1).

For the through hole after merging, be calculated as follows via-first power Cnt _Priority:

${\mathrm{Cnt}}_{\mathrm{priority}}=\frac{1}{{\mathrm{<figure-callout\; id="1"\; label="Count"\; filenames="HSA00000019501700022.png,HSA00000019501700041.png"\; state="\{\{state\}\}">Count</figure-callout>}}_1\&times;{\mathrm{Cnt}}_{\mathrm{par}}}---\left(4\right)$

The through hole occupied area is big more, and right of priority is low more; And the linked hole number is many more, and right of priority is low more.

If SubMetr _CntBe designated as under the horizontal direction minimum under imin, the horizontal direction maximum and be designated as imax, vertically be designated as jmin under the minimum, vertically be designated as jmax under the maximum, establish through hole horizontal direction size and be Cnt _SizeX, vertically be Cnt _SizeY, the through hole minimum spacing is Dist _Cnt, then the horizontal direction subscript is not less than imin-2 * (Cnt _SizeX+ Dist _Cnt), be not more than imax+2 * (Cnt _SizeX+ Dist _Cnt), vertically subscript is not less than jmin-2 * (Cnt _SizeX+ Dist _Cnt), be not more than jmax+2 * (Cnt _SizeX+ Dist _Cnt) corresponding zone is this through hole maximum extent.Zone, i.e. the maximum extension scope of through hole 1 shown in Fig. 5 (a) dashed rectangle.

By the ordering of via-first power, can obtain the through hole sequence of operation.

4, weigh according to via-first, under the chip design rule constrain, calculate the subregion expanded of the through hole of connection polysilicon and metal: propagate, after polysilicon layer elder generation does the propagation of " 1 " ripple, do the propagation of " 0 " ripple at via layer work " 0 " ripple, do the propagation of " 0 " ripple, do work " 0 " ripple propagation of " 1 " ripple propagation back in metal level elder generation at active region layer, each subwave propagation operation result is done and operates, and acquisition can be expanded subregion; Weigh according to via-first, under the chip design rule constrain, calculating is connected with the subregion expanded of the through hole of source region and metal: propagate, propagate at polysilicon layer work " 0 " ripple, do the propagation of " 0 " ripple at via layer work " 0 " ripple after active region layer elder generation work " 1 " ripple is propagated, do work " 0 " ripple propagation of " 1 " ripple propagation back in metal level elder generation, each subwave propagation operation result is done and operates, and acquisition can be expanded subregion; In the subregion expanded of through hole, evenly increase through hole, in corresponding domain layer, increase domain according to the chip design rule, and revision figure lattice point attribute matrix, the increase of standard cell through holes finished;

The restrictive condition of two kinds of through holes that connect polysilicon and metal, is connected with source region and metal is different, and expansion process is different, separates explanation below.

(1) through hole that connects polysilicon and metal is expanded

The through hole expansion process that connects polysilicon and metal is the example explanation with two inputs shown in Figure 1 and the through hole " 1 " of door.

1. calculate the via layer expandable area under through hole minimum spacing design rule constraints

In through hole largest extension zone, do " 0 " value ripple propagation operation from the property value of next-door neighbour's through hole for the position of " 0 " in via layer, obtain continuously " 0 " value zone.Should the zone inner and outer boundary retraction through hole minimum spacing design rule, obtain the zone that this layer can increase through hole.Any position increases through hole in this zone, does not violate design rule with original via layer figure.Ripple is propagated the sublattice point attribute matrix SubMetri that expansion obtains _{Cnt_blank}Expression.Expansion process is shown in Fig. 5 (a), and numeral is the expansion order.

2. calculate the polysilicon layer expandable area under polysilicon minimum spacing design rule constraints

In the largest extension zone, in the scope, begin to do the expansion of " 1 " value from lead to the hole site, obtain containing the polysilicon graphics zone of this through hole at polysilicon layer.Be close to this regional white space and can when increasing through hole, expand polysilicon.So,, do the expansion of " 0 " value ripple from " 0 " value zone of " 1 " value extended boundary next-door neighbour.Merge " 1 " and be worth extended area and " 0 " value extended area, this " 0 " that merges the zone is worth the design rule of the minimum spacing of outer boundary retraction through hole and polysilicon.Obtain to expand on the polysilicon layer zone of polysilicon like this, use SubMetri _{Poly_blank}Expression.Expansion process shown in Fig. 5 (b), the expansion process of the digital polysilicon region of black matrix wrongly written or mispronounced character, the numeral of white gravoply, with black engraved characters is the expansion process of polysilicon layer white space.

3. calculate the active region layer expandable area under through hole and active region layer minimum spacing design rule constraints

In the largest extension zone, in the scope, begin to do the expansion of " 0 " value, obtain the white space of current region at active region layer from lead to the hole site.The polysilicon of expansion can not be coated with the source region, need keep the design rule of polysilicon and active area minimum spacing with active region layer, so with the border of white space bounce back through hole and active area minimum spacing design rule.Can obtain blank active area zone like this, use SubMetri _{Active_blank}Expression.Expansion process is shown in Fig. 5 (c), and numeral is the expansion order.

4. calculate the metal level expandable area under metal minimum spacing design rule constraints

In the largest extension zone, in the scope, begin to do the expansion of " 1 " value, obtain containing the metallic region of this through hole at metal level from lead to the hole site.Be close to this regional white space and can be used as expanded metal zone when increasing through hole.From " 0 " value zone of " 1 " value extended boundary next-door neighbour, do the expansion of " 0 " value.Merge " 1 " value extended area and " 0 " value extended area.During expanded metal, the metal of expansion will satisfy metal minimum spacing design rule with original metal, so with the design rule of the minimum spacing of " 0 " value border retraction metal level, obtain the expandable area of metal level, uses SubMetri _{Metal_blank}Expression.Expansion process is shown in Fig. 5 (d), and the numeral of black matrix wrongly written or mispronounced character is the expansion process of metallic region, and the numeral of white gravoply, with black engraved characters is the expansion process of metal level white space.

All subregion is made domain and operation (SubMetri _{Cnt_blank}﹠amp; SubMetri _{Poly_blank}﹠amp; SubMetri _{Active_blank}﹠amp; SubMetri _{Metal_blank}), obtain subregion SubMetri _Blank, increasing polysilicon, metal and through hole at this subregion, the image of increase will satisfy each design rule constraints.Operating result is shown in Fig. 5 (e).

Sublattice is put attribute matrix SubMetri _BlankIn the regional corresponding region of " 1 " value be expressed as polygon Polygon _Cnt, if Polygon _CntEnough can increase through hole greatly, then in the lattice point attribute matrix of via layer correspondence, increase through hole, and increase polygon Polygon at polysilicon layer and metal level _Cnt, so just finish the through hole expansion that connects polysilicon and metal.

(2) be connected with the expansion of the through hole of source region and metal

1. calculate the via layer expandable area under minimum vias spacing design rule constraints

In the largest extension zone, do " 0 " value ripple propagation operation from the property value of next-door neighbour's through hole for the position of " 0 " in via layer, obtain continuously " 0 " value zone.Should the zone inner and outer boundary retraction through hole minimum spacing design rule, obtain the zone that this layer can increase through hole.Any position increases through hole in this zone, does not violate design rule with original via layer figure.Ripple is propagated the sublattice point attribute matrix SubMetri that expansion obtains _{Cnt_blank}Expression.

2. calculate the polysilicon layer white space under polysilicon and active area minimum spacing design rule constraints

The active area of expansion can not be covered by polysilicon graphics, need keep the design rule of polysilicon and active area minimum spacing with active area.

In the largest extension zone, begin to do the expansion of " 0 " value at polysilicon layer from lead to the hole site, obtain the continuous white space that polysilicon layer begins from the through hole position.With the design rule of " 0 " value border retraction polysilicon and active area minimum spacing, the zone SubMetri that obtains _{Poly_blank}Expression increases active area and can not cause violating design rule with polysilicon in this zone, can not change the circuit logic function.

3. calculate the active area expandable area under active area minimum spacing design rule constraints

In the largest extension zone, in the scope, begin to do the expansion of " 1 " value, obtain containing the continuous active area graphics field of this through hole at active area from lead to the hole site.

White space can be expanded active area when increasing through hole.From " 0 " value of " 1 " value extended boundary next-door neighbour, do the expansion of " 0 " value ripple.Merge " 1 " value extended area and " 0 " value extended area, with the design rule of " 0 " value border retraction through hole and active area minimum spacing.The zone deletion on Implant layer border will be exceeded in this zone.On active area, obtain like this expanding the active area zone, use SubMetri _{Active_blank}Expression.

4. calculate the metal level expandable area under metal minimum spacing design rule constraints

In the largest extension zone, in the scope, begin to do the expansion of " 1 " value, obtain containing the metal level zone of this through hole at metal level from lead to the hole site.Be close to this regional white space and can be used as expanded metal zone when increasing through hole.From " 0 " value zone of " 1 " value extended boundary next-door neighbour, do the expansion of " 0 " value.Merge " 1 " value extended area and " 0 " value extended area.Metal and original metal of expansion will satisfy metal minimum spacing design rule, so will " 0 " be worth the bounce back design rule of minimum spacing of metal level of border, obtain the expandable area of metal level, use SubMetri _{Metal_blank}Expression.

All subregion is made domain and operation (SubMetri _{Cnt_blank}﹠amp; SubMetri _{Poly_blank}﹠amp; SubMetri _{Active_blank}﹠amp; SubMetri _{Metal_blank}), obtain subregion SubMetri _Blank, increasing active area, metal and through hole at this subregion, the image of increase will satisfy each design rule constraints.

Sublattice is put attribute matrix SubMetri _BlankIn the regional corresponding region of " 1 " value be expressed as polygon Polygon _Active, if Polygon _ActiveEnough can increase through hole greatly, then in the lattice point attribute matrix of through hole correspondence, increase through hole, increase polygon Polygon at active area and metal level _Cnt, so just finish the through hole expansion that is connected with source region and metal.

Claims (1)

1. one kind increases the method that standard cell through holes promotes chip yield, may further comprise the steps:

1) will pass through Stein algorithm cycle calculations after the chip design regular integerization, obtain the highest common factor λ of design rule; With λ is base unit, standard block polysilicon layer, active region layer, via layer and metal level domain evenly are divided into rectangular node, no figure then is provided with the lattice point attribute for " 0 " on the lattice point, has figure that the lattice point attribute then is set on the lattice point and is " 1 ", constitutes each layer lattice point attribute matrix;

2) do the ripple propagation operation from the set point of domain: from the set point of lattice point attribute matrix, up and down, left and right four direction searches the lattice point that equals this set point property value, to around expansion till the lattice point that does not equal this set point property value;

Domain lattice point attribute matrix is done and operated: the corresponding property value of each lattice point of domain lattice point attribute matrix of two identical sizes is done the logical and operation respectively, rule equals " 0 " for " 0 " and " 0 ", " 0 " equals " 0 " with " 1 ", and " 1 " equals " 0 " " 1 " with " 0 " and equals " 1 " with " 1 ";

3) through-hole type of division via layer: do the ripple propagation operation of lattice point attribute for " 1 " at polysilicon layer, do the ripple propagation operation of lattice point attribute at active region layer for " 0 ", twice wave-propagation results carried out " with computing ", there is " 1 " in " with computing " result's sub-attribute matrix, judges that through hole is the through hole that connects polysilicon and metal; Do the ripple propagation operation of lattice point attribute at polysilicon layer for " 0 ", do the ripple propagation operation of lattice point attribute at active region layer for " 1 ", twice wave-propagation results carried out " with computing ", there is " 1 " in " with computing " result's sub-attribute matrix, judges that through hole is the through hole that is connected with source region and metal;

Calculating via-first power: the through hole that the sub-attribute matrix of via layer through-hole type partition process is equated is labeled as and linked hole, the number of calculating " 1 " in the sub-attribute matrix with and the inverse of linked hole number product, obtain via-first power;

4) weigh according to via-first, under the chip design rule constrain, calculate the subregion expanded of the through hole of connection polysilicon and metal: propagate, after polysilicon layer elder generation does the propagation of " 1 " ripple, do the propagation of " 0 " ripple at via layer work " 0 " ripple, do the propagation of " 0 " ripple, do work " 0 " ripple propagation of " 1 " ripple propagation back in metal level elder generation at active region layer, each subwave propagation operation result is done and operates, and acquisition can be expanded subregion;

Weigh according to via-first, under the chip design rule constrain, calculating is connected with the subregion expanded of the through hole of source region and metal: propagate, propagate at polysilicon layer work " 0 " ripple, do the propagation of " 0 " ripple at via layer work " 0 " ripple after active region layer elder generation work " 1 " ripple is propagated, do work " 0 " ripple propagation of " 1 " ripple propagation back in metal level elder generation, each subwave propagation operation result is done and operates, and acquisition can be expanded subregion;

In the subregion expanded of through hole, evenly increase through hole, in corresponding domain layer, increase domain according to the chip design rule, and revision figure lattice point attribute matrix, the increase of standard cell through holes finished.

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