CN101825484A - Malfunction detection method of incremental encoder - Google Patents
Malfunction detection method of incremental encoder Download PDFInfo
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- CN101825484A CN101825484A CN201010301223A CN201010301223A CN101825484A CN 101825484 A CN101825484 A CN 101825484A CN 201010301223 A CN201010301223 A CN 201010301223A CN 201010301223 A CN201010301223 A CN 201010301223A CN 101825484 A CN101825484 A CN 101825484A
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Abstract
The invention relates to a malfunction detection method of an incremental encoder, which belongs to the malfunction detection field of the encoder, and solves the problems of the prior art that the non-wire-break malfunction of the incremental encoder cannot be detected. An electric pulse signal A and an electric pulse signal B of the incremental encoder, phase difference of which is 90 degrees, are exclusive or to obtain a synchronic clock signal Clock, circuit output states Q2 and Q1 of two JK triggers FF2 and FF1 which are triggered by two rising edges are determined according to the state of the electric pulse signals A and B at the rising edge time of every two adjacent periods of the Clock, and the malfunction of the incremental encoder is judged according to the output state Q2 and Q1. The method also comprises the detection of a Z pulse signal of the incremental encoder: a Z pulse signal is adopted to preset a cascaded counter so as to count the pulse number which is outputted by the synchronic clock signal Clock when incremental encoder rotates a circle, and the malfunction of the Z pulse signal is judged according to the overflow of the cascaded counter. The method is applicable to the malfunction detection of the incremental encoder.
Description
Technical field
The present invention relates to a kind of fault detection method of incremental encoder, belong to the fault detect field of scrambler.
Background technology
Scrambler at present commonly used has incremental encoder and absolute type encoder, incremental encoder because cost is low than the applied range of absolute type encoder many.The photoelectric code disk of incremental encoder is by plating the lighttight metallic film of one deck on the glass disk, making equidistant printing opacity and the light tight alternate striped of circumference then on metallic film makes, when photoelectric code disk rotates, the striped of printing opacity has light to see through, lighttight striped dull thread sees through, consequent light and dark signal is received by light activated element, converts electric impulse signal output again to.The code-disc of incremental encoder is carved two code channels usually, the corresponding light-emitting component of each code channel and a photosensitive receiving element, two code channels have the uniformly-spaced gratings strips streakline of similar number, when the photoelectric code disk operate as normal, A, the B electric impulse signal of exportable phase phasic difference 90 degree, scrambler whenever rotates a circle a Z pulse signal can be provided simultaneously, as shown in Figure 1.
When incremental encoder is used for the rotating speed of motor measurement, it is connected with motor coaxle, within a set time section of motor rotation,, can calculates rotating speed of motor by the A of inquiry scrambler output, the number of B electric impulse signal.But when scrambler breaks down, lose as electric impulse signal A or B, then can cause and test the speed inaccurately, this very likely makes motor that " driving " phenomenon takes place.Thus the duty of scrambler is monitored very necessity,, in time adjust the duty of controller, guarantee equipment safety operation with when fault takes place.The fault detect of in the prior art incremental encoder being carried out mainly is at burn out detection, as shown in Figure 2.As signal A, the B of photoelectric code disk output, when Z does not have broken string, because its signal is a Transistor-Transistor Logic level, can't conducting voltage stabilizing diode D1, triode Q1 ends; As A, B, when broken string appears in Z, voltage stabilizing diode conducting under the effect of 12V power supply, triode Q1 conducting; Judge with this whether scrambler disconnection fault occurs.
Because the work under bad environment of electric system, incremental encoder also the non-disconnection fault that underlying cause causes occurs through regular meeting:
One, the code channel of photoelectric code disk covers by chemical corrosion or by dirt, causes at line just often the A that scrambler is exported, B electric impulse signal excalation;
Two, when photoelectric code disk axle and the serious eccentric error of motor shaft installation appearance, the A that causes, B electric impulse signal disappearance.
The incremental encoder fault that these two kinds of reasons cause usually is difficult to be found by the user that it can make the detection to motor speed error occur, thereby reduces the performance of total system.
Summary of the invention
The fault detection method that the purpose of this invention is to provide a kind of incremental encoder, it has solved the problem that prior art can not detect the non-disconnection fault of incremental encoder.
The fault detection method of incremental encoder:
Detection to the electric impulse signal A and the B of incremental encoder: with the electric impulse signal A of 90 ° of the phasic differences mutually of exporting under two code channel normal operating conditionss of incremental encoder and B XOR mutually, obtain synchronizing clock signals Clock, in the rising edge moment of every adjacent periods of described synchronizing clock signals Clock, the state of electric impulse signal A and B circulates between A=1, B=0 and A=0, B=1;
The circuit output state Q2Q1 that defines JK flip-flop FF2, the FF1 of two rising edges triggerings is:
S
0=00, the normal state preface;
S
1=01, the normal state preface;
S
2=10, the fault case preface;
S
3=11, the don't-care state preface;
In every adjacent two cycles with synchronizing clock signals Clock, the rising edge in previous cycle constantly, the opposite state of electric impulse signal A and B is by the S of Q2Q1
0=00 circuit state output; In the rising edge moment of back one-period, the opposite state of electric impulse signal A and B is by the S of Q2Q1
1=01 circuit state output, and the rising edge of back one-period constantly, the state of electric impulse signal A and the B previous cycle rising edge contravariant of the state of A and B constantly of respectively doing for oneself;
When the circuit output state of Q2Q1 at S
0=00 and S
1Circulation time between=01, electric impulse signal A, the B non-fault of judgement incremental encoder; When the circuit output state of Q2Q1 not at S
0=00 and S
1Circulation time between=01 is by the S of Q2Q1
2=10 circuit state output judges that A, the B signal of incremental encoder breaks down.
The present invention also provides the fault detection method of another kind of incremental encoder, be detection:, obtain synchronizing clock signals Clock with the electric impulse signal A of 90 ° of the phase phasic differences of exporting under two code channel normal operating conditionss of incremental encoder and B XOR mutually to the Z pulse signal of incremental encoder; Adopt the Z pulse signal that the cascade counter is carried out initialize operation, the preset count value is whenever rotate a circle umber of pulse poor of synchronizing clock signals Clock output of the maximum count value of cascade counter and incremental encoder, in the rotary course of incremental encoder, adopt the cascade counter that synchronizing clock signals Clock is counted, and incremental encoder whenever rotates a circle, the Z pulse signal carries out an initialize operation to the cascade counter, do not have when the cascade rolling counters forward and to overflow, judge Z pulse signal non-fault; When the cascade rolling counters forward is overflowed, judge the Z pulse signal disappearance of incremental encoder, break down.
Advantage of the present invention is:
The inventive method is by the electric impulse signal A to incremental encoder, the detection of the disappearance of B and Z pulse signal, realize judgement to the broken string or the non-disconnection fault of incremental encoder, to a certain disconnection fault mutually that occurs between incremental encoder and the control circuit, perhaps because the eccentric shaft that the long-term use of incremental encoder causes, the fault that the disappearance of the pulse signal that the code channel corrosion causes causes, can detect accurately, and realize that circuit is simple, being particularly suitable for realizing with programmable logic device (PLD) such as CPLD or FPGA, is useful the replenishing of in the prior art disconnection fault being detected.
Description of drawings
Fig. 1 is A, B, the Z pulse signal figure of incremental encoder output; Fig. 2 is the disconnection fault testing circuit figure of existing incremental encoder; Fig. 3 is the oscillogram of electric impulse signal A and B and synchronizing clock signals Clock under the incremental encoder normal operating conditions, 00 section of the 4th curve circuit output state S corresponding to Q2Q1 among the figure
0, 01 section circuit output state S corresponding to Q2Q1
1Fig. 4 is the conversion of circuit output state and the switch condition figure thereof of the inventive method; Fig. 5 is the realization circuit diagram of embodiment two described detection methods of the present invention; Fig. 6 is the circuit diagram that embodiment two and three described detection methods of the present invention realize simultaneously; Fig. 7 is the electric impulse signal A and the B The simulation experiment result figure just often of incremental encoder; Fig. 8 is that the electric impulse signal A of incremental encoder is normal, the The simulation experiment result figure when B is fixed as high level output; Fig. 9 is that the electric impulse signal A of incremental encoder is normal, the The simulation experiment result figure when B is fixed as low level output; Figure 10 is that the electric impulse signal A of incremental encoder is normal, the The simulation experiment result figure the during output of B excalation; Figure 11 is the realization circuit diagram of embodiment four described detection methods of the present invention; Emulation experiment figure when Figure 12 normally exports for the Z pulse signal of incremental encoder; Emulation experiment figure when Figure 13 loses for the Z pulse signal of incremental encoder.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 3, present embodiment is the detection to the electric impulse signal A and the B of incremental encoder: with the electric impulse signal A of 90 ° of the phasic differences mutually of exporting under two code channel normal operating conditionss of incremental encoder and B XOR mutually, obtain synchronizing clock signals Clock, in the rising edge moment of every adjacent periods of described synchronizing clock signals Clock, the state of electric impulse signal A and B circulates between A=1, B=0 and A=0, B=1;
The circuit output state Q2Q1 that defines JK flip-flop FF2, the FF1 of two rising edges triggerings is:
S
0=00, the normal state preface;
S
1=01, the normal state preface;
S
2=10, the fault case preface;
S
3=11, the don't-care state preface;
In every adjacent two cycles with synchronizing clock signals Clock, the rising edge in previous cycle constantly, the opposite state of electric impulse signal A and B is by the S of Q2Q1
0=00 circuit state output; In the rising edge moment of back one-period, the opposite state of electric impulse signal A and B is by the S of Q2Q1
1=01 circuit state output, and the rising edge of back one-period constantly, the state of electric impulse signal A and the B previous cycle rising edge contravariant of the state of A and B constantly of respectively doing for oneself;
When the circuit output state of Q2Q1 at S
0=00 and S
1Circulation time between=01, electric impulse signal A, the B non-fault of judgement incremental encoder; When the circuit output state of Q2Q1 not at S
0=00 and S
1Circulation time between=01 is by the S of Q2Q1
2=10 circuit state output judges that A, the B signal of incremental encoder breaks down.
The principle of the inventive method:
The output phase of electric impulse signal A, the B of normal encoder differs 90 degree, with A and B XOR mutually, obtains synchronizing clock signals Clock, and is shown in Figure 3, after the rising edge of first synchronizing clock signals Clock, and A=1, B=0; After the rising edge of second synchronizing clock signals Clock, A=0, B=1, the rest may be inferred, after the rising edge of follow-up synchronizing clock signals Clock, the state of A, B is at A=1, and B=0 and A=0 circulate between the B=1, feature can be judged the electric impulse signal A of incremental encoder, the disappearance of B thus, if A and the equal negate of B after the rising edge of each synchronizing clock signals Clock, circuit non-fault then, on the contrary then fault has appearred in circuit.
Embodiment two: below in conjunction with Fig. 3, Fig. 4 and Fig. 5 present embodiment is described, the difference of present embodiment and embodiment one is that electric impulse signal A is ahead of 90 ° in the phase place of B, the S of Q2Q1
0=00 circuit output state is corresponding to the state of electric impulse signal A=0, B=1, the S of Q2Q1
1=01 circuit output state is corresponding to the state of electric impulse signal A=1, B=0.
Design process to the failure detector circuit of realizing detection method of the present invention is as follows,
The JK flip-flop FF2 and the FF1 that at first adopt two rising edges to trigger, its circuit output state Q2Q1 has four kinds of states 00,01,10 and 11.
The definition circuit state:
S0=00 is the normal state preface;
S1=01 is the normal state preface;
S2=10 is the fault case preface;
S3=11 is the don't-care state preface, and circuit can not jump to this state.
Definition circuit output: Fault=0, the electric impulse signal A of incremental encoder and B are non-fault output; Fault=1, the electric impulse signal A of incremental encoder and B are for there being fault output.
By the above-mentioned analytic process Fig. 4 that draws,, obtain Q then again according to Fig. 4
2 N+1Q
1 N+1The next state Karnaugh map, as shown in table 1, the XX/X in the table 1 represents that this concrete numerical value and the function of circuit are irrelevant.
Table 1 Q
2 N+1Q
1 N+1/ Fault
Realize the circuit diagram of the inventive method at last according to above analytic process design, as shown in Figure 5.
Embodiment three: below in conjunction with Fig. 6 Figure 10 present embodiment is described, the difference of present embodiment and embodiment one is that electric impulse signal A lags behind 90 ° in the phase place of B, the S of Q2Q1
0=00 circuit output state is corresponding to the state of electric impulse signal A=1, B=0, the S of Q2Q1
1=01 circuit output state is corresponding to the state of electric impulse signal A=0, B=1.
The realization circuit of present embodiment repeats embodiment two on design concept design process gets final product, and the whole failure detector circuit figure that embodiment two and three detection method is realized simultaneously as shown in Figure 6.Electric impulse signal A by the scrambler generation, B phase XOR, obtain the pulse output map of the required clock signal C lock of failure detector circuit, the JK flip-flop of utilizing 4 rising edges to trigger realizes state machine circuit, this circuit is with electric impulse signal A, the B signal as output signal, detects A and is ahead of B or the preceding encoder fault when A of B ultrasonic with fault-signal Fault as input signal.Work as A, when occurring the pulse disappearance in the B pulse signal, when promptly scrambler broke down, the Fault signal was 1, otherwise was 0.
Fig. 7 Figure 10 is the The simulation experiment result figure of normal or certain phase fault situation of electric impulse signal A and B, and when Fig. 7 represented that electric impulse signal A and B are normal output, the Fault signal was continuously low level, represents the incremental encoder non-fault; Fig. 8 represents that electric impulse signal A is normal, and B breaks down (no pulse is fixed as high level), and the Fault signal indication becomes high level and continues after detecting the fault of incremental encoder, and fault has appearred in the expression incremental encoder; Fig. 9 represents that electric impulse signal A is normal, and B breaks down (no pulse is fixed as low level), and the Fault signal indication becomes high level and continues after detecting the fault of incremental encoder, and fault has appearred in the expression incremental encoder; Figure 10 represents that electric impulse signal A is normal, and B breaks down (due the 4th high level pulse disappearance), and the Fault signal indication becomes high level and continues after detecting the fault of incremental encoder, and fault has appearred in the expression incremental encoder.
Confirm by The simulation experiment result, the inventive method can fast detecting goes out the miss fault (comprising disconnection fault) of electric impulse signal A, the B of incremental encoder, malfunction becomes high level output by the Fault signal of circuit by former low level, for host computer provides failure message.
Embodiment four: below in conjunction with Fig. 6, Figure 11-Figure 13 present embodiment is described, present embodiment is the detection to the Z pulse signal of incremental encoder: the detection method to the Z pulse signal of incremental encoder is:
With the electric impulse signal A of 90 ° of the phase phasic differences of exporting under two code channel normal operating conditionss of incremental encoder and B XOR mutually, obtain synchronizing clock signals Clock; Adopt the Z pulse signal that the cascade counter is carried out initialize operation, the preset count value is whenever rotate a circle umber of pulse poor of synchronizing clock signals Clock output of the maximum count value of cascade counter and incremental encoder, in the rotary course of incremental encoder, adopt the cascade counter that synchronizing clock signals Clock is counted, and incremental encoder whenever rotates a circle, the Z pulse signal carries out an initialize operation to the cascade counter, do not have when the cascade rolling counters forward and to overflow, judge Z pulse signal non-fault; When the cascade rolling counters forward is overflowed, judge the Z pulse signal disappearance of incremental encoder, break down.
Present embodiment can be united use with embodiment one, two or three, detects when realizing a-signal, B signal to incremental encoder and Z signal.
At Z pulse signal fault,, can detect separately according to the described method design circuit of present embodiment as broken string or because of the signal deletion that code channel corrodes or the dirt covering causes.The electric impulse signal A of different incremental encoders outputs or the umber of pulse difference of B, the design illustrates the fault detection method of Z pulse signal with 100 pulses/transfer example to.When the umber of pulse of electric impulse signal A or B was 100 pulses/commentaries on classics, the umber of pulse of synchronizing clock signals Clock was 200 pulse/commentaries on classics.The failure detector circuit of design Z pulse signal as shown in figure 11, this circuit application 3 16 system counters 74163 carry out cascade, to counter to preset number be 111100111000, be metric 3896, with synchronizing clock signals Clock among Fig. 6 as being counted pulse, with the non-signal of Z pulse signal as 74163 presetting pulse, the rising edge of each synchronizing clock signals Clock makes counter add counting, when the Z pulse signal just often, incremental encoder whenever rotates a circle, and the Z pulse is predisposed to counter to determine the good number that presets, and counter can not overflow, be that the Faultz signal remains low level always, as shown in figure 12; When the Z pulse signal is lost, initialize operation does not take place, this hour counter can overflow, and a high level pulse appears in the Faultz signal, and as shown in figure 13, this high level pulse is issued processors such as MCU as Z pulse signal indicating fault, waits processing.The number that presets of cascade counter needs to do different settings according to the difference of incremental encoder output pulse.
Among Figure 12, the Z pulse signal is normally exported, so the Faultz signal is continuously low level, and expression incremental encoder non-fault; Among Figure 13, Z pulse signal disappearance, the Faultz signal high level pulse occurs in the back constantly in Z pulse signal disappearance, and the expression incremental encoder has fault, and the place of losing of Z pulse signal is represented in the position of X indication among the figure.
Claims (4)
1. the fault detection method of an incremental encoder is characterized in that:
Detection to the electric impulse signal A and the B of incremental encoder: with the electric impulse signal A of 90 ° of the phasic differences mutually of exporting under two code channel normal operating conditionss of incremental encoder and B XOR mutually, obtain synchronizing clock signals Clock, in the rising edge moment of every adjacent periods of described synchronizing clock signals Clock, the state of electric impulse signal A and B circulates between A=1, B=0 and A=0, B=1;
The circuit output state Q2Q1 that defines JK flip-flop FF2, the FF1 of two rising edges triggerings is:
S0=00, the normal state preface;
S1=01, the normal state preface;
S2=10, the fault case preface;
S3=11, the don't-care state preface;
In every adjacent two cycles with synchronizing clock signals Clock, in the rising edge in the previous cycle moment, the state that electric impulse signal A and B are opposite is exported by the circuit state of the S0=00 of Q2Q1; The rising edge of back one-period constantly, the opposite state of electric impulse signal A and B is by the circuit state output of the S1=01 of Q2Q1, and the rising edge of back one-period constantly, the state of electric impulse signal A and the B previous cycle rising edge contravariant of the state of A and B constantly of respectively doing for oneself;
When circuit output state circulation time between S0=00 and S1=01 of Q2Q1, judge electric impulse signal A, the B non-fault of incremental encoder; When the circuit output state of Q2Q1 circulation time between S0=00 and S1=01 not, the circuit state output of the S2=10 by Q2Q1 judges that A, the B signal of incremental encoder breaks down.
2. the fault detection method of incremental encoder according to claim 1, it is characterized in that: electric impulse signal A is ahead of 90 ° in the phase place of B, the circuit output state of the S0=00 of Q2Q1 is corresponding to the state of electric impulse signal A=0, B=1, and the circuit output state of the S1=01 of Q2Q1 is corresponding to the state of electric impulse signal A=1, B=0.
3. the fault detection method of incremental encoder according to claim 1, it is characterized in that: electric impulse signal A lags behind 90 ° in the phase place of B, the circuit output state of the S0=00 of Q2Q1 is corresponding to the state of electric impulse signal A=1, B=0, and the circuit output state of the S1=01 of Q2Q1 is corresponding to the state of electric impulse signal A=0, B=1.
4. the fault detection method of an incremental encoder is characterized in that: to the detection of the Z pulse signal of incremental encoder:
With the electric impulse signal A of 90 ° of the phase phasic differences of exporting under two code channel normal operating conditionss of incremental encoder and B XOR mutually, obtain synchronizing clock signals Clock; Adopt the Z pulse signal that the cascade counter is carried out initialize operation, the preset count value is whenever rotate a circle umber of pulse poor of synchronizing clock signals Clock output of the maximum count value of cascade counter and incremental encoder, in the rotary course of incremental encoder, adopt the cascade counter that synchronizing clock signals Clock is counted, and incremental encoder whenever rotates a circle, the Z pulse signal carries out an initialize operation to the cascade counter, do not have when the cascade rolling counters forward and to overflow, judge Z pulse signal non-fault; When the cascade rolling counters forward is overflowed, judge the Z pulse signal disappearance of incremental encoder, break down.
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