CN101807922A - Sampling hold circuit for improving performance by adopting compensation way - Google Patents
Sampling hold circuit for improving performance by adopting compensation way Download PDFInfo
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Abstract
The invention discloses a sampling hold circuit for improving the performance by adopting a compensation way, comprising a sampling unit and a compensation unit, wherein the compensation unit comprises a compensation power supply, a compensation capacitor, a control switch, a control clock and the like. During compensation, an error compensation voltage can be changed by setting and changing the corresponding value of the compensation power supply or the compensation capacitor, the compensation range and the compensation step precision are easily controlled, and the invention has the characteristics of convenient implementation, flexibility and adjustability. In the invention, precision compensation is carried out on a circuit at a sampling holding stage, a circuit compensation process and a signal acquiring process are separated, the precision compensation on the circuit is finished under the condition of not remarkably influencing the circuit speed, and a high-speed and high-precision open loop type sampling hold circuit is realized.
Description
Technical field
The present invention relates to the sampling hold circuit that uses in a kind of analog to digital converter.
Background technology
Along with electronic technology and development of computer, the mankind have entered the integrated epoch of electronic system now, and the digital system operating frequency of main flow more than GHz, is therefore had higher requirement to the speed and the precision of analog to digital converter (ADC).But speed and precision are a pair of contradiction, be difficult at present and make in the ADC product that two class indexs all obtain high-performance, therefore, High Performance ADC respectively to high-speed, in low Precision A C and low speed, two main aspects development of high-precision adc, wherein high-speed ADC can further be subdivided into full Parallel ADC, interpolation type ADC, folded interpolating type ADC and multichannel ADC etc.Signal sampling hold circuit is an indispensable part in the High Performance ADC, can significantly reduce the velocity accuracy requirement to the ADC element circuit.
At present, sampling hold circuit mainly is based on the closed loop sampling with high precision holding circuit of high-gain amplifier with based on the open loop type high-speed sampling holding circuit of capacitance-resistance RC circuit.There is following problem in open loop type high-speed sampling holding circuit: 1, since circuit working in open loop situations to satisfy the requirement that high speed signal is handled, be difficult to implement effective precision control or loop control, cause sampling precision very low, usually be difficult to surpass 6 bit resolutions, and along with the raising precise decreasing of circuit work frequency; 2, concerning the high-speed sampling holding circuit, the error compensation of precision is caused adverse effect to the circuit speed bandwidth easily, so the high-speed sampling holding circuit is generally refused error compensation or is implemented simple error compensation, simple compensation is generally based on virtual (dummy) compensation transistor, typical structure such as Fig. 1, shown in Figure 2, to absorb or to offset the electric charge injection of sampling transistor, the clock feedthrough equal error, it is a kind of passive compensation, and the design size of virtual (dummy) compensation transistor is in case determine, bucking voltage is also fixing, the bucking voltage that simple error compensation mode provides is generally less, and it is unadjustable, its compensation effect with will not error compensation compare improve few, practicality is not strong, be difficult to satisfy the required precision of high speed (MHz operating frequency) ADC, especially ultrahigh speed (GHz operating frequency) ADC of medium accuracy (6-12 position); 3, concerning the high-speed sampling holding circuit, input signal for the different operating frequency, varying in size of circuit error, error range between millivolt level to ten millivolt level, objectively need the error compensation of different sizes greatly, and existing simple compensation technology can only provide fixed compensation voltage, Adjustable Error scope and Adjustable Error precision step-length can not be provided, be difficult to adopt the compensation level that varies in size, thereby flexibility be relatively poor according to different error requirements, compensation range is little, and applicability is not strong yet.
Fig. 1 has provided existing first kind of sampling hold circuit that adopts compensation way.This circuit is by sampling transistor M1, sampling capacitance C
S, and virtual (dummy) compensation transistor M2, clock Ph1 and clock Ph2 form.The design size of transistor M2 is reference with transistor M1 usually, equates with transistor M1 or proportional (getting W/2 as width), and clock Ph1 is opposite with clock Ph2 sequential phase place.In sampling maintenance process, transistor M1 electric charge injections etc. are to the error effect of signal output part, with the error effect to signal output part such as compensation transistor M2 electric charge injection, the two error size is roughly the same or close, direction is opposite, thereby offsets or reduced the sampling error that sampling switch transistor M1 causes.In like manner, clock Ph1 passes through the error effect of transistor M2 to signal output part by the error effect of transistor M1 to signal output part with clock Ph2, and the two error size is roughly the same or close, direction is opposite, thereby offsets or reduced the influence of sampling clock to signal output part.This employing virtual (dummy) compensation transistor is a kind of rough error counteracting method to the method that sampling hold circuit carries out error compensation, be applicable to that sample frequency is lower, the sampling error compensation that error effect is less, when higher or other factors caused sampling error big when sample frequency, this error compensating method often was difficult to provide the error compensation of enough sizes.
Fig. 2 has provided existing second kind of sampling hold circuit that adopts compensation way.It can be considered the improvement of sampling hold circuit shown in Figure 1.Compare with Fig. 1 circuit, this circuit has increased the virtual compensation transistor M3 of signal input part, and compensation transistor M3 and compensation transistor M2 equal and opposite in direction, and the control clock is also identical.The compensation transistor M3 that increases can partial offset or is reduced the voltage error that factors such as sampling transistor M1 and sampling clock produce at signal input part, thereby improves the precision of sampling hold circuit indirectly.Circuit shown in Figure 2 slightly improves on the basis of Fig. 1 circuit, but in general, above-mentioned two kinds are adopted its compensation method essence of sampling hold circuit of compensation techniques identical, and the effect of error compensation also is more or less the same, and still are difficult to satisfy sampling error requirement to compensation when big.
Above-mentioned two kinds of sampling hold circuits that adopt compensation technique, though the circuit precision is increased, but still belong to the category of simple compensation, compensation range is limited, accuracy compensation is less, and flexibility is not strong, can't satisfy the more requirement of the high-speed ADC of high accuracy (more than 6).
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of and can satisfy simultaneously at a high speed and the open loop type sampling hold circuit of high-precision requirement.
Technical solution of the present invention is: adopt compensation way to improve the sampling hold circuit of performance, comprise by transistor M1 and capacitor C
SThe sampling unit that constitutes also comprises compensating unit, the source terminal reception sampled signal of transistor M1, the grid termination clock control signal Ph1 of transistor M1, the drain electrode termination capacitor C of transistor M1
SAn end, capacitor C
SAnother termination reference potential, the drain electrode end of transistor M1 and capacitor C
SCommon port as the output of sampling unit, described compensating unit comprises building-out capacitor C1, offset supply VS1, switch S 1, switch S 2 and clock control signal Ph1 and Ph2, the output voltage V of offset supply VS1
CBe connected to reference potential through switch S 2, switch S 1, one of building-out capacitor C1 is connected to the common port of switch S 1 and switch S 2, and the other end of building-out capacitor C1 is connected to the output of sampling unit; Switch S 1 is controlled by clock control signal Ph1, switch S 2 is controlled by the inverted signal Ph2 of clock control signal Ph1, sample phase, and clock control signal Ph1 is effective, transistor M1 conducting, switch S 1 closure, switch S 2 disconnects the maintenance stage, clock control signal Ph2 is effective, transistor M1 ends, and switch S 1 disconnects switch S 2 closures.
The output voltage V of described offset supply VS1
C, building-out capacitor C1 appearance value C
CAnd sampling capacitance C
SAppearance value C
0Offset voltage V with circuit
OSSatisfy relational expression: C
CV
C/ (C
0+ C
C)=V
OS, V wherein
OSOutput voltage and unequal all error voltages of input voltage for the treatment of sampled signal for the output that causes sampling unit.
The appearance value C of described building-out capacitor C1
CBe fixed value or variable value.
The output voltage V of described offset supply VS1
CBe fixed value or variable value.
The present invention's advantage compared with prior art is: sampling hold circuit of the present invention is in signal maintenance process, by changing building-out capacitor C
C, or change bucking voltage V
CCan both change error compensation to sampling hold circuit, described compensation method is regulated flexible, the compensation range broad, overcome the fixing deficiency of bucking voltage of existing simple compensation technology, can in the scope of broad, approach the real voltage error of circuit, improve the precision of sampling hold circuit as far as possible, and because this compensation technique is convenient adjustable, help according to different circuit error condition, provide in real time or change error compensation, constantly to approach the true error of circuit sampling hold circuit, realize the optimization compensation of sampling hold circuit, further improve the precision of circuit.Because error compensation is only implemented in the signal maintenance stage of sampling hold circuit, do not influence the high-speed sampling of input signal is followed the tracks of, therefore the bandwidth Design of sampling hold circuit can suitably be separated and independent optimization with the compensating circuit design, help overcoming because the contradiction that speed that the microelectronic technique condition restriction is brought and precision retrain mutually realizes high-speed, the high-precision double goal of sampling hold circuit.
Description of drawings
Fig. 1 is existing first kind of sampling hold circuit schematic diagram that adopts compensation way;
Fig. 2 is existing second kind of sampling hold circuit schematic diagram that adopts compensation way;
Fig. 3 is the circuit theory diagrams of sampling hold circuit of the present invention;
Fig. 4 is a kind of circuit theory diagrams of variable value for building-out capacitor C1 in the circuit shown in Figure 3;
Fig. 5 is a kind of circuit theory diagrams of variable value for offset supply VS1 in the circuit shown in Figure 3;
Fig. 6 is the concrete application circuit schematic diagram of first kind of circuit shown in Figure 3;
Fig. 7 is the concrete application circuit schematic diagram of second kind of circuit shown in Figure 3.
Embodiment
As shown in Figure 3, sampling hold circuit of the present invention comprises sampling unit 32 and compensating unit 30, and wherein sampling unit 32 comprises sampling switch M1, main sampling capacitance C
SAnd clock Ph1, compensating unit 30 comprises building-out capacitor C1, offset supply VS1, switch S 1, switch S 2, and clock Ph1 and Ph2.
The pole plate of building-out capacitor C1 directly is connected with the signal output part 11 (also being the signal output part of sampling hold circuit simultaneously) of sampling unit 32, another pole plate 12 or be connected with reference potential or pass through switch S 2 by switch S 1 and be connected the output voltage V of offset supply VS1 with the signal output part 13 of offset supply VS1
CBe delivered to the signal output part 11 of sampling hold circuit by building-out capacitor C1.The output voltage V of offset supply VS1
CBe bucking voltage V
C, voltage is fixed value or variable value, but both Discrete Change also can change continuously.The capacitance of building-out capacitor C1 is fixed value or variable value, but both Discrete Change also can change continuously.
As shown in Figure 3, in the sample phase of sampling hold circuit, clock Ph1 is a high level, transistor M1 conducting and switch S 1 closure, and clock Ph2 is a low level, control switch S2 disconnects, at this moment building-out capacitor C1 and main sampling capacitance C
SCommon is sampling capacitance, and input signal is sampled on the public pole plate of two electric capacity simultaneously, the output voltage conductively-closed of offset supply VS1 thereby signal output part 11 is not exerted an influence.Because output voltage V
OUTBe subjected to the influence of non-ideal factors such as clock effect, electric charge injection, electric charge leakage, certainly exist sampling error, can calculate output voltage at this moment:
V in the following formula
OUT(Ph1) be sampling and outputting voltage, C
GdBe the grid of transistor M1 and the parasitic capacitance of drain electrode, C
0Be main sampling capacitance C
SCapacitance, C
CBe the capacitance of building-out capacitor C1, C
ABe main sampling capacitance C
SWith the capacitance sum of building-out capacitor C1, R
ONBe the conducting resistance of transistor M1, V
CLK(Ph1) for transistor M1 by the high level voltage that is closed into the clock Ph1 when disconnecting, V
INOutside sampling input voltage when (Ph1) closing for transistor M1, V
OTHERFor removing first of following formula, other voltage error outside second error of listing, promptly electric charge leaks, electric charge injects, kick back the voltage error that reasons such as noise, circuit noise, high frequency distortion cause, V
OSFor causing output voltage V in the following formula
Out(Ph1) with input voltage V
IN(Ph1) summation of unequal all error voltages, be the lumped voltage offset error, comprise that low-pass filtering distortion, clock jitter, clock feedthrough, electric charge injection, circuit parasitic effect, electric charge leak, kick back all source of errors that a variety of causes such as noise, circuit noise cause.Especially, when the operating frequency (MHz～ghz band) of sampling hold circuit is higher, sampling capacitance value C
A(fF magnitude) is less, and the error effects that second clock effect causes in the following formula is obvious, and experiment shows that for the following technology of typical 0.18um, error voltage adopts the simple compensation mode to be difficult to success up to 20mV～80mV.
As shown in Figure 3, in the maintenance stage of sampling hold circuit, transistor M1 ends, and switch S 1 disconnects switch S 2 closures, building-out capacitor C1 and main sampling capacitance C
SSeries connection, building-out capacitor C1 is a building-out capacitor, the output voltage V of offset supply VS1
CBy building-out capacitor C1 and main sampling capacitance C
SAfter the series connection dividing potential drop, act on signal output part 11, the voltage error of compensating sampling holding circuit can calculate output voltage at this moment:
V in the following formula
OUT(Ph2) for keeping output voltage.At sampling and outputting voltage V
OUT(Ph1) on the basis, increase suitable error compensation voltage
To offset offset voltage V
OSThereby, make the maintenance output voltage V
OUT(Ph2) with sampling input voltage V
IN(Ph1) equal or approaching.Following formula shows, sets appropriate C
CV
CProduct can bucking circuit voltage error V
OS, make the maintenance output voltage V
OUT(Ph2) with sampling input voltage V
IN(Ph1) equal or approaching, when circuit is implemented, can be by changing C
CV
CProduct makes above-mentioned bucking voltage approach the real voltage offset error with suitable scope and precision step-length.
Among the present invention, can change bucking voltage V separately
COr change building-out capacitor C separately
C, also can change bucking voltage V simultaneously
CWith building-out capacitor C
C, all can cause C
CV
CProduct changes, thereby realizes error compensation.As special case, also can set the fixation of C approaching with voltage error
CV
CProduct makes following formula error minimum.
A kind of circuit structure diagram when as shown in Figure 4, being variable value for building-out capacitor C1.By the individual capacitor cell (C of N (N 〉=1)
X1～C
XN) and the individual switch (S of N (N 〉=1)
X1～S
XN) form, N switch is parallel between signal node 11 and the signal node 12 composition building-out capacitor C1 with after N capacitor cell connected respectively.During arbitrary switch closure, Chuan Lian capacitor cell is parallel between signal node 11 and the signal node 12 with it in N the switch, the part of capacitor C 1 by way of compensation, otherwise the corresponding capacitance unit is not a bucking voltage.The capacitance of N capacitor cell can be identical or proportional (changing as weight), and the step-length of relative set building-out capacitor C1 is identical or proportional.If N shunt capacitance unit is identical, establishing its capacitance is C
X0, in this case, when total n (behind the individual switch closure of 1≤n≤N), the building-out capacitor C1 capacitance after the parallel circuits combination is:
C
C=n * C
X0, 1≤n in the formula≤N
Following formula shows, when n gets different value, and corresponding different building-out capacitor value, thus different C is arranged
CV
C, satisfy the needs of error compensation range regulation.
Need to prove, building-out capacitor mentioned in this article, both can be any type of electric capacity that to realize in the integrated circuit technology, as mos capacitance, poly-poly electric capacity, metal capacitance etc., the also discrete fixed capacity and the discrete variable capacitance of chip exterior, the outer discrete capacitor of sheet can be connected between signal node 11 and the signal node 12 by the chip circuit pin.
A kind of circuit structure diagram when as shown in Figure 5, being variable value for offset supply VS1.By a reference source, series resistance R
1～R
N, multiselect switching network SW
1～SW
NForm.The final voltage output node of offset supply is signal node 13 (being same signal node with signal node among Fig. 3 13).A reference source can be reference voltage source V
BOr reference current source I
B, output voltage V
RBe reference voltage V
RReference voltage V
RRealization can be fixed voltage or variable voltage (as numerical control voltage), its purpose is the error compensation voltage that provides suitable to satisfy the requirement of compensation range and compensation precision (step-length).The output voltage V c of offset supply
1～Vc
NIn reference voltage V
RAnd between the reference potential, there are suitable voltage range and adjacent voltage step size (precision), to provide size accuracy suitable error compensation voltage.Series resistance R
1～R
NResistance value can equate also can proportionally to change (changing) as weight, corresponding, output bucking voltage Vc
1～Vc
NAdjacent voltage spaces (step-length) also equates or proportional variation.Multiselect switching network SW
1～SW
NBe multiselect one switch, i.e. SW in the switching network under a kind of adjustment state
1～SW
NCan only be in closure state by a switch, other switch is in off-state.For example, as multiselect switching network SW
1～SW
NIn i switch closure, when all the other N-1 switches disconnected, this moment, signal node 13 gating bucking voltages were Vc
iBe output bucking voltage V
C, magnitude of voltage is:
V
C＝V
Ci＝k·V
R·(R
1+R
2+…+R
i)/(R
1+R
2+…+R
N)
V in the following formula
CBe the bucking voltage of signal node 13 outputs, V
CiBe R
iLast output voltage, k represents R
NOn voltage and reference voltage V
RRatio, k=1 in circuit shown in Figure 5, R
1To R
NRepresent series resistance R respectively
1～R
NMagnitude of voltage.As seen, gating multiselect switching network SW
1～SW
NIn different switches, the different bucking voltage of corresponding output has realized the control to bucking voltage.
As bucking voltage V
CWith building-out capacitor C
CBe when variable, regulate flexiblely, the adjustable range broad can make the error compensation of sampling hold circuit reach optimum, and deficiency is that the auxiliary control circuit that needs is more, and circuit is also relatively complicated.As bucking voltage V
CRemain unchanged building-out capacitor C
CDuring for variable value, circuit structure is simple relatively, control logic circuit is easier to design, in integrated circuit technology, thereby the ratio of electric capacity also is easier to control the error compensation that realizes degree of precision, deficiency is that the error compensation scope is less, may cause error compensation not enough under some harsh circuit condition.As building-out capacitor C
CRemain unchanged bucking voltage V
CDuring for variable value, in integrated circuit technology, the change of magnitude of voltage realizes that relatively easily it is better to regulate flexibility, and deficiency is the difficult control of the precision of voltage, may limit the compensation precision to sampling hold circuit.
Certainly, can adopt two sampling hold circuits of the present invention to constitute the fully differential circuit for expanded application.Circuit adopts two independently compensating unit circuit, can compensate respectively the positive and negative terminal input signal, also can compensate because the extra error that the passage difference of positive and negative passage causes makes compensation best in the larger context.
As shown in Figure 6, the fully differential circuit is by a shared offset supply VS1, and common switch S1 and switch S 2 have realized the simplification of circuit.Building-out capacitor C1 and building-out capacitor C2 are connected respectively to the positive and negative channel signal output of difference channel, i.e. signal node 10 and signal node 11.Building-out capacitor C1 and building-out capacitor C2 can be the same or different, and the bucking voltage to positive and negative passage when the two is identical is also identical, when the two difference (or different slightly) to the bucking voltage difference of positive and negative passage, can further compensate the passage difference.The advantage of circuit shown in Figure 6 is bucking voltage and control circuit are simplified, and helps saving circuit power consumption and chip area.
As shown in Figure 7, the fully differential circuit passes through shared offset supply VS1, common switch S1 and switch S 2, and increased switch S 3 and switch S 4.Switch S 3, switch S 4 are connected between building-out capacitor C1, building-out capacitor C2 and the common node 12.Described switch S 3 and switch S 4 are can be as required closed or disconnect, thus enable or disconnect corresponding just/error compensation of negative passage.Foregoing circuit can be realized the shielding to bucking voltage, thereby on the basis of both-end, implements the alternately compensation of single-ended compensation or both-end, so that departure compensation more flexibly.
The content that is not described in detail in the specification of the present invention belongs to those skilled in the art's known technology.
Claims (4)
1. adopt compensation way to improve the sampling hold circuit of performance, comprise by transistor M1 and capacitor C
SThe sampling unit (32) that constitutes, the source terminal reception sampled signal of transistor M1, the grid termination clock control signal Ph1 of transistor M1, the drain electrode termination capacitor C of transistor M1
SAn end, capacitor C
SAnother termination reference potential, the drain electrode end of transistor M1 and capacitor C
SCommon port as the output (11) of sampling unit (32), it is characterized in that: also comprise compensating unit (30), described compensating unit (30) comprises building-out capacitor C1, offset supply VS1, switch S 1, switch S 2 and clock control signal Ph1 and Ph2, the output voltage V of offset supply VS1
CBe connected to reference potential through switch S 2, switch S 1, one of building-out capacitor C1 is connected to the common port (12) of switch S 1 and switch S 2, and the other end of building-out capacitor C1 is connected to the output (11) of sampling unit (32); Switch S 1 is controlled by clock control signal Ph1, switch S 2 is controlled by the inverted signal Ph2 of clock control signal Ph1, sample phase, and clock control signal Ph1 is effective, transistor M1 conducting, switch S 1 closure, switch S 2 disconnects the maintenance stage, clock control signal Ph2 is effective, transistor M1 ends, and switch S 1 disconnects switch S 2 closures.
2. employing compensation way according to claim 1 improves the sampling hold circuit of performance, it is characterized in that: the output voltage V of described offset supply VS1
C, building-out capacitor C1 appearance value C
CAnd sampling capacitance C
SAppearance value C
0Offset voltage V with circuit
OSSatisfy relational expression: C
CV
C/ (C
0+ C
C)=V
OS, V wherein
OSOutput voltage and unequal all error voltages of input voltage for the treatment of sampled signal for the output (11) that causes sampling unit (32).
3. employing compensation way according to claim 1 and 2 improves the sampling hold circuit of performance, it is characterized in that: the appearance value C of described building-out capacitor C1
CBe fixed value or variable value.
4. employing compensation way according to claim 1 and 2 improves the sampling hold circuit of performance, it is characterized in that: the output voltage V of described offset supply VS1
CBe fixed value or variable value.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101977059A (en) * | 2010-11-23 | 2011-02-16 | 复旦大学 | Sample-and-hold circuit at front end of superhigh speed flash analog-digital converter |
| CN102664626A (en) * | 2012-05-17 | 2012-09-12 | 中国电子科技集团公司第二十四研究所 | Capacitance error compensation circuit based on microcurrent source |
| CN102882526A (en) * | 2012-10-23 | 2013-01-16 | 四川和芯微电子股份有限公司 | ADC (analog to digital converter) sampling circuit |
| CN103219901A (en) * | 2013-04-19 | 2013-07-24 | 矽力杰半导体技术(杭州)有限公司 | Alternating current/direct current (AC/DC) converter control circuit and AC/DC converter using same |
| CN103596319A (en) * | 2012-08-14 | 2014-02-19 | 华润矽威科技（上海）有限公司 | A non-isolated LED driving system and a non-isolated LED driving constant-current control circuit |
| CN103684461A (en) * | 2012-09-21 | 2014-03-26 | 美国亚德诺半导体公司 | Sampling circuit, method of reducing distortion in sampling circuit, and analog to digital converter including such sampling circuit |
| CN104410421A (en) * | 2014-11-11 | 2015-03-11 | 昆腾微电子股份有限公司 | A capacitance compensation device and method for a sampling circuit |
| CN108364455A (en) * | 2018-02-11 | 2018-08-03 | 许少辉 | The signal compensation circuit of medical remote monitoring system |
| CN110146066A (en) * | 2019-05-21 | 2019-08-20 | 深迪半导体(上海)有限公司 | Quadrature error compensation circuit, MEMS sensor read-out device and MEMS sensor system |
| CN112000162A (en) * | 2020-07-23 | 2020-11-27 | 圣邦微电子（北京）股份有限公司 | Band-gap reference voltage source |
| CN112397131A (en) * | 2019-08-12 | 2021-02-23 | 长鑫存储技术有限公司 | Data sampling circuit |
| CN116131849A (en) * | 2023-02-22 | 2023-05-16 | 北京士模微电子有限责任公司 | Sampling circuit, integrated circuit and electronic equipment |
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101977059A (en) * | 2010-11-23 | 2011-02-16 | 复旦大学 | Sample-and-hold circuit at front end of superhigh speed flash analog-digital converter |
| CN102664626B (en) * | 2012-05-17 | 2015-05-06 | 中国电子科技集团公司第二十四研究所 | Capacitance error compensation circuit based on microcurrent source |
| CN102664626A (en) * | 2012-05-17 | 2012-09-12 | 中国电子科技集团公司第二十四研究所 | Capacitance error compensation circuit based on microcurrent source |
| CN103596319B (en) * | 2012-08-14 | 2015-05-27 | 华润矽威科技（上海）有限公司 | A non-isolated LED driving system and a non-isolated LED driving constant-current control circuit |
| CN103596319A (en) * | 2012-08-14 | 2014-02-19 | 华润矽威科技（上海）有限公司 | A non-isolated LED driving system and a non-isolated LED driving constant-current control circuit |
| CN103684461A (en) * | 2012-09-21 | 2014-03-26 | 美国亚德诺半导体公司 | Sampling circuit, method of reducing distortion in sampling circuit, and analog to digital converter including such sampling circuit |
| CN103684461B (en) * | 2012-09-21 | 2017-01-04 | 美国亚德诺半导体公司 | Sample circuit, down-samples the method for distortion in circuit and includes the analog-digital converter of this sample circuit |
| CN102882526A (en) * | 2012-10-23 | 2013-01-16 | 四川和芯微电子股份有限公司 | ADC (analog to digital converter) sampling circuit |
| CN103219901A (en) * | 2013-04-19 | 2013-07-24 | 矽力杰半导体技术(杭州)有限公司 | Alternating current/direct current (AC/DC) converter control circuit and AC/DC converter using same |
| CN103219901B (en) * | 2013-04-19 | 2015-12-09 | 矽力杰半导体技术(杭州)有限公司 | AC/DC converter control circuit and apply its AC/DC converter |
| CN104410421A (en) * | 2014-11-11 | 2015-03-11 | 昆腾微电子股份有限公司 | A capacitance compensation device and method for a sampling circuit |
| CN108364455A (en) * | 2018-02-11 | 2018-08-03 | 许少辉 | The signal compensation circuit of medical remote monitoring system |
| CN108364455B (en) * | 2018-02-11 | 2020-07-03 | 上海柯渡医学科技股份有限公司 | Signal compensation circuit of medical remote monitoring system |
| CN110146066A (en) * | 2019-05-21 | 2019-08-20 | 深迪半导体(上海)有限公司 | Quadrature error compensation circuit, MEMS sensor read-out device and MEMS sensor system |
| CN112397131A (en) * | 2019-08-12 | 2021-02-23 | 长鑫存储技术有限公司 | Data sampling circuit |
| CN112000162A (en) * | 2020-07-23 | 2020-11-27 | 圣邦微电子（北京）股份有限公司 | Band-gap reference voltage source |
| CN116131849A (en) * | 2023-02-22 | 2023-05-16 | 北京士模微电子有限责任公司 | Sampling circuit, integrated circuit and electronic equipment |
| CN116131849B (en) * | 2023-02-22 | 2024-02-06 | 北京士模微电子有限责任公司 | Sampling circuit, integrated circuit and electronic equipment |
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