CN101794624A - Failure diagnosis of serial addressing memory module of personable computer mainboard - Google Patents
Failure diagnosis of serial addressing memory module of personable computer mainboard Download PDFInfo
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- CN101794624A CN101794624A CN200910003802A CN200910003802A CN101794624A CN 101794624 A CN101794624 A CN 101794624A CN 200910003802 A CN200910003802 A CN 200910003802A CN 200910003802 A CN200910003802 A CN 200910003802A CN 101794624 A CN101794624 A CN 101794624A
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Abstract
The invention relates to failure diagnosis of a serial addressing memory module of a personable computer mainboard. A testing adaptor plate is connected to a computer mainboard for testing a memory module on a testing socket, a standard memory module socket is moved out of a target DRAM (Dynamic Random Access Memory) module slot on a component surface, the testing adaptor plate is connected to a target DRAM module slot on the back (welding) side of the mainboard, the target DRAM module slot is a middle slot, for example, a second or third target DRAM module slot of four target DRAM module slots, and favorable memory modules are implanted in the first target DRAM module slot and the fourth target DRAM module slot so that a BIOS (Basic Input/Output System) is stored at a high address, operating system images and a testing program are stored at a low address, and the testing program is stored in the memory modules in the testing socket for detecting defects. Because the BIOS, the operating system images and the testing program are not stored in the memory modules to be tested, the mainboard can not stop running.
Description
Technical field
The present invention relates to the memory module tester.More specifically, the present invention relates to a kind of personable computer mainboard memory tester.
Background technology
Memory module is used in electronic system miscellaneous.Personal computer (personal computer; PC) with the main storer of memory module as the PC motherboard.For guaranteeing potential vast market, the specification manufacturing that memory module is formulated according to industry standard.The module cost continues to be subjected to a large amount of production and competition, is promptly descended, and is therefore very beneficial to the consumer of electronic system of all kinds.
Memory module has many different sizes and capacity, for example than single line memory module (the single-inline memory modules of 30-pin morning (30-pin) with the 72-pin; SIMMs) and two-wire memory module (the dual inline memory modules of new 168-pin, 184-pin and 240-pin; DIMMs)." pin " former finger is from the extended pin of module edge with Metal Contact pad or lead, yet present most module is no lead.This kind module size is little, is about 3 to 5 inches, high about 1 to 1.5 inch.
This kind module comprises a little printed circuit board substrate (substrate), be generally a multilayer circuit board, this multilayer circuit board has the laminated alternately of glassfiber insulation (fiberglass insulation) and paper tinsel or metal interconnected (metalinterconnect) layer.Assembly is to be positioned on the surface, for example is welded in two surface or a lip-deep dram chip and capacitors wherein of substrate.
Fig. 1 illustrates one and cushions (fully-buffered) memory module fully.Memory module 10 comprises a substrate, and substrate can be has the multilayer board (printed-circuitboard that the surface is provided with dram chip 22; PCB).As shown in Figure 1, dram chip 22 is front surface or the sides that are arranged at substrate, and more dram chip 22 is arranged at the back side or surface (figure does not illustrate) of substrate.Memory module 10 can be one to cushion two-wire memory module (fully-buffered dual-inline memory module fully; FB-DIMM), this FB-DIMM is by (the advanced memorybuffer of the advanced memory buffer on the memory module 10; AMB) chip (figure does not illustrate) is to reach buffering fully.The AMB chip with differential wave (differential signaling) and grouping so that transmit data with two-forty.
During the memory module that does not have at present the AMB chip still continues to produce.The non-cushioned memory module of this kind will directly carry (carry) address, data and control signal to dram chip 22 by the Metal Contact pad 12 of motherboard.The simplification impact damper of some memory module utilization buffering or some signal of locking (latch), but do not use among the FB-DIMM complicated serial packet interface.
Metal Contact pad 12 is arranged along the root edge of module upper surface and lower surface.Pad fluid-tight engagement on Metal Contact pad 12 and the modular jack is so that be electrically connected to module the motherboard of one PC.The module of some kind has hole 16 and is placed in the socket with correct position to guarantee module.Groove 14 also is to be used for guaranteeing that the module insertion is correct.Capacitor or other are positioned at on-chip discrete component in order to filter the noise from dram chip 22.
Some memory module comprises that there is detection EEPROM (Electrically Erasable Programmable Read Only Memo) (serial-presence-detect electrically-erasable programmableread-only memory in the serial that is positioned at the memory module substrate; SPD-EEPROM).The SPD-EEPROM130 storage is used for the configuration information of memory module, for example arrangement (arrangement) of storing in speed, the degree of depth (depth) and the memory module.
PC memory module tester-Fig. 2
Fig. 2 illustrates the memory module tester of personal computer PC motherboard.Please refer to United States Patent (USP) the 6th, 357,022,6,351,827 and 6,742, No. 144 explanations.
Although memory module can be inserted into a memory module test jack of tester by manual type, but still need a kind of memory module manipulater (handler) that can insert and remove memory module automatically.Manipulater 60 is arranged near the PC motherboard rear of using manipulater breakout box plate (handler adaptor board) 50.Based on proportionate relationship,, thereby do not illustrate because manipulater 60 is bigger several times than PC motherboard.
Manipulater 60 is not to be arranged on the assembly face of PC motherboard, but with the face of weld of retroactive addition to the PC motherboard.After the memory module socket is removed on the assembly face that is positioned at the PC motherboard, manipulater breakout box plate 50 is inserted into hole on the PC motherboard from the rear, with as the memory module socket.Manipulater breakout box plate 50 is small-sized expoxy glass (epoxy-glass) circuit board, and this small-sized expoxy glass circuit board is in order to be engaged to a manipulater one PC motherboard.
When robotic arm (arm) 76 promotes tested module (module under test; MUT) 70 to the appropriate location when accepting test, the contactor pins 66 in the manipulater 60 will clamp down on the no wire bonds point on tested module 70 edges.Contactor pin 66 has enough pads to be used with electric power, ground connection and input and output lead on the supply tested module 70.
When the memory module socket was removed, breakout box pin 52 can utilize the hole of exposing, and is directly welded on the PC motherboard substrate 80, or breakout box pin 52 is inserted into female pin 55, and wherein female pin 55 is welded on the face of weld 84 of PC motherboard.Female pin 55 has the insertion of being fit to and removes the through hole (through-holes) that exposes behind the SIMM socket, and is fit to insert cup-shaped jack (cup-like receptacles) to receive the ductility of breakout box pin 52.Use female pin 55 that manipulater breakout box plate 50 is removed from substrate 80 easily.
In case after tested module 70 the test procedure test by PC motherboard running, tested module 70 will be stored and under be put in good pin 72 or the bad pin 74.Storage action is that one of corresponding test procedure by PC motherboard running is carried out by/failure signal.
The substrate 80 of PC motherboard is existing multilayer epoxy glass fiber (epoxy-fiberglass) circuit board.Assembly 92,94 is arranged on the assembly face 82 of substrate 80.Memory module 87 is fitted and can be inserted memory module socket 88, and wherein memory module socket 88 has the metal pin that can be inserted into hole on the substrate 80 fully.These pins are welded in the face of weld 84 of substrate 80, with firmly with outlet add-on on the PC motherboard.Expansion board 96 is to be inserted on the expansion socket of being located on the substrate 80 assembly faces 82.The cable 98 that is inserted into expansion board 96 can be connected to PC with peripheral unit (as disk set, movie monitor and multimedia device).
Because the memory module tester is to be located on the cheap PC motherboard of price, so the cost of tester is than the automated test device (automated-test-equipment that must spend 1,000,000 US dollars; ATE) machine is cheaply many.Therefore, use the testing cost of PC motherboard tester can show the reduction that lands.The memory under test module can be used many different test models (test patterns), and carries out the angular measurement examination (corner testing) that can change voltage and temperature.Angular measurement examination is blown heat or cold air to the memory under test module by a nozzle (nozzle) (scheming not paint), and applies to the voltage of memory under test module with manipulater breakout box plate 50 or the adjustment of PC motherboard.
Fig. 3 is the electrical wiring on the memory module.Memory module 10 have with motherboard 28 on the connector 32 of memory module socket fluid-tight engagement.Memory module 10 is a no buffered memory modules, this no buffered memory modules has DRAM address signal A13:0, memory bank (bank) address BA1:0 and other control signal, and other control signal for example is: row address strobe (row address strobe; RAS) control signal, column address strobe (column address strobe; CAS) control signal, can write (write enable; WE) control signal and any directly timing (clock) by connector 32 or make timing (clock-enable) signal.
Most signal is directly to pass through to dram chip 40 via memory module 10 on-chip traces (traces) 34 in the connector 32.Row all is transfused to via multipath transmission address wire (multiplexedaddress lines) with column address.Column address is designated to (apply to) address wire, low then (drivenlow) RAS that drives, dram chip 40 locking column addresss and begin the row (all columns inthe row) of all these row of access simultaneously.Then, column address is assigned to identical address wire, the low then CAS that drives.Dram chip 40 utilizes column address so that select the data of row wherein in the selected row.
Some bank-address inputs also can be supported, as BA1:0.Bank-address is not a multi-route, and row address only is provided usually.Bank-address can be selected one of them from several storage matrix of dram chip inside.
Some memory module comprises one and is positioned at the on-chip serial existence of memory module detection EEPROM (Electrically Erasable Programmable Read Only Memo) (serial-presence-detect electrically-erasable programmableread-only memory; SPD-EEPROM).SPD-EEPROM 130 storages are used for the configuration information of memory module, as: the arrangement of storing in speed, the degree of depth and the memory module.
During initialization, the host-processor of motherboard 28 reads configuration information from SPD-EEPROM130.This configuration information about memory module 10 is transferred into the serial data line SPD_D synchronous with SPD timing SPD_CLK.The address that inputs to SPD EEPROM 130 is from address wire SPD_A[2:0] on motherboard 28 carry address wire SPD_A[2:0] can be the hard lead on the motherboard 28.The unit address of memory module 10 (memory module slot number) is by SPD_A[2:0 on the motherboard 28] wiring configuration decision.Be sent to a succession of frame (frames) of data of serial data line SPD_D for forming by unit address, type of device, register (register) position and register data.
Dram chip has sizable capacity, as 512 megabits (mega bits; Mbits) or half kilomegabit (giga-bit).Defective owing to the quantity of memory cell (cells) is big, the area of the little and whole DRAM fault of capacity of individual memory cell causes manufacture view has greatly become quite general situation.Before being cut and encapsulating, can earlier dram chip be placed a wafer (wafer) to go up test earlier, yet this kind wafer class testing possibly can't be found all defect.
Therefore some has encapsulated dram chip and has still had defective.Defective dram chip must carry out the further cheap test of expense with two-forty for encapsulating dram chip, so that can be identified and abandon.Manufacturers can will be built in the dram chip in the memory module earlier, are tested by the low-cost memory module tester of being located on the motherboard more subsequently.
Fig. 4 is the memory partitioning figure (memory map) of a PC motherboard storer, and this PC motherboard has a test jack, and this test jack is used to low order address testing memory module.The storage space of PC motherboard microprocessor has Basic Input or Output System (BIOS) (basic input output system; BIOS), this BIOS can map to the location superlatively in the storage space.The procedure code of BIOS can be read by a read-only access to memory, and is copied to the memory module of inserting DRAM module slot 566 during start.After a while in boot program, operating system (operating system; OS) a image will be loaded on the lowest address of the storage space of DRAM module slot 562.
After the start, memory module producer's employed one special test procedure can be loaded on the memory module in the DRAM module slot 562.DRAM module slot 562 can be inserted a memory under test module, and wherein this memory under test module has been for being inserted on the test adaptor device plate memory under test module of test jack 560 in the test jack, but not inserts the memory module on the PC motherboard.Yet when the memory under test module was defectiveness, its defective 56 may betide in test procedure or the OS image, and causes the PC motherboard to decommission.In the ideal case, defective 56 is not present in and distributes to the storage that comprises the OS image in the DRAM module slot 562 and partly should be arranged in another storage that DRAM module slot 562 tested by test procedure partly.Then, this test procedure may will decommission or repay error message.
Yet when the defective in the tested memory module 56 betided DRAM module slot 562 and comprises the part of OS image, the PC motherboard just decommissioned in the time of might or just having started shooting during start very much.Because test procedure can't be repaid the position of error memory, this kind situation should be avoided.Test macro still can detect this mistake because of motherboard decommissions, and abandons the memory under test module in the test jack 560.
Fig. 5 is the memory partitioning figure of PC motherboard storer, and this PC motherboard has a test jack, and this test jack is used to high address testing memory module.Test jack 560 is connected to the end points of motherboard DRAM module slot 566, but not is connected to the low order address of DRAM module slot 562.Therefore the memory under test module comprises the highest memory address in PC.
Because BIOS is copied to DRAM module slot 566, BIOS also will be copied to the memory under test module.When BIOS is loaded on the defective locations of DRAM, will make a mistake, so the PC motherboard when test procedure does not carry out, will decommission during start.Because the accurate position of memory under test module defective 56 is still undiscovered, this kind situation should be avoided.Yet test macro still can detect this mistake because of motherboard decommissions, and abandons the memory under test module in the test jack 560.
General is target with the exact position of finding out defective in the memory module all.For example:, then can in the memory module substrate, remove the DRAM memory chip that comprises this defective, and new dram chip is welded on this memory module by a revision program (rework process) if this defective locations is known.This kind revision program can be saved defective memory module.
Production period can cooperate Fault Diagnosis, for example: the cause of failure judgement.Can produce a statistic according to abort situation, this statistic can be used to judge whether certain specific portion is fragile in the memory module.By this, the transformation again of memory module can make to make and produce progress.
Summary of the invention
Therefore, a kind ofly judge that the PC motherboard tester of the defective locations of imperfect memory module is required.A kind of is not required because of testing the motherboard tester that imperfect memory module decommissions.A kind of use test program and be required with the motherboard tester of isolated imperfect memory location.
The invention provides a kind of motherboard tester, in order under the situation that memory module is decommissioned, survey the defective in the memory module, comprise: test adaptor device plate, has test jack, test jack is the memory under test module of being tested by the motherboard tester in order to engage, the memory under test module that test adaptor device plate will be inserted in the test jack is electrically connected to the motherboard that joins with test adaptor device plate, and motherboard partly uses main storer middle of the memory under test module in the test jack as motherboard; Motherboard is the mainboard that is used for computing machine, and computing machine uses memory module as main storer; First module slot is positioned on the motherboard and is connected to first memory modular jack on the assembly face of motherboard, and has the first known good memory module of having inserted; Second module slot is connected to the position of second memory modular jack on the assembly face of motherboard and is connected to test adaptor device plate, and the memory under test module that wherein has been inserted in test jack on the test adaptor device plate is electrically connected to second module slot; The three module slot is positioned on the motherboard and is electrically connected to the 3rd memory module socket on the assembly face of motherboard, and has the second known good memory module of having inserted; The copy of Basic Input or Output System (BIOS) is stored in the second known good memory module; Operating system image is stored in the first known good memory module; Test procedure is stored in the first known good memory module, and wherein test procedure is performed by the processor on the motherboard, so that the memory location in the memory under test module can be read and write and can not cause motherboard to decommission; And defective locations, being arranged in the memory under test module, the test procedure that can be performed in processor identifies, and is reported to the user; By this, test procedure identifies defective locations, and because of test procedure is not loaded in the memory under test module, so motherboard can not decommission.
The present invention provides a kind of opposing memory module tester that decommissions in addition, comprises: the robot device, in order to memory module is moved to the output storehouse of testing memory module by the input storehouse of testing memory module not; Principal computer is in order to the control robot device; A plurality of testing stations, in order to the memory module that test loads and unloads by the robot device, each testing station comprises: test adaptor device plate; Test jack is positioned on the test adaptor device plate, and test jack is in order to engage memory module, and memory module is inserted in test jack and is become the memory under test module by the robot device; Motherboard is used for personal computer, and in order to the order of response principal computer, carries out test procedure and is inserted in memory module in the test jack with test; First module slot is positioned on the motherboard, and first module slot is connected to the first memory modular jack on the assembly face of motherboard and has the first known good memory module of having inserted; Second module slot is connected to the position of the second memory modular jack that has removed on the assembly face of motherboard and is connected to test adaptor device plate, and the memory under test module that wherein is inserted in test jack on the test adaptor device plate is electrically connected to second module slot; The three module slot is positioned on the motherboard and is connected to the 3rd memory module socket on the assembly face of motherboard, and has the second known good memory module of having inserted; The copy of Basic Input or Output System (BIOS) is stored in the second known good memory module; And operating system image, be stored in the first known good memory module; Wherein test procedure is stored in the first good memory module, and test procedure is performed by motherboard, so that the memory location in the memory under test module can be read and write and not cause motherboard to decommission; By this, test procedure is not loaded in the memory under test module, so test procedure can be tested the memory under test module and do not cause motherboard to decommission.
The present invention also provides a kind of opposing memory module tester that decommissions, and comprises: the robot device, in order to memory module is moved to the output storehouse of testing memory module by the input storehouse of testing memory module not; Principal computer is in order to the control robot device; A plurality of testing stations, in order to the memory module that test loads and unloads by the robot device, each testing station comprises: test adaptor device plate; Test jack is positioned on the test adaptor device plate, and test jack is in order to engage memory module, and memory module is inserted in test jack and is become the memory under test module by the robot device; Motherboard is used for personal computer, and in order to the order of response principal computer, carries out test procedure and is inserted in memory module in the test jack with test; First module slot is positioned on the motherboard, and first module slot is connected to the first memory modular jack on the assembly face of motherboard and has the first known good memory module of having inserted; Second module slot is connected to the position of the second memory modular jack that has removed on the assembly face of motherboard and is connected to test adaptor device plate, and the memory under test module that wherein is inserted in test jack on the test adaptor device plate is electrically connected to second module slot; The three module slot is positioned on the motherboard and is connected to the 3rd memory module socket on the assembly face of motherboard, and has the second known good memory module of having inserted; The copy of Basic Input or Output System (BIOS) is stored in the second known good memory module; And operating system image, be stored in the first known good memory module; Wherein test procedure is stored in the first good memory module, and test procedure is performed by motherboard, so that the memory location in the memory under test module can be read and write and not cause motherboard to decommission; By this, test procedure is not loaded in the memory under test module, so test procedure can be tested the memory under test module and do not cause motherboard to decommission.
Description of drawings
Fig. 1 is the synoptic diagram of a fully-buffered memory modules;
Fig. 2 illustrates a memory module tester that is arranged at the PC motherboard;
Fig. 3 illustrates the electrical wiring on the memory module;
Fig. 4 is the memory partitioning figure of a PC motherboard, and its PC motherboard has the test jack with low order address testing memory module;
Fig. 5 is the memory partitioning figure of a PC motherboard, and its PC motherboard has the test jack with high address testing memory module;
Fig. 6 is the memory partitioning figure of PC motherboard, and its PC motherboard has in one tests the test jack of the memory module on second module position with the address;
Fig. 7 is the memory partitioning figure of PC motherboard, and its PC motherboard has to test the test jack of the locational memory module of three module in another with the address;
Fig. 8 A and 8B point out when BIOS for interleaving access during the config memory module, the problem of testing memory module;
Fig. 9 illustrates a non-homogeneous storage space, and it can avoid the problem that taken place when the interleaving access as Fig. 8 B;
Figure 10 illustrates to revise has the memory module of damaging dram chip;
Figure 11 illustrates the memory module that test one usage level is provided with motherboard;
Figure 12 one looks down the aerial view of a multiple masters testing station downwards, and its multiple masters testing station has the overhead track (overhead rail) that uses for x-y-z robot (robotic) manipulater.
Embodiment
The present invention relates to improvement to memory module tester and diagnostic tool.Following narration is to make to be familiar with this technical field person and can to utilize the present invention, and application of the present invention and required condition are provided simultaneously.Explanation hereinafter, be under making in the technical field those of ordinary skill can make and use the present invention and propose, and provide according to patented claim and requirement thereof.To those skilled in the art, it is conspicuous making various modifications for following preferred embodiment and general principle and feature.Therefore, scope of the present invention is not limited only to embodiment as herein described, but with principle as herein described and the consistent maximum magnitude of feature.
The inventor discovers if the memory under test module is placed the partly middle of motherboard address space, but the fault of assisted diagnosis memory module.Two good memory modules are inserted standard storage module socket on the motherboards, from motherboard one the 3rd memory module socket is removed simultaneously, and the motherboard trace that will be used for having removed socket is connected to test adaptor device plate.The memory under test module will be inserted into the test jack on the test adaptor device plate and be connected to the motherboard trace that is used for removing the memory module socket.
The memory module that has removed is to use in order to the center section as the motherboard address space.The BIOS that is positioned at the high address is loaded on one of them of good memory module, and is arranged in the OS image of low order address and other good memory module that test procedure is loaded on standard storage module socket on the insertion motherboard.Therefore, BIOS, OS image and test procedure all are loaded on known good memory module.And the intermediate address in the address space can be videoed to the memory under test module of possible breakdown, wherein, intermediate address be not give the important procedure sign indicating number that causes motherboard to decommission used.
Even the memory under test module is a fault, motherboard still can be started shooting and be carried out test procedure and can not decommission.This test procedure can completely cut off the failed storage position in the memory under test module and repay this position to tester system main frame or diagnostic device.
Fig. 6 is the memory partitioning figure of PC motherboard, and its PC motherboard has in one tests the test jack of memory module on second module position with the address.The storage space of microprocessor has basic input and output and goes into (the basic input output system of system on the PC motherboard; BIOS), BIOS can map to the highest addresses of storage space.This bios program sign indicating number can be from read-only access to memory (read only memory; ROM) be read, and during start, be copied to DRAM module slot 568.In boot program after a while, operating system (operatingsystem; OS) a image will be loaded on the lowest order address of storage space in the DRAM module slot 562.
After the start, storer producer employed one special test procedure will be loaded on the memory module that is connected to DRAM module slot 562.DRAM module slot 564 can be connected to the memory under test module of having inserted test jack 560, and test jack 560 is positioned on the test adaptor device plate that oppositely is arranged at the motherboard face of weld.DRAM module slot 564 is not to be connected to the memory module of inserting a standard storage module socket, and wherein this standard storage module is to be positioned on the assembly face of PC motherboard.
When the memory under test module is fault, defective will can not take place in test procedure or OS image, this is because test procedure and OS image are to be stored in the known good memory module, and this known good memory module is arranged in the DRAM module slot 562 on the motherboard.The BIOS copy that is arranged in the high address simultaneously is another the known good memory module that is stored in motherboard DRAM module slot 568, and the defective in the memory under test module also can not take place in the BIOS copy.
Since BIOS copy, OS image and test procedure all are stored in known good memory module, the defective 56 in the memory under test module will can not cause motherboard to decommission.As long as test procedure can be carried out (for example having the measure of restoring from the access of memory under test module failure memory location in the test procedure) well, motherboard will unlikely decommission.The detectable abort situation of this test procedure is with the repayment user, for example by test macro main frame or diagnosis main frame.This test procedure can write and read test socket 560 in all memory locations of memory under test module, wherein, test jack 560 is connected to DRAM module slot 564.
Motherboard can comprise three or four memory modules.When using four modules, the position of the 3rd memory module (DRAM module slot 566) can implant a known good memory module on a standard motherboard socket.
Fig. 7 illustrates the memory partitioning figure of PC motherboard, and its PC motherboard has with another intermediate address tests the test jack of memory module on the three module position.In this kind aspect, motherboard comprises four memory module socket positions: DRAM modular jack 562,564,566,568.In test period, four slots are all stuck with.Known good memory module is inserted in the standard storage module socket on the motherboard assembly face (DRAM modular jack 562,564,568).Test jack 560 breakout box plate after tested is connected to the motherboard trace of the 3rd DRAM module slot 566.
Because BIOS copy, OS image and test procedure all are stored in and are inserted into a DRAM module slot 562 and are inserted in the known good memory module of the 4th DRAM module slot 568, the interior defective 56 of memory under test module will can not cause motherboard to decommission.The test procedure sign indicating number can insert certainly in the memory module of a DRAM module slot 562 and read, and the test procedure sign indicating number can read and write the memory location that is inserted into memory under test module in the test jack 560, wherein, test jack 560 is to be connected to the 3rd DRAM module slot 566.When defective 56 was locked, the address that test procedure can write down its exact position and repay its all defect was to main frame or user.
BIOS routine configuration dram slot.
During the motherboard start, be copied in BIOS before or after the high address of DRAM, BIOS will carry out a series of routine.BIOS is stored in the flash memories usually, and this flash memories can be upgraded by the hardware configuration of motherboard.This hardware configuration can comprise last time motherboard running storage, about the information of DRAM in the slot.
Some BIOS conventional program can the execute store test.Whether BIOS can write a value in storage address, then read this address and still conform to judgment data.If data conform to, then BIOS supposes that just DRAM is positioned at this address at present.
BIOS has the form of feasible stored configuration.For example: when the implanted one 1 gigabit (giga of first slot are only arranged; G) during DRAM, the stored configuration table may have an inlet point (entry) for its use, or when all implanted 1G DRAM of two slots, the stored configuration table may have another inlet point to be used for these two DRAM, or when all implanted 1G DRAM of three slots, the stored configuration table may have other inlet point to be used or the like for these three DRAM.Some inlet point may use in mixed configuration, as: slot 1 is that 1G, slot 2 are that 4G and slot 4 are 4G for 512M, slot 3.This kind can allow the form of stored configuration all can comprise supporting paper or other file of BIOS or motherboard usually.
During the start, BIOS can automatically test the concatenation address, and according to the memory test result, selects an inlet point to dispose as present in the stored configuration form.This kind autorun may be because of carrying out the BIOS installation procedure and cancelling this function and can't carry out.Generally speaking, the BIOS installation procedure can be pressed certain specific keys and carries out during start, for example F5 on the PC keyboard or blank key.During start, display screen may occur notifying the user to press the information which kind of button can enter the BIOS installation procedure.
To the explanation of Fig. 3, BIOS can decide present stored configuration by the SPD_EEPROM 130 that reads each memory module as before.Some memory module comprises a serial and has the read-only access to memory of detection electric erazable programmable (serial-presence-detect electrically-erasableprogrammable read-only memory on the memory module substrate; SPD-EEPROM).SPD-EEPROM 130 storage is used for the configuration information of memory module, as the arrangement of the storage of speed, the degree of depth and memory module.BIOS can read the SPD-EEPROM 130 of each four memory module in the DRAM module slot 562,564,566,568, and finds the inlet point in the stored configuration form, and this inlet point is to meet the data that read from SPD_EEPROMs 130.After the storer autorun was cancelled, BIOS just used other method with config memory.The third method is just used last stored configuration for before motherboard is started shooting once more.
Cancellation storer autorun will force BIOS that the OS image is loaded on first memory module in the DRAM module slot 562 in BIOS.The advantage of this mode is to avoid the memory under test module of the second or the 3rd slot that the OS image is stored in low order address.
Interleaving access problem one Fig. 8 A and the 8B of DRAM
Fig. 8 A and 8B point out when BIOS in order to carry out interleaving access during the config memory module, the problem in the middle of the testing memory module.When all DRAM module slots 562,564,566,568 all implant the memory module (comprising the memory under test module of inserting test jack 560) of same capability, BIOS can select an inlet point from the stored configuration form, but this inlet point interleaving access two or four addresses that memory module is central.
Among Fig. 8 A, four memory modules all have same capability (dram chips of 12,800 megabits).For the memory module with 8 this kind chips, its module capacity is 12,800 megabyte (mega byte; MB).Because inserting the memory under test module of test jack 560 also is 128MB, so all four memory modules are all same capability, 128MB.
When with intermediate address access test socket 560, BIOS can select the stored configuration of an interleaving access, but not four memory modules are assigned to continuous address.For the stored configuration of two road interleaving access (2-way interleaved), its address is alternately to come across two memory modules.For example: a DRAM module slot 562 correspondences (routed) to from 0 to 4K-1 address, are corresponded to the 2nd DRAM module slot 564 address of 4K to 8K-1.The 4K block (the DRAM page) that links to each other the alternately access between two slots of formula (ping-pong fashion) of to rattle.The capacity of other staggered page (page-interleave) may be 8K, 2K, 1K or the like, or other staggered page can use word (word-interleaving) access that interlocks.
Because row precharge may overlap because of with the access of second memory module the time and be hidden, and then causes DRAM to postpone, so the stored interleaved with higher bandwidth is configured to preferable selection.When the capacity of memory under test module conformed to another capacity of inserting memory module, BIOS can select two road or four tunnel interleaving access configuration.
In Fig. 8 B, BIOS selects an interleaving access stored configuration.Because all four memory modules have same capability (128MB), BIOS selects the configuration of a double base two road interleaving access.The known good memory module that is inserted into the third and fourth DRAM module slot 566,568 is by interleaving access together, so BIOS is stored in two memory modules simultaneously.Similarly, be inserted into the memory under test module interleaving access of the known good memory module of a DRAM module slot 562 with the test jack 560 that is inserted into the 2nd DRAM module slot 564.Therefore, OS image and test procedure are stored in the known good memory module of a DRAM module slot 562 and the memory under test module of the 2nd DRAM module slot 564.
If the memory under test module comprises defective 56, and defective betides in the storer of part in order to the OS image of memory interlace access or test procedure, and then motherboard may decommission.The position of defective 56 can't tested program be found thereby is interrupted diagnosis, its be not hope.
Fig. 9 illustrates one non-homogeneous (non-homogenous) storage space, and it is in order to avoid the interleaving access problem as Fig. 8 B.The memory under test module is the capacity that is different from known good memory module, but not will be inserted into test jack 560 with the memory module of known good memory module same capability in the DRAM module slot 562,566,568.
The known good memory module of in the DRAM module slot 562,566,568 each is all the module of 128MB respectively, yet the memory under test module of inserting 564 test jacks 560 of the 2nd DRAM module slot is 1 GB (giga byte; GB) module.Because the capacity of memory under test module is different with the capacity of other memory module, BIOS can't select the interleaving access stored configuration of memory under test module with interleaving access.
BIOS still can continue inserting DRAM module slot 566,568 the 3rd and the 4th known good memory module interleaving access, but can't carry out interleaving access to the memory under test module of the 2nd DRAM module slot 564 and the known good memory module of a DRAM module slot 562.Therefore the OS image all is stored in the known good memory module with reaching test procedure, but not the memory under test module.Test procedure can be performed and can not cause decommissioning, and the position of finding out defective 56 simultaneously is with repayment main frame or user.
Except that the memory module of terrific insertion 128MB, the user can be with the memory module built-in test socket 560 of other capacity.By reminding the user can not insert the memory module of 128MB as host test system software or diagnostic software.If when needing test 128MB memory module, the memory module (as the memory module of 512MB) of different capabilities can be inserted.Another kind method can be used several motherboards with the known good memory module of different capabilities, so user or robotic manipulator can be inserted the memory under test module suitable motherboard to test.
Figure 10 will be for having the synoptic diagram of the memory module correction that has been identified as bad dram chip.During making, bad memory module can be identified in test.These a little bad memory modules can be collected and remove to a correction district to carry out possible reparation and repairing (salvage).The skilled worker who revises the district can use diagnosis formula motherboard tester described herein (promptly with intermediate address bad memory module being inserted test jack 560) to test all bad memory modules.
The method can allow complete execution test procedure, testing all memory locations of bad memory under test module, thereby can produce a defective locations map.The skilled worker can must abandon to judge whether this bad memory module can be corrected maybe according to this defective map.
Revising the skilled worker can use the storer map to judge which dram chip is defective in the bad memory module.Then, this defective dram chip will be removed or sealing-off (desoldering), and a new dram chip is welded on its position.Therefore, the memory module that has been corrected can be tested again and be returned the making flow process.
Among Figure 10, test procedure has been judged the defective in the bad dram chip 644.Test procedure is also judged zero defect in other dram chip 642.Module 600 can be by removing bad dram chip 644 and revising with obtaining of replacing of new dram chip.SPD-EEPROM 130 does not need again by reprogramming (reprogrammed).Since bad memory module can be repaired and sell, whole cost can be descended because of correction.
The production test system
Be arranged on the PC motherboard tester and unlike being used for present integrated circuit (integratedcircuit; IC) tester costliness makes that based on low-cost cause the tester that is arranged on the PC motherboard is developed.When the testing memory module, only about 10,000 U.S. dollars of motherboard tester cost and can replace the IC tester that needs cost 250,000 U.S. dollars.The memory module of desire test is inserted into test jack on the test adaptor device plate (subcard) to test, and wherein, test adaptor device plate is arranged at the reverse side of motherboard.In this described the present invention, can implement this test macro with motherboard, this test macro be with test adaptor device plate be connected to be used for intermediate address slot to guarantee interleaving access not to take place.
Figure 11 points out to use one to be horizontally disposed with (horizontally-mounted) motherboard to test a memory module.See also U.S.'s sequence number the 09/702nd, 017, be United States Patent (USP) the 6th now, 357, No. 023, title is " in order to test from the connector assembly with PC motherboard face of weld memory module of forced air " (ConnectorAssembly for Test ing Memory Models from the Solder-Side of a PC Motherboardwith Forced Hot Air).Existing P C motherboard is for turning upside down and flatly being arranged in the chassis 63.Motherboard substrate 30 utilizes fixed mount (standoff) or sept (spacer) 61 to be arranged at sheet metal 64, but not as among the existing P C motherboard substrate 30 being connected directly to chassis 63.Though motherboard substrate 30 is not connected directly to the chassis in this enforcement aspect, implements aspect motherboard substrate 30 in other and can be connected directly to the chassis.But sheet metal 64 mat screws, bolt or clip nail (figure does not paint) secure to chassis 63.
Test adaptor device version 50 is arranged in the class well portion 67, and class well portion 67 is arranged at sheet metal 64.Test jack 51 is arranged on the test adaptor device plate 50, and pin 52 can be electrically connected to motherboard substrate 30 for test jack 51.Memory under test module 18 can be inserted into test jack 51 to test.Test adaptor device plate 50 can be for the tested module (module-under-test of SIMM/DIMM test jack 51; MUT) be electrically connected on the PC motherboard in order to remove the lead of SIMM socket.
Test adaptor device plate 50 is a little circuit board, its can make automation mechanized operation device, operator or robot arm easily access be arranged at the SIMM/DIMM test jack 51 of test adaptor device plate 50.The test jack 51 on test adaptor device plate 50 a certain surfaces and the connector fluid-tight engagement of SIMM/DIMM memory module 18 (tested module).Another surface of test adaptor device plate 50 then has breakout box pin 52, and breakout box pin 52 is placed in the hole and electrically connects to form.The breakout box pin is welded in the through hole of breakout box plate 50 and substrate 30.Breakout box pin 52 and the pin that is used for DIMM socket 38 and is located at substrate have identical arrangement with at interval.One or more DIMM socket 38 is removed thereby stays through hole on the assembly face of PC motherboard.Breakout box pin 52 suitable can passing because of removing the through hole that the SIMM socket is exposed.From face of weld 35 (but not from assembly face 33) 52 backguys of breakout box pin are passed through to assembly face 33.
End face than large chassis can have a plurality of openings, and each opening can be fixed in sheet metal 64 in a horizontally disposed motherboard, but and use test breakout box plate.But this can allow a plurality of motherboards and test jack parallel testing.
Figure 12 one looks down the aerial view of a multiple masters testing station downwards, and its multiple masters testing station has the overhead track that uses for the x-y-z robotic manipulator.Please refer to the United States Patent (USP) the 6th of people such as Co (Co et al.), 415,397, title is " many PC of the robotization motherboard memory module test macro with virtual examination person among robotic manipulator and the figure " (Automated Multi-PC-Motherboard Memory-Module Test Systemwith Robotic Handler and In-Transit Visual Inspection).Operator 100 can be seated at control operation touch-control control panel or keyboard before the testing station.The pallet of testing memory module can not comprise a bar code (barcode), and before pallet placed input storehouse 163, operator 100 was with this bar code scanning to one main system interface 65.Then, robotic manipulator 180 is picked up the not test module that is moved into storehouse 163 input pallets 162.These modules are revealed tester (leakage tester) 182 with purchasing earlier to be put in.The module that robot arm 180 then will pass through moves to test jack, and wherein test jack is arranged on the test adaptor device plate of one of them motherboard substrate 30 face of weld to test.
The module by motherboard or leak-testing is not placed in reparation pallet 176 by robot arm 180.Before camera 175 as virtual examination person be extracted and be moved to robot arm 180 will by the module self-test socket of mother matrix test.Do not lost to VI pallet 178 by virtual examination person's module.The module that to pass through places output pallet 172, and will put full tray and move to storehouse 173 before the testing station so that operator 100 can remove it.
Each motherboard is for being horizontally disposed with, and turning upside down also can pack into tests the class well portion of station yard frame.The testing station has the surface that is positioned at the bench top height approximately, and bench top is surveyed the face of weld that motherboard exposes in the class well portion by the sign indicating number frame and formed.Robotic manipulator 180 is set up on the track 192,194 of being located at the motherboard upper strata, for example on the operator's 100 who sits down the crown.Operator 100 also uses the empty full reparation pallet 176 and VI pallet 178 of pallet displacement.
Track 192,194 is fixed in the x direction, y-track 196 is moved along the x direction.Therefore robot arm assembly 198 can move along y track 196 in the y direction, arrives desired position up to robot arm, for example the test jack on the breakout box plate or input or output pallet.Then, the electric hand arm on the robot arm assembly 198 can up move down, and module is extracted (up) or inserts (down) to test jack or tray.The mode that robot arm assembly 198 can rotate (rotate) or rotation (spin) moves to the position of wanting with this module.
Each motherboard substrate 30 has the memory module socket on test commentaries on classics device plate, this test adaptor device plate is connected to the module that is positioned at intermediate address (non-high address or the low order address of being positioned at).Then, when having defective as if the last module of tested storage that is inserted into test jack, this defective can be found out by the test procedure that operates on the motherboard.This defective will can not cause that motherboard decommissions.The memory under test module that this test macro host computer can guarantee to be inserted into motherboard is different with the capacity of known good memory module, to avoid interleaving access.
The another kind of aspect of implementing
The present inventor also finishes other and implements aspect.For example: as previously described, the memory under test module has a single defective 56, and test procedure can be found out a plurality of defectives in each memory under test module.By these defective locations, but the also kind of defect recognition, for example the delegation of defective or a row hint its be row fault or row fault.When all by the memory under test module on the data of a certain input and output pin of dram chip make a mistake, this mistake may be a welding mistake, and does not need to revise or repair to replace dram chip.Therefore the type of defect recognition can help correction work.
Some motherboard may have a plurality of storage channels, and its slot is arranged according to the required pattern of interleaving access.In in such cases, can use two test jacks 560, each test jack 560 has a memory under test module, and therefore two slots can carry out interleaving access, but its motherboard does not have any known good memory module.These slots can be logical slot but not entity can insert slot, and can be in explaining the memory configurations useful concept.Memory bus can be shared or separates.
The number of the test jack on the test adaptor device plate is not necessarily identical, and can add that add-on assemble is to test adaptor device plate.Also can use difference that mechanism and electrical assembly are set.Motherboard engages with test adaptor device plate with the angles of 60 to 120 degree in fact, but not with just be 90 spend or with the parallel mode of test adaptor device plate.
As previously described, but memory module socket self-test breakout box plate remove, test adaptor device plate is arranged on the motherboard face of weld.Perhaps, memory module can continue to insert in test jack and not remove.Then, test adaptor device plate can be the module expansion board, and this module expansion board is inserted into the test jack on the motherboard assembly face.The module expansion board comprises the test jack at little circuit board one edge, and in the resistance welding contact of opposite edge in order to the insert module socket.The memory under test module is inserted into the test jack of module expansion board.Similarly, the memory under test module can directly be inserted into the modular jack on the motherboard and must not used the module expansion board.
Test jack on the test adaptor device plate can be in order to accept memory assembly, and for example therefore the assembly of DRAM can allow to test the memory assembly that is added on memory module.
Can be arranged on the chassis near the test adaptor device plate 50 or fixedly on the sheet metals of motherboard substrate in order to the hot device of memory module in the heating test.Can use glass mat or other can be with the better isolation thing of motherboard self-test breakout box 50 electrical equipment temperature isolation.Cooling rifle or pressurized air (but not well heater) can be in order to cooling test cabinet and memory modules.
The wood invention can be tested many different types of memories modules.For example: use standard DRAM or newer expanding data output (extended data output; EDO) and the module of synchronous dram all can be tested, fully-buffered memory modules (fully-buffered memory modules; FB-DIMMs) also can be tested.This system especially is fit to test flank speed memory module, because the load capacity of two-forty memory module is minimized.Other storer is as RAMBUS module (module of being developed by RAMBUS company), Double Data Rate (double data rate; DDR) module and PCI33 synchronization module also can be tested.
All applicable this invention of the memory module of various different capabilities and different coefficients, replaceable breakout box plate not of the same race is to avoid being subject to test adaptor device plate and class well portion size.The setting of test adaptor device version and motherboard substrate can make skilled worker or operator replace beta version easily.The present invention also can use the motherboard of non-PC.The present invention can be applicable to arbitrary goal systems plate.Many test jacks can be arranged on each test adaptor device plate or the single motherboard, so that the multi-memory module can be simultaneously tested in identical motherboard.
Mountain one (Yamaichi) style connector can be used as test jack, and preferably, test jack can be turnout (production-quality) connector/socket, because of it only needs lower insertion force.Turnout connector/socket is than the insertion the used number of times of the conventional socket on the motherboard (about 100 times) more (about 100 times of conventional socket, turnout connector/socket is usually greater than 100,000 times).Produce socket and have displacer (ejector) usually in the socket two edges.This can slow down the injection when artificial or robot manipulation's module.Produce socket and also can comprise a V-type groove.Operator or robot arm can place module the recess of V-type groove, after placing, push away toward socket from the module top.The recess of V-type groove can reduce the required accuracy when module check of operator or mechanical hand people arm.
Robot arm can adopt many different technologies.The for example arm of swing or rotation, or even telescopic arm or use vertical servo control mechanism (vertical servo) in the arm end points.Another kind method can be used perhaps many different types of automatic pallet stacker of x-y-z tracing system or known electrical system.After inserting a new memory module, this test macro initially is with the hot-air warming-up in halted state.Memory module also can be inserted and test to treat it with hot-air being blown preheating to its module.The input pallet can heat earlier to finish preheating.
The operator looks tray and how long need be placed into or remove and operate a plurality of test boards simultaneously.Robot arm assembly 98 can add a plurality of arms, can be picked up simultaneously and move to allow two or more memory module.Test adaptor device plate can be adjusted to has two or more test jacks, with allow two or more multimode can on identical motherboard, test simultaneously.Motherboard then will be repaid that breaks down in two modules of main system interface.
In industrial standard (internet security and acceleration; ISA) or peripheral component interface (peripheral component interface; PCI) the network controller card of bus can be relayed to other bus, and not limited by the existing bus, and wherein the network control card is and main system interface or host communication.Control card can be parallel or alternative to the serial port interface of main system interface by a standard.Interface can use live wire, USB (universal serial bus) (universal Serial Bus; USB) or other existing standard.According to action in various degree, can use dissimilar robot arms and tracing system.Use different extracting technology memory module to be fixed in the robot arm.The testing station can be used string row (in tandem) or independently a plurality of separately robot arm.For example: a certain arm can be loaded into motherboard with module, second module unloading that arm will have been tested.
The possibility of recovery can be reprocessed and have to the memory module of test crash, for example: replace defective dram chip or weld the coupling part that comes loose once more.Few part in the module, for example 1%, may need reprocessing.Yet the dram chip amount of being produced by processing of wafers technology (wafer fab) is few sometimes, will cause failure rate soaring.Production sample can be used as another kind of another method of testing that receives low production line dram chip of surveying once in a while.This sampling method also can be surveyed the problem in the canned program simultaneously.
SPD-EEPROM 130 can integrate high speed storing impact damper (advanced memory buffer; AMB) or other buffer chip.Some type memory may not have SPD-EEPROM 130.Two-wire memory module (the fully-buffereddual-inline memory module that the present invention can be applicable to not have buffered memory modules, the memory module of buffering arranged, cushion fully; FB-DIMM) and comprise he that may use other type future and plant memory module.
Though only to the dram chip explanation, also the memory module of available other kind is replaced, as static RAM (static random access memory in the front; SRAM), the storer of nonvolatile memory or other kind.The present invention can be in conjunction with chip layer redundancy (chip-level redundancy) and DRAM producer's reparation.Can use built-in self testing (built-in-self-test; BIST) to check.
Different control signals may be utilized.Trace can be the interior trace of the interior layer of lip-deep metal line of memory module or multilayer board.Voice Interference Analysis System (Voice Interference Analysissystem; Vias), jumper coupler or other connector can form the part of electrical path.Can increase resistance, capacitor or other complex filter and other assembly in addition, for example: power supply-ground connection pass capacitor (power-ground bypass capacitors) can be attached to memory module.
Multiplexer (multiplexer; MUX) or switch can carry out loopback (loop-back) test and standard operation.The standard that the present invention extends the memory module standard and the memory module in future all has greatest help.
Technical background chapters and sections of the present invention are problem or the environmental information that comprises about the technology of the present invention background, but not other described prior art.Therefore technical background is not that the technical background chapters and sections content of being described by the applicant is only arranged.
Any method or program in this narration can be machine application and computer utility, and implements with machine, computing machine or other device, is not to assist and implement under the situation with independent manpower at no machine.Report or other are shown in the test result that display device (as computer screen, projector screen), message generation device and associated multimedia device all belong to (comprise by machine and produce the hard disk that prints off) entity by the machine generation.The computer control of other machine also is the test result of another kind of entity at last.
Though the present invention does explanation according to the exposure embodiment, for those of ordinary skill in the affiliated technical field, the present embodiment can have a plurality of variations, and these variations simultaneously are conspicuous, and are in spirit of the present invention and scope.Therefore, those of ordinary skill can be made many modifications in the affiliated technical field, and these modifications all are in the spirit and scope of the application's claim.
Claims (20)
1. a motherboard tester in order under the situation that memory module is decommissioned, is surveyed the defective in the memory module, it is characterized in that comprising:
Test adaptor device plate, has test jack, test jack is the memory under test module of being tested by the motherboard tester in order to engage, the memory under test module that test adaptor device plate will be inserted in the test jack is electrically connected to the motherboard that joins with test adaptor device plate, and motherboard partly uses main storer middle of the memory under test module in the test jack as motherboard;
Motherboard is the mainboard that is used for computing machine, and computing machine uses memory module as main storer;
First module slot is positioned on the motherboard and is connected to first memory modular jack on the assembly face of motherboard, and has the first known good memory module of having inserted;
Second module slot is connected to the position of second memory modular jack on the assembly face of motherboard and is connected to test adaptor device plate, and the memory under test module that wherein has been inserted in test jack on the test adaptor device plate is electrically connected to second module slot;
The three module slot is positioned on the motherboard and is electrically connected to the 3rd memory module socket on the assembly face of motherboard, and has the second known good memory module of having inserted;
The copy of Basic Input or Output System (BIOS) is stored in the second known good memory module;
Operating system image is stored in the first known good memory module;
Test procedure is stored in the first known good memory module, and wherein test procedure is performed by the processor on the motherboard, so that the memory location in the memory under test module can be read and write and can not cause motherboard to decommission; And
Defective locations is arranged in the memory under test module, and the test procedure that can be performed in processor identifies, and is reported to the user;
By this, test procedure identifies defective locations, and because of test procedure is not loaded in the memory under test module, so motherboard can not decommission.
2. motherboard tester according to claim 1, it is characterized in that motherboard main storer in the middle of partly be positioned between the storage address of the storage address of the access first known good memory module and the access second known good memory module, wherein the storage address of access memory under test module is positioned between the storage address of the storage address of the access first known good memory module and the access second known good memory module.
3. motherboard tester according to claim 2 is characterized in that during the start during execute store volume test Basic Input or Output System (BIOS) of stopping using.
4. motherboard tester according to claim 2, it is characterized in that Basic Input or Output System (BIOS) exists the serial of detection of stored device, the second known good memory module to exist the serial of detection of stored device and memory under test module to have the detection of stored device by the serial of reading the first known good memory module, judge stored configuration, wherein the memory under test module is that the copy of intermediate address and Basic Input or Output System (BIOS), operating system image or test procedure all do not have overlapping according to the access of intermediate address institute.
5. motherboard tester according to claim 2, it is characterized in that the memory under test module has memory span, the memory span of memory under test module is different from the memory span of the first known good memory module and the second known good memory module, wherein the memory span of memory under test module is different from the memory span of the first known good memory module and the second known good memory module, to prevent the interleaving access of memory under test module.
6. motherboard tester according to claim 2, it is characterized in that first memory modular jack and the 3rd memory module socket are installed on the assembly face of motherboard, the assembly mask has the expansion socket of integrated circuit and expansion board to be mounted thereon, and wherein test adaptor device plate is installed on the motherboard face of weld with respect to the assembly face.
7. motherboard tester according to claim 6 is characterized in that also comprising:
The four module slot is positioned on the motherboard and is connected to the 4th memory module socket on the assembly face of motherboard, and has the 3rd known good memory module of having inserted.
8. motherboard tester according to claim 6 is characterized in that also comprising:
The four module slot, be connected to the position of the 4th memory module socket on the assembly face of motherboard and be connected to test adaptor device plate, be inserted into wherein that the second memory under test module of second test jack is electrically connected to the four module slot on the test adaptor device plate;
Wherein, the second memory under test module is the intermediate store address institute access according to the storage address of storage address that is positioned at the first known good memory module and the access second known good memory module.
9. motherboard tester according to claim 2 is characterized in that motherboard is arranged in a plurality of motherboards, and each motherboard has test adaptor device plate and the test jack that does not cause motherboard to decommission in order to test memory under test module, and the motherboard tester also comprises:
The diagnostic system interface is coupled to a plurality of motherboards, tests the memory under test module that is inserted into test jack in order to the order motherboard, and from motherboard acceptance test result; And
Robot arm, the order in order to the response diagnostics system interface is inserted into test jack with memory module, with as the memory under test module, by this, motherboard can be tested the memory module that is inserted in test jack on the test adaptor device plate, and does not cause motherboard to decommission.
10. motherboard tester according to claim 1 is characterized in that test adaptor device plate is the module expansion board, and the module expansion board is inserted in the second memory modular jack on the assembly face of motherboard.
The memory module tester 11. an opposing decommissions is characterized in that comprising:
The robot device is in order to move to the output storehouse of testing memory module with memory module by the input storehouse of testing memory module not;
Principal computer is in order to the control robot device;
A plurality of testing stations, in order to the memory module that test loads and unloads by the robot device, each testing station comprises:
Test adaptor device plate;
Test jack is positioned on the test adaptor device plate, and test jack is in order to engage memory module, and memory module is inserted in test jack and is become the memory under test module by the robot device;
Motherboard is used for personal computer, and in order to the order of response principal computer, carries out test procedure and is inserted in memory module in the test jack with test;
First module slot is positioned on the motherboard, and first module slot is connected to the first memory modular jack on the assembly face of motherboard and has the first known good memory module of having inserted;
Second module slot is connected to the position of the second memory modular jack that has removed on the assembly face of motherboard and is connected to test adaptor device plate, and the memory under test module that wherein is inserted in test jack on the test adaptor device plate is electrically connected to second module slot;
The three module slot is positioned on the motherboard and is connected to the 3rd memory module socket on the assembly face of motherboard, and has the second known good memory module of having inserted;
The copy of Basic Input or Output System (BIOS) is stored in the second known good memory module; And
Operating system image is stored in the first known good memory module;
Wherein test procedure is stored in the first good memory module, and test procedure is performed by motherboard, so that the memory location in the memory under test module can be read and write and not cause motherboard to decommission;
By this, test procedure is not loaded in the memory under test module, so test procedure can be tested the memory under test module and do not cause motherboard to decommission.
The memory module tester 12. opposing according to claim 11 decommissions, it is characterized in that motherboard main storer in the middle of partly be positioned between the storage address of the storage address of the access first known good memory module and the access second known good memory module, wherein the storage address of access memory under test module is positioned between the storage address of the storage address of the access first known good memory module and the access second known good memory module.
The memory module tester 13. opposing according to claim 12 decommissions, it is characterized in that the memory under test module has memory span, the memory span of memory under test module is different from the memory span of the first known good memory module and the second known good memory module;
Wherein the memory span of memory under test module is different from the memory span of the first known good memory module and the second known good memory module, to prevent the interleaving access of memory under test module.
The memory module tester 14. opposing according to claim 12 decommissions is characterized in that each test adaptor device plate also comprises:
Second test jack is positioned on the test adaptor device plate, and in order to receive the second memory under test module, the second memory under test module is inserted into second test jack by the robot device;
Wherein motherboard is tested the memory under test module and the second memory under test module,
Each motherboard is tested two memory modules by this.
The memory module tester 15. opposing according to claim 12 decommissions is characterized in that each motherboard also comprises:
The four module slot, be connected to the position of the 4th memory module socket that has removed on the assembly face of motherboard and be connected to test adaptor device plate, wherein the second memory under test module is inserted into second test jack on the test adaptor device plate and is electrically connected to the four module slot;
Wherein, the second memory under test module is according to the storage address institute access between the storage address of storage address that is positioned at the access first known good memory module and the access second known good memory module.
16. a reliable multiple masters memory tester is characterized in that comprising:
The main system device is in order to the test of memory module on the control multiple masters;
A plurality of testing stations device, in order to the testing memory module, each testing station device comprises:
The test jack device is in order to engage the memory under test module to test;
The motherboard device is controlled by the main system device, in order to carry out test procedure is inserted into the test jack device with test memory under test module; And
Test adaptor device panel assembly is installed on the motherboard device, in order to the test jack device is electrically connected to the memory bus device that is positioned on the motherboard device;
The first module slot device is in order to the first known good memory module that connects the first memory modular jack on the motherboard device and be inserted in order to joint;
The second module slot device, reach in order to be connected to test adaptor device panel assembly in order to the position that is connected to the second memory modular jack that has removed on the motherboard device, the memory under test module that wherein is inserted into test jack device on the test adaptor device panel assembly is electrically connected to the second module slot device;
The three module slot apparatus is in order to the second known good memory module that is connected to the 3rd memory module socket on the motherboard device and is inserted in order to joint;
The copy of Basic Input or Output System (BIOS) is stored in the second known good memory module; And
Operating system image is stored in the first known good memory module;
Wherein test procedure is stored in the first known good memory module, and test procedure is performed by the motherboard device, so that the memory location of memory under test module can be read and write and do not cause motherboard to decommission,
Wherein, reliable multiple masters memory tester has a plurality of motherboard devices, each motherboard device has additional testing breakout box panel assembly, and additional testing breakout box panel assembly has the test jack device, and each motherboard device is in order to the memory under test module of executed in parallel test procedure in other motherboard assembly;
Test by this memory under test module and because test procedure be not loaded in the memory under test module, so do not cause the motherboard device to decommission.
17. reliable multiple masters memory tester according to claim 16 is characterized in that also comprising:
Defective locations is arranged in the memory under test module, and its test procedure that can be performed in the motherboard device identifies, and is reported to the main system device;
Test procedure identifies defective locations by this, and because test procedure is not loaded in the memory under test module, so do not cause the motherboard device to decommission.
18. reliable multiple masters memory tester according to claim 17, the centre that it is characterized in that the main storer of motherboard device partly are to be positioned between the storage address of the storage address of the access first known good memory module and the access second known good memory module;
Wherein the storage address of access memory under test module is positioned between the storage address of the storage address of the access first known good memory module and the access second known good memory module.
19. reliable multiple masters memory tester according to claim 18, it is characterized in that the memory under test module has memory span, the memory span of memory under test module is different from the memory span of the first known good memory module and the second known good memory module;
Wherein the memory span of memory under test module is different from the memory span of the first known good memory module and the second known good memory module, in order to prevent the interleaving access of memory under test module.
20. reliable multiple masters memory tester according to claim 16 is characterized in that also comprising:
The robot device, controlled by the main system device, in order to grasp memory module and memory module be inserted into the test jack device, after test procedure is finished, the robot device grasps memory module and shifts out memory module in order to the self-test socket device, after motherboard device indication main system device memory module is passed through test procedure, the memory module that the robot device has also tested with storage to output unit in order to the mobile memory module;
Robot device's mobile memory module by this.
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| CN200910003802A CN101794624A (en) | 2009-02-01 | 2009-02-01 | Failure diagnosis of serial addressing memory module of personable computer mainboard |
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| CN102456416A (en) * | 2010-10-28 | 2012-05-16 | 维瀚科技有限公司 | Vertical test equipment for electronic assemblies |
| CN102455406A (en) * | 2010-11-01 | 2012-05-16 | 维瀚科技有限公司 | Switching test device for electronic component |
| CN104615518A (en) * | 2015-03-04 | 2015-05-13 | 浪潮集团有限公司 | Memory rank margin test method combining temperature and voltage variables |
| TWI561838B (en) * | 2015-09-08 | 2016-12-11 | Inventec Corp | Testing device of address configuration signal of dimm slot and testing method thereof |
| CN107179452A (en) * | 2016-03-10 | 2017-09-19 | 易宝股份有限公司 | Combined slot and bottom plate identification |
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| CN102456416B (en) * | 2010-10-28 | 2014-10-08 | 维瀚科技有限公司 | Vertical test equipment for electronic assemblies |
| CN102455406A (en) * | 2010-11-01 | 2012-05-16 | 维瀚科技有限公司 | Switching test device for electronic component |
| CN104615518A (en) * | 2015-03-04 | 2015-05-13 | 浪潮集团有限公司 | Memory rank margin test method combining temperature and voltage variables |
| TWI561838B (en) * | 2015-09-08 | 2016-12-11 | Inventec Corp | Testing device of address configuration signal of dimm slot and testing method thereof |
| CN107179452A (en) * | 2016-03-10 | 2017-09-19 | 易宝股份有限公司 | Combined slot and bottom plate identification |
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