CN101794330B - Verification method of integrated circuit and system thereof - Google Patents
Verification method of integrated circuit and system thereof Download PDFInfo
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- CN101794330B CN101794330B CN2009102441722A CN200910244172A CN101794330B CN 101794330 B CN101794330 B CN 101794330B CN 2009102441722 A CN2009102441722 A CN 2009102441722A CN 200910244172 A CN200910244172 A CN 200910244172A CN 101794330 B CN101794330 B CN 101794330B
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Abstract
The invention relates to a verification method of an integrated circuit and a system thereof. The method comprises the following steps of: firstly, abstracting an integrated circuit to be verified by an abstraction engine to generate a corresponding abstraction model and carrying out formalization calculation; secondly, initializing an excitation generation engine and establishing a Markov model based on specifications of the integrated circuit to be verified; thirdly, generating excitation of the excitation generation engine by the Markov model, inputting the excitation into a simulator and carrying out simulation on the integrated circuit to be verified by the simulator; fourthly, comparing a simulation result of current period and a simulation result obtained in the last period by the excitation generation engine based on formalization information, if the simulation result of the current period is nearer to a target state, regulating parameters in the Markov model; and fifthly, if the integrated circuit to be verified does not achieve the target state and the simulation time does not exceed the preset time, executing third step, and otherwise, stopping the simulation and reporting success or overtime running. The invention can lower the calculation cost and enhance the detection efficiency.
Description
Technical field
The present invention relates to large scale integrated circuit checking field, relate in particular to integrated circuit verification method and system thereof.
Background technology
Along with developing rapidly of IC industry, the diversity of design and complicacy degree are also more and more higher, and the growth of design scale that the traditional function verification method is handled and efficient lags behind the growth of exploitation scale, and it is difficult increasing to make that it faces.
The integrated circuit complicacy increases a difficult problem of bringing to functional verification and comprises two aspects: the first design built-in function logic, interface protocol, exception processing or the like complexity sharply increases, and relies on artificial experience or existing method to be difficult to handle; The register number that comprises in second integrated circuit structure increases, and causes simulation speed more and more slower, makes that formalization verification method is difficult to handle more.In order to solve or to alleviate above-mentioned two problems, the integrate circuit function verification method need reduce the human expert knowledge that needs as far as possible, and generates short test vector, to drive the specific functional attributes of simulating, verifying.
In addition, in existing integrated circuit verification flow process, the increase of the function coverage of design is not linear, and especially the difficulty for design reaches attribute or state, often expends a large amount of checking costs and produces little effect.At the difficult checking that reaches attribute or state in the integrated circuit, be a urgent problem.The function verification method of existing integrated circuit mainly is divided into simplation verification and formalization checking two big class methods.
Simulation verification method is mainly by carrying out emulation for design input test vector, and result and correct golden model (Golden Model) of function of emulation compared, with the function correctness of checking design under different input stimulus situations.Simulation verification method can be verified the design attributes that some are common fast, but for the edge attributes that is difficult to arrive, is difficult to cover in finite time and verify.Verify the specific function point though can write test vector, need expend the great amount of manpower time, and test vector is difficult to reuse between different designs by artificial craft, can not be as main checking means.
In the formalization verification method, mainly be model testing (Model Checking) method, relatively be suitable for the edge attributes of design is verified.In these class methods, integrated circuit (IC) design is conceptualized as a Finite State Model, objective attribute target attribute then is described to a temporal logic formula, and the process of checking is the accessible state in the traversal Finite State Model, thereby the proof integrated circuit (IC) design satisfies objective attribute target attribute; Perhaps provide the counter-example of a status switch form, can not satisfy with the proof objective attribute target attribute.Model testing has standardization, is easy to robotization, characteristics completely, but wherein the state space size causes " state explosion " with register number exponential increase (2^n) in the design; This also is the root problem that puzzlement model testing method is applied in the large-scale industry design.
By dividing other relative merits and the analysis that adapts to scene to simplation verification and formalization verification method, but can find a kind of method that improves verification efficiency and checking Treatment Design scale: formalization checking and simulation verification method are combined, on original design, carry out to a certain degree abstract, on abstract model, obtain partial design information with formalization verification method, generate short artificial vector with these information guide analog simulations then, thereby authenticate to the design edge attributes of target fast and accurately.Can reduce the cost that formalization method calculates by abstract, the design information of Huo Deing can help to improve the efficient of objective attribute target attribute being carried out simplation verification simultaneously.
Take the verification method of this optimization, it is abstract that problem is how circuit to be carried out, and can make the abstract model of acquisition less and comprise design information more accurately.Simple and direct method is by the understanding of slip-stick artist to integrated circuit (IC) design, and artificial part and the maximally related logic of target extracted is as abstract model.This method is better for medium and small design effect, but for somewhat complex design then effect can not get guaranteeing, and need a large amount of expert's times, be not suitable for the demand of robotization checking.Another kind method is then based on the thought of modern integrated circuits module design, extract and design module that the signal relation of dbjective state correspondence is close as abstract model.If but module is bigger, then cause abstract model too complicated, and the abstract granularity of this method is bigger, not ideal enough.Adopt data digging method in addition, in integrated circuit (IC) design, excavate relation between each register-bit, register-bit in close relations is added abstract model.This kind method is carried out on register-bit (bit) level, and is not suitable for the needs of register transfer level functional verification.
In addition, how utilizing and carry out the information that formalization calculates guide simplation verification to cover the design attributes of target fast on abstract model, also is a difficult problem.A kind of feasible method is, with the formalization computing method abstract model of design is described as a state space, calculate from dbjective state preceding picture forward, and with the distance of picture before this as approximate assessment to state.Utilize the range information that calculates acquisition on the abstract model to the analog simulation channeling conduct, its core just is to encourage the strategy that generates engine and guiding how to design.Existent method, what mostly adopt is at random excitation producing method, generates N cycle tests at every turn, then with abstract range information assess these sequence emulation the state quality that can arrive, therefrom the minimum sequence of the selection abstract distance of arrival is carried out emulation.The method that also has adopts genetic algorithm and cultural algorithm to generate engine as excitation, utilizes the fitness function of abstract range information design population.Cultural algorithm is the strategy of a kind of " selecting excellent in excellent " in essence, promptly selects individual procreation of future generation from good population, in the hope of better population quality; But this method is learning knowledge from artificial intelligence in the past not, and does not well utilize the information of design specifications, and its efficient can have further raising.
Use the hybrid verification method list of references 1 at the integrated circuit edge attributes of abstract distance guiding, Distance-Guided Hybrid Verification with GUIDO Design, Proceedings onDesign, Automation and Test in Europe 2006.Munich, Germany:IEEE, 2006:1-6; Document 2, Guiding simulation with increasingly refined abstracttraces, Proceedings on Design Automation Conference, 2006.Anaheim, California, USA:ACM/IEEE, 2006:737-742; Document 3, An effective guidancestrategy for abstraction-guided simulation, Proceedings on DesignAutomation Conference, 2007.San Diego, California, USA:ACM/IEEE, 2007:63-68; Document 4, Efficient Design Validation Based on Cultural Algorithms, Proceedings on Design, Automation and Test in Europe 2008.Munich, Germany:IEEE, 2008:402-407.
Summary of the invention
For addressing the above problem, the invention provides integrated circuit verification method and system thereof, can reduce assessing the cost, improve detection efficiency.
The invention discloses a kind of integrated circuit verification method, comprising:
Step 1, abstract engine carries out abstract to integrated circuit to be verified, generate corresponding abstract model, and carries out formalization and calculate on described abstract model, to obtain formalization information;
Step 3, excitation generates engine and generates excitation by Markov model, and with described excitation input emulator, described emulator carries out emulation to described integrated circuit to be detected;
Step 4, described excitation generate engine and compare the simulation result of this cycle simulation result and last cycle emulation acquisition according to described formalization information, if this cycle simulation result more near dbjective state, is then adjusted parameter in the described Markov model;
Step 5 if integrated circuit miss the mark state to be detected and simulation times do not surpass preset times, is then carried out described step 3; Otherwise, stop emulation, and report success or move overtime.
Described step 1 further is,
Step 21 is set up the data dependency graph;
Step 22 is carried out abstractly on described data dependency graph, generates abstract model;
Step 23 is carried out formalization and is calculated on described abstract model, obtain formalization information.
Described step 21 further is,
Step 31 according to the description of the hardware description language of integrated circuit to be detected, is set up the data dependency graph according to the dbjective state variable of storage dbjective state; In the described data dependency graph, each node is represented a register variable, and the oriented arrow between two nodes represents that there is data dependence relation in destination node to the source node.
Described step 22 further is,
Step 41 in described data dependency graph, from the dbjective state variable, according to logic dependence recalling from the close-by examples to those far off, and adopts the BFS (Breadth First Search) mode that the register variable that traverses is joined abstract model; If two exist the register variable of dependence to be added in the described abstract model, then the combinational logic between two described register variables also is added in the described abstract model.
Described step 22 further is,
Step 51, in described data dependency graph, described dbjective state variable is divided into group, dbjective state variable from each group, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode register variable that traverses to be joined in the corresponding sub-abstract model of abstract model; If two exist the register variable of dependence to be added in the described sub-abstract model, then the combinational logic between two described register variables also is added in the described sub-abstract model.
Described step 23 further is,
Step 61, employing is carried out formalization calculating based on the formalization computational tool of two fens decision diagrams on described abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table, described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
Described step 23 further is,
Step 71, employing is carried out formalization calculating based on the formalization computational tool of two fens decision diagrams on each described sub-abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table of described sub-abstract model correspondence, described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
Described step 3 further is,
Step 81, described excitation generated engine before each cycle of emulation, generated the excitation of one-period according to the current configuration of Markov model, and offered emulator and carry out emulation.
Described step 4 further is,
Step 91, from described abstract range information table, search the abstract distance of simulation result correspondence, compare the simulation result in a same emulation cycle of this cycle simulation result according to described abstract distance, if comparative result is that this cycle simulation result is more near dbjective state, then execution in step 92, otherwise, carry out described step 5;
Step 92 increases the weight on the pairing limit of excitation of current simulation result in the Markov model, and reduces the weight on other limits in the described Markov model so that weight and be 1 in the limit that in the Markov model set out in summit is carried out described step 5.
Described step 4 further is,
Step 101 is searched the abstract distance of simulation result correspondence from described abstract range information table, calculate the fitness of simulation result in sub-abstract model according to following formula,
fit
i＝Max
i-D
i
Fit
iBe the fitness value of simulation result in each sub-abstract model; D
iThe abstract distance of the correspondence that in the abstract range information table of described sub-abstract model, finds for simulation result, Max
iMaximum abstract distance value for described sub-abstract model;
Step S102 is calculated as follows the fitness of simulation result,
V
iBe the dbjective state variable number that comprises in the sub-abstract model; V
TotalTotal dbjective state variable number of expression abstract model; N
PThe quantity of representing sub-abstract model, Fitness_value represents the fitness value of this cycle simulation result;
Step S103, the fitness of the simulation result correspondence in a same emulation cycle of fitness of this cycle simulation result correspondence relatively, if comparative result be this cycle simulation result more near dbjective state, then execution in step 104, otherwise, carry out described step 5;
Step 104 increases the weight on the pairing limit of excitation of current simulation result in the Markov model, and reduces the weight on other limits in the described Markov model so that weight and be 1 in the limit that in the Markov model set out in summit is carried out described step 5.
The invention discloses a kind of integrated circuit verification system, comprising:
Abstract engine is used for integrated circuit to be verified is carried out abstract, generates corresponding abstract model, and carries out formalization and calculate on described abstract model, to obtain formalization information;
Excitation generates engine and comprises that Markov model sets up module, excitation generation module, parameter adjustment module, checking reporting module as a result,
Described Markov model is set up module, is used for the Markov model of setting up according to the standard of integrated circuit to be detected;
Described excitation generation module is used for generating excitation by Markov model, with described excitation input emulator;
Described emulator is used for described integrated circuit to be detected is carried out emulation;
Described parameter adjustment module is used for the simulation result that the described formalization information of foundation compares this cycle simulation result and last cycle emulation acquisition, if this cycle simulation result more near dbjective state, is then adjusted parameter in the described Markov model;
Described checking is reporting module as a result, is used for starting when integrated circuit miss the mark state to be detected and simulation times surpass preset times described excitation generation module; Otherwise, stop emulation, and report success or move overtime.
Described abstract engine is further used for setting up the data dependency graph; On described data dependency graph, carry out abstractly, generate abstract model; On described abstract model, carry out formalization and calculate, obtain formalization information.
Described abstract engine is further used for the description according to the hardware description language of integrated circuit to be detected when setting up the data dependency graph, set up the data dependency graph according to the dbjective state variable of storage dbjective state; In the described data dependency graph, each node is represented a register variable, and the oriented arrow between two nodes represents that there is data dependence relation in destination node to the source node.
Described abstract engine is further used in described data dependency graph when generating abstract model, from the dbjective state variable, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode that the register variable that traverses is joined abstract model; If two exist the register variable of dependence to be added in the described abstract model, then the combinational logic between two described register variables also is added in the described abstract model.
Described abstract engine is further used in described data dependency graph when generating abstract model, described dbjective state variable is divided into group, dbjective state variable from each group, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode register variable that traverses to be joined in the corresponding sub-abstract model of abstract model; If two exist the register variable of dependence to be added in the described sub-abstract model, then the combinational logic between two described register variables also is added in the described sub-abstract model.
Described abstract engine is carrying out being further used for adopting the formalization computational tool based on two fens decision diagrams to carry out formalization calculating when formalization is calculated on described abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table, and described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
Described abstract engine is carrying out being further used for adopting the formalization computational tool based on two fens decision diagrams to carry out formalization calculating when formalization is calculated on each described sub-abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table of described sub-abstract model correspondence, described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
Described excitation generation module was further used for before each cycle of emulation, generated the excitation of one-period according to the current configuration of Markov model, and offered emulator and carry out emulation.
Described parameter adjustment module is further used for searching the abstract distance of simulation result correspondence from described abstract range information table, compare the simulation result in a same emulation cycle of this cycle simulation result according to described abstract distance, if comparative result is that this cycle simulation result is more near dbjective state, then increase the weight on the pairing limit of excitation of current simulation result in the Markov model, and the weight that reduces other limits in the described Markov model is so that weight and be 1 in the limit that in the Markov model set out in summit, and starts described checking reporting module as a result; Otherwise, directly start described checking reporting module as a result.
Described parameter adjustment module is further used for searching the abstract distance of simulation result correspondence from described abstract range information table, calculate the fitness of simulation result in sub-abstract model according to following formula,
fit
i＝Max
i-D
i
Fit
iBe the fitness value of simulation result in each sub-abstract model; D
iThe abstract distance of the correspondence that in the abstract range information table of described sub-abstract model, finds for simulation result, Max
iMaximum abstract distance value for described sub-abstract model; Be calculated as follows the fitness of simulation result,
V
iBe the dbjective state variable number that comprises in the sub-abstract model; V
TotalTotal dbjective state variable number of expression abstract model; N
PThe quantity of representing sub-abstract model, Fitness_value represents the fitness value of this cycle simulation result;
The fitness of the simulation result correspondence in a same emulation cycle of fitness of comparison this cycle simulation result correspondence, if comparative result is that this cycle simulation result is more near dbjective state, then increase the weight on the pairing limit of excitation of current simulation result in the Markov model, and the weight that reduces other limits in the described Markov model is so that weight and be 1 in the limit that in the Markov model set out in summit, and starts described checking reporting module as a result; Otherwise, directly start described checking reporting module as a result.
Beneficial effect of the present invention is, by using Markov model and regulating Markov model according to simulation result and can reduce and assess the cost, improve detection efficiency, can the bigger integrated circuit of treatment scale, avoided the limited problem of existing formalization verification method treatment scale; And improved at the integrated circuit difficulty and reached the efficient that attribute encourages generation, shortened the length of verifying required excitation vector, on average improved more than 10 times than existing half formalization verification method efficient.
Description of drawings
Fig. 1 is the process flow diagram of integrated circuit verification method of the present invention;
Fig. 2 is the data dependency graph set up from design description and the abstraction process synoptic diagram on the data dependency graph;
Fig. 3 is the circuit state transition diagram and the corresponding abstract distance expression of abstract range information table correspondence in the embodiment;
Fig. 4 is the Markov model synoptic diagram of setting up from design specifications;
Fig. 5 is the structural drawing of integrated circuit verification of the present invention system.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The flow process of the inventive method as shown in Figure 1.
Step S100, abstract engine carries out abstract to integrated circuit to be verified, generate corresponding abstract model, and carries out formalization and calculate on described abstract model, to obtain formalization information.
Abstract method need done a compromise aspect abstract accuracy and the abstract scale, relevant logic is many more because if the model that takes out comprises objective attribute target attribute, its abstract quality and accuracy are good more, but corresponding model scale also increases, and causing that it is carried out formalization, to calculate required cost also big more; Relevant logic is few more if the model that takes out comprises objective attribute target attribute, and to calculate required cost more little though carry out formalization, and the design relevant information that comprises is also few more inaccurate more, thereby can't provide enough guidances for follow-up excitation generates.
Abstract method in the embodiment is based on the register transfer level, in the design of the described integrated circuit of hardware description language, carries out abstract according to the logic dependence of register variable.Particularly, the target design attribute is described to a dbjective state, and this dbjective state is by one group of register-stored, and these registers are called as the dbjective state variable.
State variable is one group of register, and the value that design point is preserved by these registers is formed.
For example, the totalizer carry is overflowed and is described to corresponding spill over variable and puts 1 state, and the spill over register then becomes the dbjective state variable.Therefore the logic that logically is closely related with those dbjective state variablees is useful core logic.
The embodiment of described step S100 is as described below.
Step S110 sets up the data dependency graph.
Hardware description language according to integrated circuit to be detected is described, and the surrounding target state variable is set up the data dependency graph.In the data dependency graph, each node is represented a register variable, and the oriented arrow between two nodes represents that there is data dependence relation in destination node to the source node.
Step S120 carries out abstractly on the data dependency graph, generates abstract model.
In the data dependency graph,,, and adopt the BFS (Breadth First Search) mode that the register variable that traverses is joined abstract model according to logic dependence recalling from the close-by examples to those far off from the dbjective state variable.If two exist the register variable of dependence to be added in the abstract model, then combinational logic between the two also is added in the abstract model accordingly.
In another embodiment, abstract method also adopts the method that abstract model is divided into a plurality of sub-abstract models, when abstract model larger, when surpassing the acceptable boundary, according to the contact tightness degree between the register, abstract model is divided into a plurality of sub-abstract models, and wherein each sub-abstract model all is the abstract model that obtains through preceding method forward from part dbjective state variable.
The embodiment of data dependency graph of setting up and the abstraction process on the data dependency graph as shown in Figure 2.Among Fig. 2, each circle is represented register in the integrated circuit to be detected, and the oriented arrow between the circle is represented the data dependence relation of the existence from destination node to the source node, and the most right-hand node is dbjective state variable R 1, dbjective state variable R 2, dbjective state variable R 3.Thereby the abstract process of circuit is specially, and in the data dependency graph, from the dbjective state variable, according to logic dependence recalling from the close-by examples to those far off, adopts the BFS (Breadth First Search) method that the register variable that traverses is joined abstract model; If two exist the register of dependence to be added in the abstract model, then combinational logic between the two also is added in the abstract model accordingly.When abstract model is larger, according to the contact tightness degree between the register, abstract model is divided into a plurality of sub-abstract models, and wherein each sub-abstract model all comprises the dbjective state variable of part, for example sub-abstract model 1 among Fig. 2 and sub-abstract model 2.
The abstract granularity of this kind abstract method is thinner, and the degree of depth by the control BFS (Breadth First Search), can control the size and the scale of abstract model flexibly, take out more precise analytic model if desired and can bear more formalization and assess the cost, then strengthen search depth, more logic around the extracting objects state variable, thus a more accurate abstract model obtained; Otherwise if fruit does not need abstract model too accurately, the formalization calculation cost that perhaps can accept is limited, then selects less search depth, thereby obtains comparatively coarse but a abstract model that scale is less.
S130 carries out formalization and calculates on abstract model, obtain formalization information, and this formalization information is saved as abstract range information table.
Employing is carried out formalization calculating based on the formalization computational tool of two fens decision diagrams on abstract model, obtain formalization information, and formalization information is recorded in the abstract range information table, and formalization information comprises the abstract distance of abstract state and abstract state correspondence.
In the embodiment, employing was based on two fens decision diagram (BDD, Binary Decision Diagram) formalization computational tool begins to calculate the preceding picture of this dbjective state abstract model from dbjective state, and will calculate all before as state and corresponding before image distance from preserving.Be an abstract state as state before each is described, preceding image distance is from being abstract distance.Abstract range information table is preserved abstract state and corresponding abstract distance, and is as shown in table 1, each the row a certain abstract distance value of representative and corresponding abstract state thereof in the table, and a plurality of abstract states can be assisted description with the X position.The abstract state set of abstract distance value maximum has comprised the original state of circuit, so the abstract distance value of circuit initial state correspondence is maximum abstract distance value.
Table 1
What Fig. 3 represented is and pairing circuit state transition diagram of table 1 and corresponding abstract distance.Wherein 000 shape, 0 attitude is the initial state of circuit, and 1111 states are dbjective states, and the state that does not have to occur in the drawings is an inaccessible state, also is illegal state.Calculate preceding picture forward from dbjective state, one to clap with the interior state abstraction distance that can arrive dbjective state be 1, pushing away in this, till arriving initial state (promptly 0000).This abstract range information is organized and is kept in the abstract range information table.Calculate preceding picture method as document Hardware Design Verification:Simulation and FormalMethod-Based Approaches about adopting based on the method for two fens decision diagrams, William K.Lam, Person Education, Inc is described in 2005..
Abstract model is divided into the situation of a plurality of sub-abstract models, employing is carried out formalization calculating based on the formalization computational tool of two fens decision diagrams on each described sub-abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table of described sub-abstract model correspondence, described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
Step S200, excitation generates the Markov model that the engine initialization is set up according to integrated circuit standard to be detected.
Standard (Specification) according to integrated circuit to be detected is set up corresponding Markov model, and Markov model is carried out initialization.The Markov model that utilization obtains generation at random meets the excitation of integrated circuit (IC) design standard.The synoptic diagram of Markov model and method for building up are as shown in Figure 4.
The design specifications of integrated circuit is meant a standard of determining and requires document before design circuit.
What represent among Fig. 4 is the Markov model structure of setting up according to a processor design specifications.Markov model is made up of the heavy directed edge of the full cum rights that links to each other between summit and the summit; Affairs like affairs (transaction) of each summit representative design or the category, and the probability that the weight representative on every directed edge is shifted from the source node to destination node.
When the excitation that is applied to processor for example generates in the engine, a kind of instruction (NOP) or class instruction are represented in each summit, as the mark in the summit among Fig. 4, for example Float floating-point operation, Branch branch instruction etc., Markov model are transferred to another summit and are then represented and produce a corresponding instruction from a summit.Under the original state, the summit is to link to each other in twos in the Markov model, and equates from the weight on all limits, represents any next summit of transferring at random.From all limit weight sums on a summit is 1, and the probability sum that expression is shifted to next summit is 1.
Step S300, excitation generates engine and generates excitation by Markov model, and with described excitation input emulator, emulator carries out emulation to integrated circuit to be detected.
Before each cycle of emulation, generate the excitation of one-period and offer emulator according to the current configuration of Markov model and carry out emulation.
Step S400, excitation generates engine and compares the simulation result of this cycle simulation result and last cycle emulation acquisition according to formalization information, if this cycle simulation result more near dbjective state, is then adjusted parameter in the described Markov model.
Excitation generates engine and utilizes abstract range information table to calculate the fitness function value of current state, and the fitness function value of the same cycle emulation of fitness function value of this cycle of being about to emulation of going forward side by side compares, and generates corresponding feedback signal according to comparative result; According to feedback signal the probability parameter of Markov model is adjusted.
The more little distance objective state of then representing of the abstract distance value of current state is near more, if distance is 0, then expression has arrived dbjective state.And by shown in the formula (1), fitness function value and abstract distance value are inversely proportional to, the abstract distance value that just outstanding more state correspondence is more little, and then corresponding big more fitness function value.Increased if the fitness function value of the state of current simulation result was compared with the value of last one-period, then expression is progressive, generates corresponding feedback signal, according to feedback signal the probability parameter of Markov model is adjusted; Otherwise do not produce feedback signal, do not adjust.
Produce legal excitation vector according to Markov model, each is clapped by the feedback adjusting Markov model in emulation, thereby produces higher-quality excitation vector.Therefore the core of this workflow is the generation of dynamic feedback in the simulation process and to the adjustment strategy of Markov model.
The embodiment of described step 400 is as described below.
S410, from abstract range information table, search the abstract distance of simulation result correspondence, compare the simulation result in a same emulation cycle of this cycle simulation result according to abstract distance, if comparative result is that this cycle simulation result is more near dbjective state, execution in step S420 then, otherwise, carry out described step S500.
In a kind of embodiment, from abstract range information table, search the abstract distance of simulation result correspondence, calculate corresponding fitness function value, the fitness value of the simulation result correspondence in a same emulation cycle of fitness value of comparison this cycle simulation result correspondence, the fitness value of simulation result correspondence is higher if comparative result is this cycle, execution in step S420 then, otherwise, execution in step S500.
The embodiment that is divided into sub-abstract model for abstract model is as described below.
A sequential circuit comprises the register of some, and then the state of this circuit is by the unique expression of the combination of these register values.For ask for the process of the fitness value of state according to abstract range information table, it is outstanding more that big more then this state of fitness value is assessed as to the assessment strategy of state, this fitness value by formula 1 and formula 2 calculate.
Fit
i=Max
i-D
iFormula (1)
Because abstract model may comprise a plurality of sub-abstract models, then fit
iIt is the fitness value in each sub-abstract model; By searching abstract range information table, obtain the abstract distance D of current simulation result correspondence
i, Max
iThe maximum abstract distance value of representing this sub-abstract model, maximum abstract distance value are abstract distance maximum in the abstract range information table of this sub-abstract model correspondence.
Total fitness value is then obtained by the fitness value calculation of all sub-abstract models, wherein the V in the formula (2)
iRepresent the dbjective state variable number that comprises in the sub-abstract model; V
TotalTotal dbjective state variable number of expression abstract model; N
PThe quantity of representing sub-abstract model, Fitness_value represents the fitness value of this cycle simulation result.Therefore fitness value is big more shows that current simulation result is more near dbjective state.
For the situation that abstract model is not divided into a plurality of sub-abstract models, calculate fitness value by following formula (5).
Fitness_value=Max-D formula (5)
Fitness_value represents the fitness function value of this cycle simulation result, and Max represents maximum abstract distance value, and D is the abstract distance of simulation result correspondence.If the fitness value of the state correspondence in the current emulation cycle is compared the fitness value of one-period raising is arranged, then current state is be evaluated as " outstanding ", represents to dbjective state near a step.Thereby a feedback signal, Markov model is adjusted.
For the situation that abstract model is not divided into a plurality of sub-abstract models, also can by direct more abstract distance judge this cycle simulation result whether than simulation result of last cycle more near dbjective state.
S420 increases the weight on the pairing limit of excitation of current simulation result in the Markov model, and reduces the weight on other limits in the described Markov model so that weight and be 1 in the limit that in the Markov model set out in summit.
The embodiment one of performing step S420
In the excitation generative process, be that the weight on limit realizes by adjusting wherein to the adjustment of Markov model.The feedback that produces in the simulation process represents that current state is " outstanding ", then increases the weight on the limit in the pairing Markov model of the excitation that causes current state in the Markov model.Thereby in excitation generation subsequently, similar outstanding excitation more likely is generated, and generates quality thereby improve excitation.But because from all limit weights on a summit be 1, the weight that increases a limit then must reduce the weight on other limit.
Specifically, the adjustment strategy to Markov model can be described as:
P
j Decr=k * (P
j-P
Min) formula (4)
Wherein, P
IncrRepresent the weight that the limit in the pairing Markov model of excitation of current simulation result increases, P
MaxFor every limit of regulation can weighting heavy maximal value, P
iBe the current weighted value on the limit in the pairing Markov model of the excitation of current simulation result, N
vNumber for all summits in the Markov model.
Like this, it is just difficult more that weight can be continued to increase in the limit that current weight is big more, the limit that current weight is more little, and it is just easy more to increase weight, thereby reaches a dynamic balance.
P
j DecrExpression is from the limit on a summit, and the weight that the limit the limit in the pairing Markov model of the excitation of current simulation result need deduct is so that from all limit weights on a summit be 1.For example, from a summit N bar limit is arranged, wherein limit i is the limit in the pairing Markov model of excitation of current simulation result, limit j is remaining limit of removing trimming i in the N bar limit, because the weight of limit i is increased, thereby reduces the weight of limit i, so that the weight on N bar limit adds and be 1.
P
jFor this need reduce the current weighted value in limit of weight, P
MinFor every limit of regulation can weighting heavy minimum value, k is to make from all limit weights on a summit and is 1 coefficient.Said process is a normalization process, and like this, the weighted value that the limit normalization that current weight is big more deducts is many more, and the weighted value that the limit normalization that current weighted value is more little deducts is few more.
By described dynamic adjustment, Markov model is not easy to be absorbed in local optimum, to such an extent as to local optimum can form dynamic balance for big especially other limit of certain bar limit weight loses the chance that is traveled through, obtain better machine learning effect and generate to instruct excitation.
The embodiment two of performing step S420
Adjustment strategy to Markov model is that the weight that the limit in the pairing Markov model of the excitation of current simulation result increases is a preset value;
In the limit of setting out in summit, the weight that the limit the limit in the pairing Markov model of the excitation of current simulation result need deduct is calculated as follows:
P
j decr＝k×(P
j)
P
j DecrExpression is from the limit on a summit, and the weight that the limit the limit in the pairing Markov model of the excitation of current simulation result need deduct is so that from all limit weights on a summit be 1.P
jFor this need reduce the current weighted value in limit of weight.
The embodiment three of performing step S420
From the limit on a summit, the weight on the limit in the pairing Markov model of the excitation of current simulation result increases to weight limit value 1, and all the other limit weights are minimal weight value 0.
Step S500 is not if integrated circuit miss the mark state to be detected and simulation times surpass preset times, then execution in step S300; Otherwise, stop emulation, and report success or move overtime.
Stop emulation because of integrated circuit to be detected reaches dbjective state, then report successfully; Do not stop emulation because of simulation times surpasses preset times, then the report operation is overtime.
A kind of integrated circuit verification system, as shown in Figure 5.
Excitation generates engine 200 and comprises: Markov model is set up module 210, excitation generation module 220, parameter adjustment module 230, checking reporting module 240 as a result.
Markov model is set up module 210, is used for the Markov model of setting up according to the standard of integrated circuit to be detected.
Checking reporting module 240 as a result is used for starting described excitation generation module 220 when integrated circuit miss the mark state to be detected and simulation times surpass preset times; Otherwise, stop emulation, and report success or move overtime.
Preferable, abstract engine 100 is further used for setting up the data dependency graph; On described data dependency graph, carry out abstractly, generate abstract model; On described abstract model, carry out formalization and calculate, obtain formalization information.
In the embodiment one, abstract engine 100 is further used in described data dependency graph when generating abstract model, from the dbjective state variable, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode that the register variable that traverses is joined abstract model; If two exist the register variable of dependence to be added in the described abstract model, then the combinational logic between two described register variables also is added in the described abstract model.
In the embodiment two, abstract engine 100 is further used in described data dependency graph when generating abstract model, described dbjective state variable is divided into group, dbjective state variable from each group, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode register variable that traverses to be joined in the corresponding sub-abstract model of abstract model; If two exist the register variable of dependence to be added in the described sub-abstract model, then the combinational logic between two described register variables also is added in the described sub-abstract model.
Preferable, excitation generation module 220 was further used for before each cycle of emulation, generated the excitation of one-period according to the current configuration of Markov model, and offered emulator and carry out emulation.
Preferable, parameter adjustment module 230 is further used for searching the abstract distance of simulation result correspondence from described abstract range information table, compare the simulation result in a same emulation cycle of this cycle simulation result according to described abstract distance, if comparative result is that this cycle simulation result is more near dbjective state, then increase the weight on the pairing limit of excitation of current simulation result in the Markov model, and the weight that reduces other limits in the described Markov model is so that weight and be 1 in the limit that in the Markov model set out in summit, and starts described checking reporting module 240 as a result; Otherwise, directly start described checking reporting module 240 as a result.
fit
i＝Max
i-D
i
Fit
iBe the fitness value of simulation result in each sub-abstract model; D
iThe abstract distance of the correspondence that in the abstract range information table of described sub-abstract model, finds for simulation result, Max
iMaximum abstract distance value for described sub-abstract model; Be calculated as follows the fitness of simulation result,
V
iBe the dbjective state variable number that comprises in the sub-abstract model; V
TotalTotal dbjective state variable number of expression abstract model; N
PThe quantity of representing sub-abstract model, Fitness_value represents the fitness value of this cycle simulation result;
The fitness of the simulation result correspondence in a same emulation cycle of fitness of comparison this cycle simulation result correspondence, if comparative result is that this cycle simulation result is more near dbjective state, then increase the weight on the pairing limit of excitation of current simulation result in the Markov model, and the weight that reduces other limits in the described Markov model is so that weight and be 1 in the limit that in the Markov model set out in summit, and starts described checking reporting module 240 as a result; Otherwise, directly start described checking reporting module 500 as a result.
Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but determine by the scope of claims.
Claims (20)
1. an integrated circuit verification method is characterized in that, comprising:
Step 1, abstract engine carries out abstract to integrated circuit to be verified, generate corresponding abstract model, and carries out formalization and calculate on described abstract model, to obtain formalization information;
Step 2, excitation generate the Markov model that the engine initialization is set up according to the standard of integrated circuit to be verified;
Step 3, excitation generates engine and generates excitation by Markov model, and with described excitation input emulator, described emulator carries out emulation to described integrated circuit to be verified;
Step 4, described excitation generate engine and compare the simulation result of this cycle simulation result and last cycle emulation acquisition according to described formalization information, if this cycle simulation result more near dbjective state, is then adjusted parameter in the described Markov model;
Step 5 if integrated circuit miss the mark state to be verified and simulation times do not surpass preset times, is then carried out described step 3; Otherwise, stop emulation, and report success or move overtime.
2. integrated circuit verification method according to claim 1 is characterized in that,
Described step 1 further is,
Step 21 is set up the data dependency graph;
Step 22 is carried out abstractly on described data dependency graph, generates abstract model;
Step 23 is carried out formalization and is calculated on described abstract model, obtain formalization information.
3. integrated circuit verification method according to claim 2 is characterized in that,
Described step 21 further is,
Step 31 according to the description of the hardware description language of integrated circuit to be verified, is set up the data dependency graph according to the dbjective state variable of storage dbjective state; In the described data dependency graph, each node is represented a register variable, and the oriented arrow between two nodes represents that there is data dependence relation in destination node to the source node.
4. integrated circuit verification method according to claim 3 is characterized in that,
Described step 22 further is,
Step 41 in described data dependency graph, from the dbjective state variable, according to logic dependence recalling from the close-by examples to those far off, and adopts the BFS (Breadth First Search) mode that the register variable that traverses is joined abstract model; If two exist the register variable of dependence to be added in the described abstract model, then the combinational logic between two described register variables also is added in the described abstract model.
5. integrated circuit verification method according to claim 3 is characterized in that,
Described step 22 further is,
Step 51, in described data dependency graph, described dbjective state variable is divided into group, dbjective state variable from each group, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode register variable that traverses to be joined in the corresponding sub-abstract model of abstract model; If two exist the register variable of dependence to be added in the described sub-abstract model, then the combinational logic between two described register variables also is added in the described sub-abstract model.
6. integrated circuit verification method according to claim 2 is characterized in that,
Described step 23 further is,
Step 61, employing is carried out formalization calculating based on the formalization computational tool of two fens decision diagrams on described abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table, described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
7. integrated circuit verification method according to claim 5 is characterized in that,
Described step 23 further is,
Step 71, employing is carried out formalization calculating based on the formalization computational tool of two fens decision diagrams on each described sub-abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table of described sub-abstract model correspondence, described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
8. integrated circuit verification method according to claim 1 is characterized in that,
Described step 3 further is,
Step 81, described excitation generated engine before each cycle of emulation, generated the excitation of one-period according to the current configuration of Markov model, and offered emulator and carry out emulation.
9. according to claim 6 or 7 described integrated circuit verification methods, it is characterized in that,
Described step 4 further is,
Step 91, from described abstract range information table, search the abstract distance of simulation result correspondence, compare this cycle simulation result simulation result of the same one-period according to described abstract distance, if comparative result is that this cycle simulation result is more near dbjective state, then execution in step 92, otherwise, carry out described step 5;
Step 92 increases the weight on the pairing limit of excitation of current simulation result in the Markov model, and reduces the weight on other limits in the described Markov model so that weight and be 1 in the limit that in the Markov model set out in summit is carried out described step 5.
10. integrated circuit verification method according to claim 7 is characterized in that,
Described step 4 further is,
Step 101 is searched the abstract distance of simulation result correspondence from described abstract range information table, calculate the fitness of simulation result in sub-abstract model according to following formula,
fit
i＝Max
i-D
i
Fit
iBe the fitness value of simulation result in each sub-abstract model; D
iThe abstract distance of the correspondence that in the abstract range information table of described sub-abstract model, finds for simulation result, Max
iMaximum abstract distance value for described sub-abstract model;
Step S102 is calculated as follows the fitness of simulation result,
V
iBe the dbjective state variable number that comprises in the sub-abstract model; V
TotalTotal dbjective state variable number of expression abstract model; N
PThe quantity of representing sub-abstract model, Fitness_value represents the fitness value of this cycle simulation result;
Step S103, the fitness of the simulation result correspondence in a same emulation cycle of fitness of this cycle simulation result correspondence relatively, if comparative result be this cycle simulation result more near dbjective state, then execution in step 104, otherwise, carry out described step 5;
Step 104 increases the weight on the pairing limit of excitation of current simulation result in the Markov model, and reduces the weight on other limits in the described Markov model so that weight and be 1 in the limit that in the Markov model set out in summit is carried out described step 5.
11. an integrated circuit verification system is characterized in that, comprising:
Abstract engine is used for integrated circuit to be verified is carried out abstract, generates corresponding abstract model, and carries out formalization and calculate on described abstract model, to obtain formalization information;
Excitation generates engine and comprises that Markov model sets up module, excitation generation module, parameter adjustment module, checking reporting module as a result,
Described Markov model is set up module, is used for the Markov model that initialization is set up according to the standard of integrated circuit to be verified;
Described excitation generation module is used for generating excitation by Markov model, with described excitation input emulator;
Described emulator is used for described integrated circuit to be verified is carried out emulation;
Described parameter adjustment module is used for the simulation result that the described formalization information of foundation compares this cycle simulation result and last cycle emulation acquisition, if this cycle simulation result more near dbjective state, is then adjusted parameter in the described Markov model;
Described checking is reporting module as a result, is used for starting when integrated circuit miss the mark state to be verified and simulation times surpass preset times described excitation generation module; Otherwise, stop emulation, and report success or move overtime.
12. integrated circuit verification according to claim 11 system is characterized in that,
Described abstract engine is further used for setting up the data dependency graph; On described data dependency graph, carry out abstractly, generate abstract model; On described abstract model, carry out formalization and calculate, obtain formalization information.
13. integrated circuit verification according to claim 12 system is characterized in that,
Described abstract engine is further used for the description according to the hardware description language of integrated circuit to be verified when setting up the data dependency graph, set up the data dependency graph according to the dbjective state variable of storage dbjective state; In the described data dependency graph, each node is represented a register variable, and the oriented arrow between two nodes represents that there is data dependence relation in destination node to the source node.
14. integrated circuit verification according to claim 13 system is characterized in that,
Described abstract engine is further used in described data dependency graph when generating abstract model, from the dbjective state variable, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode that the register variable that traverses is joined abstract model; If two exist the register variable of dependence to be added in the described abstract model, then the combinational logic between two described register variables also is added in the described abstract model.
15. integrated circuit verification according to claim 13 system is characterized in that,
Described abstract engine is further used in described data dependency graph when generating abstract model, described dbjective state variable is divided into group, dbjective state variable from each group, according to logic dependence recalling from the close-by examples to those far off, and adopt the BFS (Breadth First Search) mode register variable that traverses to be joined in the corresponding sub-abstract model of abstract model; If two exist the register variable of dependence to be added in the described sub-abstract model, then the combinational logic between two described register variables also is added in the described sub-abstract model.
16. integrated circuit verification according to claim 12 system is characterized in that,
Described abstract engine is carrying out being further used for adopting the formalization computational tool based on two fens decision diagrams to carry out formalization calculating when formalization is calculated on described abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table, and described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
17. integrated circuit verification according to claim 15 system is characterized in that,
Described abstract engine is carrying out being further used for adopting the formalization computational tool based on two fens decision diagrams to carry out formalization calculating when formalization is calculated on each described sub-abstract model, obtain formalization information, described formalization information is recorded in the abstract range information table of described sub-abstract model correspondence, described formalization information comprises the abstract distance of abstract state and abstract state correspondence.
18. integrated circuit verification according to claim 11 system is characterized in that,
Described excitation generation module was further used for before each cycle of emulation, generated the excitation of one-period according to the current configuration of Markov model, and offered emulator and carry out emulation.
19. according to claim 16 or 17 described integrated circuit verification systems, it is characterized in that,
Described parameter adjustment module is further used for searching the abstract distance of simulation result correspondence from described abstract range information table, compare this cycle simulation result simulation result of the same one-period according to described abstract distance, if comparative result is that this cycle simulation result is more near dbjective state, then increase the weight on the pairing limit of excitation of current simulation result in the Markov model, and the weight that reduces other limits in the described Markov model is so that weight and be 1 in the limit that in the Markov model set out in summit, and starts described checking reporting module as a result; Otherwise, directly start described checking reporting module as a result.
20. integrated circuit verification according to claim 17 system is characterized in that,
Described parameter adjustment module is further used for searching the abstract distance of simulation result correspondence from described abstract range information table, calculate the fitness of simulation result in sub-abstract model according to following formula,
fit
i＝Max
i-D
i
Fit
iBe the fitness value of simulation result in each sub-abstract model; D
iThe abstract distance of the correspondence that in the abstract range information table of described sub-abstract model, finds for simulation result, Max
iMaximum abstract distance value for described sub-abstract model; Be calculated as follows the fitness of simulation result,
V
iBe the dbjective state variable number that comprises in the sub-abstract model; V
TotalTotal dbjective state variable number of expression abstract model; N
PThe quantity of representing sub-abstract model, Fitness_value represents the fitness value of this cycle simulation result;
The fitness of the simulation result correspondence in a same emulation cycle of fitness of comparison this cycle simulation result correspondence, if comparative result is that this cycle simulation result is more near dbjective state, then increase the weight on the pairing limit of excitation of current simulation result in the Markov model, and the weight that reduces other limits in the described Markov model is so that weight and be 1 in the limit that in the Markov model set out in summit, and starts described checking reporting module as a result; Otherwise, directly start described checking reporting module as a result.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1928816A (en) * | 2006-09-26 | 2007-03-14 | 武汉大学 | Model drive for embedded system software and component development method |
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| CN1797411A (en) * | 2004-12-28 | 2006-07-05 | 北京六合万通微电子技术有限公司 | Method and equipment for implementing verification of digital-analog mixed type IC |
| CN1928816A (en) * | 2006-09-26 | 2007-03-14 | 武汉大学 | Model drive for embedded system software and component development method |
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Application publication date: 20100804 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: Verification methods and systems for integrated circuits Granted publication date: 20111109 License type: Exclusive License Record date: 20221009 |