CN101789918B - Parallel channel equalization method - Google Patents

Abstract

The invention discloses a parallel channel equalization method which comprises the following steps of: (S1) carrying out parallel frame synchronization processing on input data; (S2) carrying out parallel channel estimation by utilizing a known PN (pseudo-random noise) training sequence and a PN training sequence in data output by the step (S1) to obtain a channel parameter; (S3) respectively storing frame body data in the data output by the step (S1) and the channel parameter obtained by the estimation into a first-in first-out memory, making up 0 for the channel parameter, and then beginning to output the frame body data and the channel parameter at the same time; and (S4) sequentially carrying out a parallel FFT (Fast Fourier Transform Algorithm) operation, a parallel division operation and a parallel IFFT (Inverse Fast Fourier Transform) operation on the frame body data and the channel parameter to obtain output data. The invention can reduce the requirements on the processing speed of the data and the clock rates of devices, is suitable for wireless high-speed data communication systems, can realize the unbiased estimation of the channel parameter and improve the accuracy of an estimated parameter on hardware and is particularly suitable for occasions requiring to utilize only a section of the training sequence to carry out the channel estimation.

Description

Parallel channel equalization method

Technical field

The present invention relates to digital information transmission technical field, relate in particular to a kind of parallel channel equalization method.

Background technology

In radio communication channel, exist stronger multipath to disturb usually, need to adopt the channel equalization algorithm to offset the influence of time-variant multipath channel.Usually the equalization methods that adopts has time domain equalization and frequency domain equalization two big classes.For the time domain equalization algorithm, need to adopt transversal filter to accomplish; For the frequency domain equalization algorithm, need data be carried out handling behind the DFT.Carry out frequency domain equalization and at first need estimate channel parameter, channel estimating mainly contains auxiliary algorithm for estimating of data and blind algorithm for estimating two big classes, and wherein the data aided algorithm is simple because of method, and estimated accuracy is high, has obtained using widely.

Traditional channel equalization algorithm proposes to the single channel serial data, and when transmission rate was very high, device need move under very high clock rate, considers factors such as cost and power consumption, and this high speed device of a large amount of uses is irrational in communication system.

Summary of the invention

The technical problem that (one) will solve

The objective of the invention is deficiency to prior art; A kind of requirement that can reduce processing speed of data and device clock rate has been proposed; Be applicable to the wireless high-speed data communication system; The nothing that on hardware, can realize channel parameter is estimated partially, improves the accuracy of estimated parameter, is particularly suitable for requiring only to utilize one section training sequence to carry out the parallel channel equalization scheme of the occasion of channel estimating.

(2) technical scheme

For achieving the above object, the invention provides a kind of parallel channel equalization method, may further comprise the steps:

S1 carries out the concurrent frame Synchronous Processing to the input data;

S2 utilizes PN training sequence (the PN training sequence that promptly receives) in the data of known PN training sequence and step S1 output to carry out parallel channel and estimates, obtains channel parameter;

S3 stores frame data in the data of step S1 output and the channel parameter of estimating in the pushup storage into respectively, and said channel parameter is mended 0, at synchronization said frame data and channel parameter is begun output then;

S4, to the FFT computing that walks abreast successively of said frame data and channel parameter, parallel division arithmetic and parallel I FFT computing obtain dateout.

Wherein, said step S1 may further comprise the steps:

S11 will participate in parallel N _pAll input storage of road related operation are exported N in the input data register _pChannel parallel data, every road N _rIndividual data;

S12 is with said N _pEach road N of channel parallel data _rIndividual data symbol, respectively with known PN training sequence in the value of relevant position compare output N _pChannel parallel data, there is N on each road _rIndividual data, real part and imaginary part value respectively are positive 1 or negative 1;

S13 is with the N of step S12 output _pChannel parallel data is sued for peace respectively and the mould of value is then thought more than or equal to predetermined threshold value and searched PN training sequence original position, wherein, only in preset judgement window (size of window is preset), carries out synchronous searching;

S14 is with the N that receives _pThe PN training sequence in the channel parallel data (promptly above-mentioned " the PN training sequence that receives ") and the length of frame data all are adjusted into N _pIntegral multiple, mend 0 during curtailment, frame data and PN training sequence after output is handled then, wherein, the initial data of frame data and PN training sequence is exported in the first via;

S15; The angle of the data rotatable phase of confirming according to the symbol of the real part of the corresponding maximum related value of said PN training sequence original position and imaginary part to receive; Then whole frame data are carried out the phase place rotation, eliminate phase ambiguity, said whole frame data comprise PN training sequence and frame data.

Wherein, said step S2 may further comprise the steps:

S21, a PN training sequence register of the PN training sequence that storage is known returns to initial condition;

S22 is with the parallel N that receives _pRoad PN training sequence stores N into _pOrganize in the 2nd PN training sequence register, be used for subsequent calculations;

S23; According to the value of a said PN training sequence register with the corresponding position of the 2nd PN training sequence register; Utilize adder to carry out complex multiplication operation; With all back data additions of multiplying each other obtain multiplying each other of back vector, then with a PN training sequence register rotation, other of the back vector that obtains successively multiplying each other;

S24, each the component addition with the vector of step S23 output obtains a scalar;

S25 carries out each component that computing obtains channel parameter through shift unit and adder to each component and the said scalar of the vector of step S23 output, wherein, calculates N simultaneously _pIndividual component, and with this N _pIndividual component and line output.

Wherein, said step S4 may further comprise the steps:

S411 is respectively to the N of said frame data and channel parameter _pBar props up circuit-switched data and makes N _b/ N _pPoint FFT; S412 carries out the phase place rotation to the data after the step S411 processing; S413 makes N to the data after the step S412 processing _pPoint FFT is to obtain N simultaneously _pData behind road frame data and the channel parameter FFT;

S42 is to N _pN is carried out in data pointwise behind road frame data and the channel parameter FFT _pThe road division that walks abreast;

S431 is to the N after the S42 processing _pBar props up circuit-switched data and makes N _pPoint IFFT; S432 carries out the phase place rotation to the data after the step S431 processing; S433 makes N to the data after the step S432 processing _b/ N _pPoint IFFT is to obtain N simultaneously _pRoad balanced data output.

Wherein, the phase place that correspondence position rotated in step S412 and S432 is conjugation each other.

Wherein, before step S1, said input data clock recovery and carrier wave recovery have correctly been accomplished.

Wherein, said input data comprise frame head data and frame data, and said frame head data comprises frame head Cyclic Prefix and PN training sequence, and said frame data comprise frame Cyclic Prefix and valid data.

Wherein, in said parallel channel equalization method, adopt the QPSK modulation system to carry out radio communication, wherein, the frame head data of I, Q two paths of data is identical.

Wherein, said PN training sequence is the m sequence.

Wherein, the duration of said input data is enough short, to guarantee the utilizing estimated channel information of frame head data during whole input data, to remain valid.

Wherein, the length of said frame head Cyclic Prefix and frame Cyclic Prefix all should be more than or equal to channel length.

(3) beneficial effect

The parallel channel equalization method that technical scheme of the present invention proposes adopts the parallel processing mode, has reduced the requirement to processing speed of data and device clock rate, applicable to the wireless high-speed data communication system.Through suitable selection parameter; Parallel channel method of estimation wherein can only multiply each other through addition and displacement realization matrix and invert; Thereby the nothing that on hardware, can realize channel parameter is estimated partially; Improved the accuracy of estimated parameter, be particularly suitable for requiring only to utilize one section training sequence to carry out the occasion of channel estimating.

Description of drawings

Fig. 1 is the all-digital receiver theory diagram that the method for the embodiment of the invention is used;

Fig. 2 is the method flow diagram of the embodiment of the invention;

Fig. 3 is an employed frame assumption diagram in the method for the embodiment of the invention;

Fig. 4 is employed 9 grades of m sequencer structural representations in the method for the embodiment of the invention.

Embodiment

Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.

The present invention can be applicable in the high-speed radiocommunication all-digital receiver, and the all-digital receiver theory diagram that the method for the embodiment of the invention is used is as shown in Figure 1, and Fig. 2 is the method flow diagram of the embodiment of the invention, and Fig. 3 is an employed frame assumption diagram in this method.As shown in Figure 3, frame structure comprises frame head and frame.Wherein, frame head comprises frame head Cyclic Prefix (frame head CP) and PN training sequence, and frame comprises frame Cyclic Prefix (frame CP) and valid data.The length of frame head CP is N _Hg, the length of PN training sequence is N _PN, the length of frame CP is N _Bg, frame length is N _bThe PN training sequence is chosen as the m sequence.Adopt the QPSK modulation system, the frame head of I, Q two-way is identical, and 1 is mapped as positive number, and 0 is mapped as negative.

It is considered herein that conducting frame synchronously, before the channel estimation and equalization, all-digital receiver has correctly been accomplished the recovery of clock recovery and carrier wave.The input of frame synchronization, channel estimating and channel equalization step and output are I, each N of Q _pChannel parallel data.Be computing convenience, N _bBe N _pIntegral multiple.

In the following formula, T representes transposition, and H representes conjugate transpose.Provide some definition below.

Definition PN training sequence

$x={(x_0,x_1,\·\·\·,x_{N_{\mathrm{PN}}-1})}^T---\left(1\right)$

Because of the frame head of I, Q two-way is identical, so satisfy x _i=1+j or x _i=-1-j, i=0,1 ..., N _PN-1.Add that length is N _HgCyclic Prefix after, the representation of frame head does

${(x_{N_{\mathrm{PN}}-N_{\mathrm{hg}}},\·\·\·,x_{N_{\mathrm{PN}}-1},x_0,x_1,\·\·\·,x_{N_{\mathrm{PN}}-1})}^T---\left(2\right)$

At receiving terminal, the PN training sequence that definition receives does

$y={(y_0,y_1,\·\·\·,y_{N_{\mathrm{PN}}-1})}^T---\left(3\right)$

Satisfy relational expression

y＝Ah+w (4)

Wherein, h=(h ₀, h ₁..., h _L-1) ^T(5)

Be channel parameter, length is L, and satisfies N _Hg>=L, N _Bg>=L.The expression formula of matrix A is:

$A={\left[\begin{array}{cccc}{x}_0& x_{N_{\mathrm{PN}}-1}& \·\·\·& x_{N_{\mathrm{PN}}-L+1}\\ x_1& x_0& \·\·\·& x_{N_{\mathrm{PN}}-L+2}\\ \·& \·& & \·\\ \·& \·& \·\·\·& \·\\ \·& \·& & \·\\ x_{N_{\mathrm{PN}}-1}& x_{N_{\mathrm{PN}}-2}& \·\·\·& x_{N_{\mathrm{PN}}-L}\end{array}\right]}_{N_{\mathrm{PN}}\×L}---\left(6\right)$

Its first row promptly are vector x, and other each row are cyclic shifts of first row.W is an additive white Gaussian noise.By maximum likelihood estimate, can solve:

h＝(A ^HA) ^-1A ^Hy (7)

The frame data that definition receives are:

$s={(s_0,s_1,\·\·\·,s_{N_b-1})}^T---\left(8\right)$

Definition

$h^{\′}=\left[\begin{array}{c}h\\ 0\end{array}\right]---\left(9\right)$

Here 0 for length be N _b-L, and all values is 0 column vector entirely.

Calculate the FFT of s and h ' respectively:

S＝FFT(s) (10)

H′＝FFT(h′)(11)

Division is calculated in pointwise:

D＝S/H′ (12)

Then

d＝IFFT(D) (13)

Be the result after the parallel frequency domain channel equalization.

Realize that for ease of hardware above-mentioned channel estimating only realizes with adder and shift unit.According to the relevant nature of m sequence, when phase deviation was 0, its correlation was N _PN, otherwise its correlation is-1, therefore, can obtain

$A^{H}A={\left[\begin{array}{cccc}2N_{\mathrm{PN}}& -2& \·\·\·& -2\\ -2& 2N_{\mathrm{PN}}& \·\·\·& -2\\ \·& \·& \·& \·\\ \·& \·& \·& \·\\ \·& \·& \·& \·\\ -2& -2& \·\·\·& 2N_{\mathrm{PN}}\end{array}\right]}_{L\×L}---\left(14\right)$

To A ^HA inverts, and obtains

${\left(A^{H}A\right)}^{-1}=\frac{1}{2(N_{\mathrm{PN}}+1)(N_{\mathrm{PN}}-L+1)}\left(\right[1]+(N_{\mathrm{PN}}-L+1)I)---\left(15\right)$

Wherein [1] expression all elements is 1 matrix entirely, I representation unit battle array.Definition

z＝(z ₀，z ₁，…，z _L-1) ^T＝A ^Hy (16)

$a=\underset{i=0}{\overset{L-1}{\mathrm{\Σ}}}{z}_i---\left(17\right)$

q＝(q ₀，q ₂，…，q _L-1) ^T＝[a，a，…，a] ^T+(N _PN-L+1)z (18)

Wherein, q _i=a+ (N _PN-L+1) z _i, i=0,1 ..., L-1 (19)

Then channel parameter is:

$h=\frac{1}{2(N_{\mathrm{PN}}+1)(N_{\mathrm{PN}}-L+1)}q---\left(20\right)$

Because A ^HForm by-1+j and 1-j, can be through addition in the hope of z and a.Character by the m sequence can be known: N _PN=2 ⁿ-1, as the L=2 that selects to participate in computing ^mThe time, q can realize that m and n are positive integer here through addition and displacement.Back 2 (the N of each component of channel parameter h of final output _PN+ 1) (N _PN-L+1) bit representation fractional part can be accepted or rejected as required.Also can select the individual component of preceding L ' in L the channel parameter component to be used for channel equalization calculating.

Because the input data are N _pThe road parallel input mode, definition y _i, i=1,2 ..., N _pBe each branch road input vector, then

$\left\{\begin{array}{c}{y}_1={(y_0,y_{N_p},\·\·\·,y_{(N_m-1)N_p})}^T\\ \·\\ \·\\ \·\\ y_{N_p}={(y_{N_p-1},y_{2N_p-1},\·\·\·,0)}^T\end{array}\right.---\left(21\right)$

The length of each vector does

Here

Expression rounds up, y _iIn curtailment vector last mend 0, with y ₁Length is identical.

Definition

The dimension matrix A _i, i=1,2 ..., N _p, matrix A _iThe data of the 1st row be respectively the capable data of i of matrix A, A ₁By the 1st of A, N _p+ 1,2N _p+ 1 ..., row is formed, all the other each matrixes and the like, matrix last column of curtailment mends 0, obtains:

$z=A^{H}y=A_1^H{y}_1+A_2^H{y}_2+\·\·\·+A_{N_p}^H{y}_{N_p}---\left(22\right)$

Try to achieve a, q and h by (17)～(20) formula then.Calculate the N of h simultaneously _pIndividual component, promptly h is N _pRoad and line output.

For N _pChannel parallel data is made N to every branch road respectively _b/ N _pPoint FFT.If A _i(k), i=1,2 ..., N _p, k=0,1 ..., N _b/ N _p-1 representes the FFT that i bar branch road calculates respectively, then need carry out the phase place rotation to these data:

$C_i\left(k\right)=W_{N_b}^{(i-1)k}{A}_i\left(k\right),i=\mathrm{1,2},\·\·\·,N_p,k=\mathrm{0,1},\·\·\·,N_b/N_p-1---\left(23\right)$

With i is that variable is respectively to C _i(k) make N _pPoint FFT obtains N simultaneously _pData behind the FFT of road, every circuit-switched data length is N _b/ N _p

N _pRoad parallel I FFT is tried to achieve by the anti-process of FFT.

Specify method of the present invention below.The present invention proposes parallel channel equalization method and comprises step:

S1. concurrent frame is synchronous, confirms frame head and frame position, corrects phase ambiguity and adjustment dateout;

S2. parallel channel is estimated, the corresponding data estimation channel parameter that utilizes known PN training sequence and receive;

S3. metadata cache stores frame data and channel estimating parameter among the FIFO into, begins output at synchronization, and the channel estimating parameter is mended 0.

S4. parallel frequency domain channel equalization is accomplished FFT, division and IFFT.

Step S1 further comprises step:

S11. input string and conversion

Be to confirm PN training sequence and frame position, needs will import data and known PN training sequence carries out related operation.Be the economize on hardware resource, the part correlation character of PN training sequence capable of using is got the preceding N of PN training sequence _rComputing, N are here participated in the position _r≤N _PNBecause the original position of PN training sequence is unascertainable, do not know at N _pIn the middle of which bar of bar branch road, therefore need carry out N _pThe road related operation that walks abreast.Need N altogether _p+ N _r-1 input data, this function is accomplished by one group of register.Realize that for ease of hardware mask register length is kN _p, k is a positive integer here, and satisfies kN _p>=N _p+ N _r-1.

At first, after receiving the input data, registers group is carried out Data Update

$\left\{\begin{array}{c}{d}_{\mathrm{spi}}\left(i\right)=d_{\mathrm{spi}}(i-N_p),i=N_p+1,\·\·\·,{\mathrm{kN}}_p\\ d_{\mathrm{spi}}\left(i\right)=d_{\mathrm{in}}\left(i\right),i=\mathrm{1,2},\·\·\·,N_p\end{array}\right.---\left(24\right)$

Here d _In(i), i=1,2 ..., N _pBe the input data.Input string and conversion are output as N _pChannel parallel data, every road N _rIndividual data

d _spo(i，m)＝d _spi(kN _p-i-m+2)，i＝1，2，…，N _p，m＝1，2，…，N _r (25)

Here, d _Spo(i, m) expression i road m data.

S12. level conversion

With d _Spo(i, m) sign bit of real part and imaginary part compares with the value of PN training sequence correspondence position respectively, the data d after the output level conversion _To(i, m), i=1,2 ..., N _p, m=1,2 ..., N _r

If Re [d _Spo(i, m)] for just and corresponding PN be 0, Re [d then _To(i, m)] be-1; If Re [d _Spo(i, m)] for negative and corresponding PN are 0, Re [d then _To(i, m)] be 1; If Im [d _Spo(i, m)] for just and corresponding PN be 0, Im [d then _To(i, m)] be-1; If Im [d _Spo(i, m)] for negative and corresponding PN are 0, Im [d then _To(i, m)] be 1.

S13. synchronous searching

To d _To(i, N m) _pCircuit-switched data addition summation respectively

$d_{\mathrm{cor}}\left(i\right)=\underset{m=1}{\overset{N_r}{\mathrm{\Σ}}}{d}_{\mathrm{to}}(i,m),i=\mathrm{1,2},...,N_p---\left(26\right)$

And with d _Cor(i) mould and preset thresholding T _CorRelatively.If d _Cor(i)>=T _Cor, then write down the position P of these data _SynFor improving the accuracy rate of frame synchronization, only in the judgement window, carry out synchronous searching.

S14. dateout adjustment

From P _SynThe position begins to export PN training sequence and the frame data that receive.If data length is N _pIntegral multiple, then need not adjust data.Otherwise, data length is increased to N _pIntegral multiple, curtailment is used 0 polishing, and removes frame prefix, an output frame volume data.The initial data of PN training sequence and frame data is in the output of article one branch road, and second data is in the output of second branch road, and follow-up data by that analogy.

S15. phase place rotation

The purpose of phase place rotation is to eliminate phase ambiguity.If Re [d _Cor(P _Syn)] and Im [d _Cor(P _Syn)] just be, then rotate θ=0 degree; If Re [d _Cor(P _Syn)] for negative, Im [d _Cor(P _Syn)] for just, then rotate θ=90 degree; If Re [d _Cor(P _Syn)] and Im [d _Cor(P _Syn)] be negative, then rotate θ=180 degree; If Re [d _Cor(P _Syn)] for just, Im [d _Cor(P _Syn)] for spending negative θ=270 that then rotate.Final dateout does

d _r(i)＝d _in(i)exp(jθ)，i＝1，2，…，N _p (27)

Step S2 further comprises step:

S21. initialization

After every frame data channel parameter estimation finished, a PN training sequence register of the PN training sequence that storage is known returned to initial condition.

S22. import storage

With the N that receives _pRoad PN training sequence stores N into _pOrganize in the 2nd PN training sequence register, finish until the PN training sequence.The length of every group of register is

S23. matrix and input vector multiply each other

Promptly ask vector z.When the S22 state finishes, m (m=1,2 ..., N _p) n the 2nd PN training sequence register r of group _Mn(n-1) N of a respectively corresponding PN training sequence register _p+ m value.If the value of a PN training sequence register is 0, then calculate (1+j) r _Mn, otherwise calculate (1-j) r _Mn, this step only can be accomplished through adder.The all values addition is promptly obtained first component of z.The 2nd PN training sequence register remains unchanged then, and a PN training sequence register cycle moves to right 1, obtains second component of z.So continue displacement, be shifted after L time, obtain vector z.

S24. ask vector with

All L component additions with z obtain scalar a.

S25. export estimated value

With each component of z N that moves to left _PN-L+1 position, with a addition, each component of the channel parameter of finally being exported.Back 2 (the N of each parameter component _PN+ 1) (N _PN-L+1) bit representation fractional part can be accepted or rejected as required.Calculate the N of h simultaneously _pIndividual component, promptly h is N _pRoad and line output.

Step S4 further comprises step:

S41. carry out the FFT computing:

S411. respectively to the N of frame and channel parameter _pThe data of bar branch road are N _b/ N _pPoint FFT obtains frame A _i(k) and channel parameter B _i(k), i=1,2 ..., N _p, k=0,1 ..., N _b/ N _p-1.

S412. carry out the phase place rotation

Be rotated by (23) formula, obtain C respectively _i(k) and D _i(k).

S413. be that variable is respectively to C with i _i(k) and D _i(k) make N _pPoint FFT obtains N simultaneously _p(k+ (i-1) N of data S behind road frame and the channel parameter FFT _b/ N _p) and H ' (k+ (i-1) N _b/ N _p), i=1,2 ..., N _p, k=0,1 ..., N _b/ N _p-1.

S42. carry out division arithmetic

N is carried out in pointwise _pThe road division that walks abreast:

D(k+(i-1)N _b/N _p)＝[S(k+(i-1)N _b/N _p)]/[H′(k+(i-1)N _b/N _p)] (28)

S43. carry out the IFFT computing:

S433. be that variable is to D (k+ (i-1) N with i _b/ N _p) make N _pPoint IFFT obtains N _pCircuit-switched data J _i(k), i=1,2 ..., N _p, k=0,1 ..., N _b/ N _p-1.

S432. carry out the phase place rotation

$L_i\left(k\right)=W_{N_b}^{-(i-1)k}{J}_i\left(k\right),i=\mathrm{1,2},\·\·\·,N_p,k=\mathrm{0,1},\·\·\·,N_b/N_p-1---\left(29\right)$

S433. respectively to N _pThe data of bar branch road are N _b/ N _pPoint IFFT gets d (i+kN _p), i=1,2 ..., N _p, k=0,1 ..., N _b/ N _p-1.

Illustrate the foregoing description through the form that parameter is specialized below.

In the wireless communication system of present embodiment, transmitting terminal is selected the QPSK modulation system, and the PN training sequence is selected 9 grades of m sequences, length N in the frame head _PN=511, generator polynomial x ⁹+ x ⁴+ 1, its structured flowchart is as shown in Figure 4, initial condition 010000000.The length of frame head CP is N _Hg=270, the length of frame CP is N _Bg=256, frame length is N _b=4096.Channel length L=256, and N is arranged _PN-L+1=256.N _p=2, N _r=64, back 18 is fractional part in the estimated channel parameter, and everybody is integer part for the front, after suitably accepting or rejecting, promptly can be used as channel estimation value output.

When carrying out channel equalization, two paths of data is carried out 2048 FFT respectively, basic 2-FFT computing is carried out in the phase place rotation again, and line output 2 circuit-switched data; Carry out 2 tunnel parallel divisions; Data behind 2 road divisions are carried out basic 2-IFFT computing, and phase place rotation is carried out 2048 IFFT respectively to two paths of data at last, obtains the result after the final equilibrium.

The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from know-why of the present invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.

Claims (8)

1. a parallel channel equalization method is characterized in that, may further comprise the steps:

S1 carries out the concurrent frame Synchronous Processing to the input data;

S2 utilizes PN training sequence in the data of known PN training sequence and step S1 output to carry out parallel channel and estimates, obtains channel parameter;

S3 stores frame data in the data of step S1 output and the channel parameter of estimating in the pushup storage into respectively, and said channel parameter is mended 0, at synchronization said frame data and channel parameter is begun output then;

S4, to the FFT computing that walks abreast successively of said frame data and channel parameter, parallel division arithmetic and parallel I FFT computing obtain dateout;

Said step S1 may further comprise the steps:

S11 will participate in parallel N _pAll input storage of road related operation are exported N in the input data register _pChannel parallel data, every road N _rIndividual data;

S12 is with said N _pEach road N of channel parallel data _rIndividual data symbol, respectively with known PN training sequence in the value of relevant position compare output N _pChannel parallel data, there is N on each road _rIndividual data, real part and imaginary part value respectively are positive 1 or negative 1;

S13 is with the N of step S12 output _pChannel parallel data is sued for peace respectively and the mould of value is then thought more than or equal to predetermined threshold value and searched PN training sequence original position, wherein, only in preset judgement window, carries out synchronous searching;

S14 is with the N that receives _pThe PN training sequence in the channel parallel data and the length of frame data all are adjusted into N _pIntegral multiple, mend 0 during curtailment, frame data and PN training sequence after output is handled then, wherein, the initial data of frame data and PN training sequence is exported in the first via;

S15; The angle of the data rotatable phase of confirming according to the symbol of the real part of the corresponding maximum related value of said PN training sequence original position and imaginary part to receive; Then whole frame data are carried out the phase place rotation, eliminate phase ambiguity, said whole frame data comprise PN training sequence and frame data;

Said step S2 may further comprise the steps:

S21, a PN training sequence register of the PN training sequence that storage is known returns to initial condition;

S22 is with the parallel N that receives _pRoad PN training sequence stores N into _pOrganize in the 2nd PN training sequence register, be used for subsequent calculations;

S23; According to the value of a said PN training sequence register with the corresponding position of the 2nd PN training sequence register; Utilize adder to carry out complex multiplication operation; With all back data additions of multiplying each other obtain multiplying each other of back vector, then with a PN training sequence register rotation, other of the back vector that obtains successively multiplying each other;

S24, each the component addition with the vector of step S23 output obtains a scalar;

S25 carries out each component that computing obtains channel parameter through shift unit and adder to each component and the said scalar of the vector of step S23 output, wherein, calculates N simultaneously _pIndividual component, and with this N _pIndividual component and line output;

Said step S4 may further comprise the steps:

S411 is respectively to the N of said frame data and channel parameter _pBar props up circuit-switched data and makes N _b/ N _pPoint FFT; S412 carries out the phase place rotation to the data after the step S411 processing; S413 makes N to the data after the step S412 processing _pPoint FFT is to obtain N simultaneously _pData behind road frame data and the channel parameter FFT; Wherein, N _bExpression frame length;

S42 is to N _pN is carried out in data pointwise behind road frame data and the channel parameter FFT _pThe road division that walks abreast;

S431 is to the N after the S42 processing _pBar props up circuit-switched data and makes N _pPoint IFFT; S432 carries out the phase place rotation to the data after the step S431 processing; S433 makes N to the data after the step S432 processing _b/ N _pPoint IFFT is to obtain N simultaneously _pRoad balanced data output.

2. parallel channel equalization method as claimed in claim 1 is characterized in that the phase place that correspondence position rotated in step S412 and S432 is conjugation each other.

3. parallel channel equalization method as claimed in claim 1 is characterized in that, before step S1, said input data has correctly been accomplished clock recovery and carrier wave recovery.

4. like each described parallel channel equalization method of claim 1～3; It is characterized in that; Said input data comprise frame head data and frame data, and said frame head data comprises frame head Cyclic Prefix and PN training sequence, and said frame data comprise frame Cyclic Prefix and valid data.

5. like each described parallel channel equalization method of claim 1～3, it is characterized in that in said parallel channel equalization method, adopt the QPSK modulation system to carry out radio communication, wherein, the frame head data of I, Q two paths of data is identical.

6. like each described parallel channel equalization method of claim 1～3, it is characterized in that said PN training sequence is the m sequence.

7. like each described parallel channel equalization method of claim 1～3, it is characterized in that the duration of said input data is enough short, to guarantee the utilizing estimated channel information of frame head data during whole input data, to remain valid.

8. parallel channel equalization method as claimed in claim 4 is characterized in that, the length of said frame head Cyclic Prefix and frame Cyclic Prefix all should be more than or equal to channel length.

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