CN101789701A - Soft switching power converter - Google Patents
Soft switching power converter Download PDFInfo
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- CN101789701A CN101789701A CN201010117084A CN201010117084A CN101789701A CN 101789701 A CN101789701 A CN 101789701A CN 201010117084 A CN201010117084 A CN 201010117084A CN 201010117084 A CN201010117084 A CN 201010117084A CN 101789701 A CN101789701 A CN 101789701A
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Abstract
A power converter according to the present invention comprises a resonant tank. The resonant tank is switched by a plurality of transistors. A control circuit generates a plurality of switching signals to control the transistors. The pulse widths of the switching signals are modulated for regulating an output voltage of the power converter. The control circuit is coupled to detect an input voltage of the power converter. The frequency of the switching signals is changed in response to the change of the input voltage or/and an output load of the power converter.
Description
Technical field
The invention relates to a kind of power converter, refer in particular to a kind of soft switching power converter.
Background technology
Phase-shift type power converter (Phase Shift Power Converter) is a kind of soft switching power converter, and it comprises full-bridge type phase shift (full-bridge phaseshift), asymmetrical half-bridge formula (asymmetrical half bridge) and active clamping formula (active clamp) framework or the like.The advantage of phase-shift type power converter be high efficiency and low electromagnetic interference (Electromagnetic Interference, EMI).In recent development, many phase shift technique have been proposed, for example: the United States Patent (USP) the 4th that Christopher, P.Henze, NedMohan and John G.Hayes were applied on August 8th, 1989,855, No. 888 " Constant frequency resonant power converter withzero voltage switching "; No. the 5th, 442,540, the United States Patent (USP) " Soft-switchingPWM converters " that Guichao C.Hua and Fred C.Lee were applied in August 15 nineteen ninety-five; No. the 6th, 356,462, the United States Patent (USP) " Soft-switchedfull-bridge converters " that Yungtaek Jang and Milan M.Jovanovic were applied on March 12nd, 2002; No. the 6th, 069,798, the United States Patent (USP) " Asymmetrical power converter and methodof operation thereof " that Rui Liu was applied on May 30th, 2000.In various phase-shift type power converter, transformer and/or the parasitic leakage inductance (parasitic leakage inductance) that adds magnet assembly are in order to as a resonance inductance, it is switched and produces circulating current, with reach zero voltage switching (Zero Voltage Switching, ZVS).
Yet the shortcoming of these phase-shift type power converters is that opereating specification is narrow.Therefore, purpose of the present invention is for proposing a kind of control mode, with the opereating specification of extended power transducer and increase operating efficiency.
Summary of the invention
Main purpose of the present invention is to provide a kind of power converter, is used to expand its opereating specification and increases operating efficiency.
To achieve the above object, the present invention is a kind of soft switching power converter, and it includes:
One resonant circuit;
The plural number transistor switches this resonant circuit; And
One control circuit, produce plural number and switch signal to control those transistors, and the pulse bandwidth of those switching signals of modulation, to adjust an output voltage of this power converter, this control circuit is detected an input voltage of this power converter, and changes the frequency that those switch signal according to the variation of this input voltage.
Among the present invention, wherein this resonant circuit more comprises an electric capacity and an induction installation, and this electric capacity couples this induction installation.
Among the present invention, wherein this control circuit more produces the complex delay time, and switch signal between to reach flexible switch those transistors at those those time of delays.
Among the present invention, more comprise one time of delay resistance, it couples this control circuit and switches those time of delays of signals to determine those.
Among the present invention, wherein those frequencies of switching signal reduce according to the reduction of this input voltage.
Among the present invention, wherein those frequencies of switching signal reduce according to the increase of an output loading of this power converter.
Among the present invention, more comprise a frequency setting resistance, it couples this control circuit, switches a maximum switching frequency of signal to determine those.
Among the present invention, more comprise a frequency modulating resistance, it couples this control circuit and switches a minimum switching frequency of signal to determine those.
Among the present invention, wherein this control circuit comprises:
One oscillator is detected this input voltage and and is feedback signal to produce an oscillation signal;
One pulse width modulation circuit produces a pulse wave width modulation signal according to this oscillation signal, and this pulse width modulation circuit is according to the pulse bandwidth of this this pulse wave width modulation signal of back coupling signal changing; And
One output circuit produces those according to this pulse wave width modulation signal and switches signal, the complex delay time be positioned at those switch signals between switch those transistors with flexibility.
Among the present invention, wherein this control circuit more comprises:
One feedback input circuit, couple an output of this power converter and receive this back coupling signal to produce the biased surely signal that moves, this oscillator receives the biased signal that moves of this standard and produces this oscillation signal to detect this back coupling signal, this pulse width modulation circuit receives the biased signal that moves of this standard, and according to the pulse bandwidth of this back coupling signal with this pulse wave width modulation signal of modulation.
Among the present invention, wherein this oscillator comprises:
One frequency modulating circuit produces a frequency modulating signal according to this back coupling signal and this input voltage;
One frequency generating circuit produces a charging current and a discharging current according to a frequency setting resistance and this frequency modulating signal, and this frequency setting resistance couples this control circuit and switches a maximum switching frequency of signal to determine those; And
One oscillating circuit receives this charging current and this discharging current to produce this oscillation signal.
The beneficial effect that the present invention has: those transistors of the present invention are in order to switch resonant circuit, control circuit produces plural number and switches signal to control those transistors, those pulse bandwidths that switch signal are subjected to modulation, to adjust an output voltage of power converter, one input voltage of control circuit detecting power converter, the frequency of switching signal changes according to the variation of an output loading of the input voltage of power converter or power converter.
Description of drawings
Fig. 1 is the circuit diagram of the power converter of a preferred embodiment of the present invention;
Fig. 2 is the circuit diagram of the control circuit of a preferred embodiment of the present invention;
Fig. 3 is the circuit diagram of the oscillator of a preferred embodiment of the present invention;
Fig. 4 is the circuit diagram of the frequency modulating circuit of a preferred embodiment of the present invention;
Fig. 5 is the circuit diagram of the frequency generating circuit of a preferred embodiment of the present invention;
Fig. 6 is the circuit diagram of the pulse width modulation circuit of a preferred embodiment of the present invention;
Fig. 7 is the circuit diagram of the blanking circuit of a preferred embodiment of the present invention;
Fig. 8 is the circuit diagram of the output circuit of a preferred embodiment of the present invention;
Fig. 9 be a preferred embodiment of the present invention time of delay circuit circuit diagram; And
Figure 10 is the translation function curve chart that shows the variation of the corresponding switching frequency of gain.
[figure number simple declaration]
10 transistors, 100 control circuits
110 transistors, 112 resistance
115 resistance, 116 resistance
20 transistors, 200 oscillators
210 rate modulation circuits, 220 current sources
211 first amplifiers, 221 second amplifiers
230 the 3rd amplifiers 235 the 4th amplifier
240 frequency generating circuits, 241 operational amplifiers
242 resistance, 243 transistors
244 transistors, 245 transistors
246 transistors, 247 transistors
250 current sources, 251 operational amplifiers
254 transistors, 255 transistors
256 transistors, 261 transistors
262 transistors, 263 transistors
264 transistors, 265 transistors
270 electric capacity, 271 switches
275 comparators, 276 comparators
281 NAND gate, 282 NAND gate
283 inverters, 285 inverters
30 transformers, 300 pulse width modulation circuits
310 T type flip-flops, 315 D type flip-flops
320 comparators, 331 inverters
332 transistors, 335 current sources
340 electric capacity, 35 stray inductances
400 blanking circuits, 410 inverters
420 transistors, 430 charging currents
450 electric capacity 460 and door
50 electric capacity, 500 output circuits
51 resistance, 510 current sources
52 resistance, 520 operational amplifiers
525 resistance, 53 resistance
550 transistors, 551 transistors
552 transistors, 553 transistors
61 resistance, 610 inverters
62 resistance 650 and door
660 with the door 670 buffers
680 buffers circuit 700 time of delay
701 time of delay circuit 71 rectifiers
715 inverters, 72 rectifiers
720 transistors, 73 inductance
75 electric capacity, 750 electric capacity
790 with the door I
CCharging current
80 Zener diodes, 81 resistance
85 optical coupler I
DDischarging current
I
MThe modulation electric current I
TCharging current
I
T1Electric current I
T2Electric current
IP input signal OP output signal
S
BBlanking signal S
HSwitch signal
S
LSwitch signal S
WThe frequency modulating signal
V
CCSupply electric V
FThe accurate biased signal that moves
V
FBBack coupling signal V
HUpper limit threshold value
V
INImport electric V
LThe lower limit threshold value
V
MFrequency modulating signal V
OOutput voltage
V
SWVoltage PLS oscillation signal
Embodiment
Further understand and understanding for making architectural feature of the present invention and the effect reached had, cooperate detailed explanation, be described as follows in order to preferred embodiment and accompanying drawing:
Seeing also Fig. 1, is the circuit diagram of the power converter of a preferred embodiment of the present invention.As shown in the figure, an electric capacity 50 and an induction installation (for example a transformer 30, its stray inductance 35 and load) form a resonant circuit (Resonant Tank).Electric capacity 50 is coupled between the end and earth terminal of first side winding of transformer 30.Therefore, electric capacity 50 is coupled to induction installation.Transistor 10,20 is coupled to resonant circuit, to switch resonant circuit.One drain of transistor 10 is coupled to an input voltage V
IN, the one source pole of transistor 10 is connected in a drain of transistor 20.The drain of the source electrode of transistor 10 and transistor 20 is coupled to the other end of the first side winding of transformer 30 via stray inductance 35.The one source pole of transistor 20 is coupled to earth terminal.Rectifier 71 and 72 is connected in the secondary side winding of transformer 30, and is connected to the output voltage V of power converter via an inductance 73
OOne electric capacity 75 is used to produce output voltage V
O
One control circuit 100 produces and switches signal S
HWith S
L, switch signal S
HWith S
LThe gate that couples transistor 10 and 20 respectively is with oxide-semiconductor control transistors 10 and 20.Switch signal S
HWith S
LPulse bandwidth be can be according to feedbacking signal V
FBAnd by modulation, to adjust the output voltage V of power converter
OBack coupling signal V
FBResult from VFB end.One feedback circuit comprises a Zener diode 80, a resistance 81 and an optical coupler 85, and it couples the output voltage V of power converter
OTo produce back coupling signal V
FBIn addition, a VA of control circuit 100 end is coupled to the input voltage V of power converter via resistance 61 and 62
IN, and detecting input voltage V
INResistance 61 connects input voltage V
IN, and resistance 61 is connected mutually with resistance 62.The VA end of control circuit 100 is connected in a tie point of resistance 61 and resistance 62.Switch signal S
HWith S
LFrequency can be according to input voltage V
INWith back coupling signal V
FBVariation and change.Therefore, can allow power converter to operate on the input voltage opereating specification of a broadness.
Switch signal S
HWith S
LFrequency can be along with input voltage V
INMinimizing and reduce.Switch signal S
HWith S
LFrequency also can be along with feedbacking signal V
FBIncrease and reduce.Back coupling signal V
FBVariation be the output loading that is associated in power converter.Therefore, control circuit 100 is the output loadings that are used to detect power converter, with the increase of the output loading of foundation power converter, switches signal S and reduce
HWith S
LFrequency.One resistance 53 is connected in the RT end of control circuit 100 to determine time of delay.Be positioned at time of delay and switch signal S
HWith S
LBetween, to reach flexible switching transistor 10 and 20.Therefore, control circuit 100 more produces and switches to reach flexible time of delay.Resistance 53 be used for as one time of delay resistance, switch signal S with decision
HWith S
LTime of delay.The RF end that one resistance 51 is connected in control circuit 100 switches signal S with decision
HWith S
LMaximum switching frequency.Resistance 51 is used for switching signal S as a frequency setting resistance with decision
HWith S
LMaximum switching frequency.Another resistance 52 is connected in the RM end of control circuit 100, and signal S is switched in its decision
HWith S
LMinimum switching frequency.Resistance 52 is used for adjusting resistance as a frequency and switches signal S with decision
HWith S
LMinimum switching frequency.
Seeing also Fig. 2, is the circuit diagram of the control circuit of a preferred embodiment of the present invention.As shown in the figure, it comprises a feedback input circuit, and it is coupled to output voltage V
OTo receive back coupling signal V
FB, to produce the biased surely signal V that moves
FThe accurate biased signal V that moves
FBe relevant to back coupling signal V
FBTransistor 110 forms feedback input circuit with resistance 112,115 and 116.One drain of transistor 110 receives a supply voltage V
CC, a gate of transistor 110 couples the VFB end to receive back coupling signal V
FBResistance 112 is connected between the drain and gate of transistor 110.Resistance 115 is connected in the one source pole of transistor 110.Resistance 116 is connected between resistance 115 and the earth terminal.
The accurate biased signal V that moves of one oscillator (OSC), 200 detectings
FDetect input voltage V with holding via VA
IN, to produce an oscillation signal PLS.Therefore, oscillator 200 detecting back coupling signal V
FBWith input voltage V
IN, to produce oscillation signal PLS.The resistance 51 that is positioned at the RF end couples oscillator 200 with the resistance 52 that is positioned at the RM end, with peak frequency and the minimum frequency of decision oscillation signal PLS.One pulse width modulation circuit (PWM) 300 couples oscillator 200 and produces pulse wave width modulation signal S with foundation oscillation signal PLS
WPulse width modulation circuit 300 is according to the accurate biased signal V that moves
FModulation pulse wave width modulation signal S
WPulse bandwidth.Therefore, pulse wave width modulation signal S
WPulse bandwidth along with feedbacking signal V
FBAnd by modulation.
One output circuit (OUT) 500 couples pulse width modulation circuit 300, and according to pulse wave frequency range signal S
WSwitch signal S to produce
HWith S
LIn addition, be positioned at switching signal S time of delay
HWith S
LBetween, to reach flexible switching transistor 10 and 20.The resistance 53 that is positioned at the RT end couples output circuit 500, with the decision value of time of delay.Comprise one first time of delay and one second time of delay time of delay.Result from for first time of delay and switch signal S
HSwitch signal S by afterwards
LBefore the conducting.Result from for second time of delay and switch signal S
LSwitch signal S by afterwards
HBefore the conducting.
Seeing also Fig. 3, is the circuit diagram of the oscillator of a preferred embodiment of the present invention.As shown in the figure, oscillator 200 comprises a frequency modulating circuit (M
IN-F) 210, one frequency generating circuit (FSW) 240 and an oscillating circuit.Frequency modulating circuit 210 couples the VA end and receives the accurate biased signal V that moves
F Frequency modulating circuit 210 is according to feedbacking signal V
FBWith input voltage V
INProduce a frequency modulating signal V
M Frequency generating circuit 240 is according to resistance 51 and frequency modulating signal V
MProduce a charging current I
CWith a discharging current I
DConsult Fig. 1 again, resistance 51 couples the RF end of control circuit 100.Frequency generating circuit 240 also produces a modulation electric current I
MWith charging RM end and flow through in resistance 52.Consult Fig. 1 again, resistance 52 is coupled to the RM end of control circuit 100.
Oscillating circuit comprises an electric capacity 270, switch 271 and 272, comparator 275 and 276, NAND gate 281 and 282 and inverter 283 and 285.One first termination of switch 271 is received charging current I
CWith charging capacitor 270.One second end of switch 271 couples one first end of switch 272 and one first end of electric capacity 270.The one second termination folding and unfolding electricity electric current I of switch 272
DWith discharge capacity 270.One second end of electric capacity 270 is coupled to earth terminal.One positive input terminal of comparator 275 receives upper limit threshold value V
HFirst end of one positive input terminal coupling capacitance 270 of one negative input end of comparator 275 and comparator 276, second end of switch 271 and first end of switch 272.One negative input end of comparator 276 receives a lower limit threshold value V
L, and upper limit threshold value V
HBe higher than lower limit threshold value V
L
One first end of NAND gate 281 couples an output of comparator 275.One first end of NAND gate 282 couples an output of comparator 276.One output of NAND gate 281 couples one second end of NAND gate 282.One output of NAND gate 282 couples one second end of NAND gate 281.One input of inverter 283 couples the output and the control switch 272 of NAND gate 281.One input of inverter 285 couples an output and the control switch 271 of inverter 283.One output of inverter 285 produces oscillation signal PLS.Therefore, oscillating circuit receives charging current I
CWith discharging current I
DTo produce oscillation signal PLS.
Seeing also Fig. 4, is the circuit diagram of the frequency modulating circuit of a preferred embodiment of the present invention.As shown in the figure, frequency modulating circuit 210 comprises one first amplifier 211, one second amplifier 221, one the 3rd amplifier 230 and one the 4th amplifier 235.One positive input terminal of first amplifier 211 receives the accurate biased signal V that moves
F, a negative input end of first amplifier 211 receives a threshold value V via a resistance 212
T1One output of first amplifier 211 couples the negative input end of first amplifier 211 via a resistance 213.One positive input terminal of second amplifier 221 couples the VA end, and a negative input end of second amplifier 221 couples its output, and forms a buffer circuit.One end of current source 220 couples supply voltage V
CC, the other end of current source 220 couples the output of second amplifier 221 via a resistance 224.One positive input terminal of the 3rd amplifier 230 couples the output of first amplifier 211 via a resistance 214.One end of one resistance 215 couples the positive input terminal of the 3rd amplifier 230, and the other end of resistance 215 is coupled to earth terminal.One negative input end of the 3rd amplifier 230 couples the other end of current source 220 and is coupled to its output via a resistance 225.
One positive input terminal of the 4th amplifier 235 couples the output of the 3rd amplifier 230.One negative input end of the 4th amplifier 235 couples its output, and the output of the 4th amplifier 235 couples the RM end and produces frequency modulating signal V
MThe modulation electric current I
MProvide to the output of the 4th amplifier 235 and the RM that charges end.Move signal V when standard is biased
FBe higher than threshold value V
T1The time, frequency modulating signal V
MCan be according to the accurate biased signal V that moves
FIncrease and increase.Frequency modulating circuit 210 is more via VA end detecting input voltage V
INWhen the voltage of VA end reduces and is lower than the threshold value that current source 220 provided, frequency modulating signal V
MWill be according to input voltage V
INMinimizing and increase.
Seeing also Fig. 5, is the circuit diagram of the frequency generating circuit of a preferred embodiment of the present invention.As shown in the figure, frequency generating circuit 240 comprises one first voltage current adapter, one second voltage current adapter, a current source 250, transistor 244 and 245 one first current mirrors that form, transistor 246 and 247 one second current mirrors that form, transistor 254 and 255 one the 3rd current mirrors that form, transistor 254 and 256 one the 4th current mirrors that form, transistor 261 and 262 one the 5th current mirrors that form, transistor 261 and 263 one the 6th current mirrors that form and transistor 264 and 265 one the 7th current mirrors that form.Frequency generating circuit 240 produces charging current I according to the resistance 51 (as shown in Figure 1) that couples the RF end
CWith discharging current I
DCharging current I
CWith discharging current I
DAccording to frequency modulating signal V
MIncrease and reduce.
First voltage current adapter comprises an operational amplifier 241, a transistor 243 and a resistance 242.One positive input terminal receive frequency modulation signal V of operational amplifier 241
M, an output of operational amplifier 241 couples a gate of transistor 243.One negative input end of operational amplifier 241 couples the one source pole of transistor 243.Resistance 242 is connected between the source electrode and earth terminal of transistor 243.One drain of transistor 243 couples first current mirror.The transistor 244 of first current mirror and 245 source electrode couple supply voltage V
CCTransistor 244 and 245 gate and the drain of transistor 244 and 243 interconnect.One drain of transistor 245 couples second current mirror.The transistor 246 of second current mirror and 247 source electrode are coupled to earth terminal.Transistor 246 and 247 gate and the drain of transistor 246 and 245 interconnect.One drain of transistor 247 is coupled to the 5th current mirror.
Second voltage current adapter comprises an operational amplifier 251, a transistor 253 and a resistance 252.One positive input terminal of operational amplifier 251 couples current source 250.Current source 250 more couples supply voltage V
CCThe positive input terminal of operational amplifier 251 more is connected in the resistance 51 (as shown in Figure 1) that is coupled in the RF end.One output of operational amplifier 251 couples a gate of transistor 253, and a negative input end of operational amplifier 251 couples the one source pole of transistor 253.Resistance 252 be connected in the source electrode of transistor 253 and earth terminal between.One drain of transistor 253 couples the 3rd current mirror.The transistor 254 of the 3rd current mirror and 255 source electrode couple supply voltage V
CCTransistor 254 and 255 gate and the drain of transistor 254 and 253 interconnect.One drain of transistor 255 couples the 5th current mirror.
The one source pole of the transistor 256 of the 4th current mirror couples supply voltage V
CCOne gate of transistor 256 couples the gate of transistor 254.One drain of transistor 256 produces the modulation electric current I
MThe transistor 261 of the 5th current mirror and 262 source electrode are coupled to earth terminal.Transistor 261 and 262 gate and the drain of transistor 261,247 and 255 interconnect.One drain of transistor 262 couples the 7th current mirror.The one source pole of the transistor 263 of the 6th current mirror is coupled to earth terminal.One gate of transistor 263 couples the gate of transistor 261.One drain of transistor 263 produces discharging current I
DThe transistor 264 of the 7th current mirror and 265 source electrode couple supply voltage V
CCTransistor 264 and 265 gate and the drain of transistor 264 and 262 interconnect.One drain of transistor 265 produces charging current I
C
Seeing also Fig. 6, is the circuit diagram of the pulse width modulation circuit of a preferred embodiment of the present invention.As shown in the figure, oscillation signal PLS couples a T type flip-flop 310 and a D type flip-flop 315, to trigger T type flip-flop 310 and D type flip-flop 315.One input D of D type flip-flop 315 receives supply voltage V
CCOne output Q of T type flip-flop 310 be connected with an output Q of D type flip-flop 315 one with door 350 two inputs, to produce pulse wave width modulation signal S
WT type flip-flop 310 provides one 50% maximal duty cycle (Duty Cycle) to give pulse wave width modulation signal S
WThe output Q of T type flip-flop 310 more connects an input of an inverter 331.Inverter 331, a transistor 332, a current source 335 and an electric capacity 340 constitute a slope generator, produce a slope signal with the activation of the output of foundation T type flip-flop 310.
One end of current source 335 couples supply voltage V
CC, one first end of the other end coupling capacitance 340 of current source 335.One second end of electric capacity 340 is coupled to earth terminal.First end of one drain coupling capacitance 340 of transistor 332.The one source pole of transistor 332 is coupled to earth terminal, and a gate of transistor 332 couples an output of inverter 331.When the output enable of T type flip-flop 310,340 chargings of 335 pairs of electric capacity of current source.When the output forbidden energy of T type flip-flop 310, electric capacity 340 discharges via transistor 332 and earth terminal.Therefore, electric capacity 340 promptly produces the slope signal.
The slope signal couples a positive input terminal of a comparator 320, and a negative input end of comparator 320 receives the accurate biased signal V that moves
F, and comparator 320 compares slope signal and the accurate biased signal V that moves
F, producing a pulse wave width modulation replacement signal, pulse wave width modulation replacement signal couples a replacement input R of D type flip-flop 315 via a NAND gate 325, with replacement D type flip-flop 315 with reach this pulse wave width modulation signal of modulation S
WPulse bandwidth.One blanking circuit (BLK) 400 couples pulse wave width modulation signal S
WAnd according to pulse wave width modulation signal S
WActivation and produce a blanking signal S
BBlanking signal S
B Connect NAND gate 325 to forbid the replacement of D type flip-flop 315, to guarantee pulse wave width modulation signal S
WA minimum ON time.
Seeing also Fig. 7, is the circuit diagram of the blanking circuit of a preferred embodiment of the present invention.As shown in the figure, blanking circuit 400 comprises a charging current 430, an inverter 410, a transistor 420, an electric capacity 450 and one and door 460.In the preferred embodiment of the present invention, transistor 420 can be a N transistor npn npn.One gate terminal of N transistor npn npn 420 receives pulse wave width modulation signal S via inverter 410
WReceive pulse wave width modulation signal S with a first input end of door 460
WThe one source pole of N transistor npn npn 420 is coupled to earth terminal.Couple a drain of N transistor npn npn 420 and an end of electric capacity 450 with one second input of door 460.The drain of N transistor npn npn 420 couples supply voltage V via charging current 430
CCThe other end of electric capacity 450 is coupled to earth terminal.Produce blanking signal S with an output of door 460
BTherefore, blanking circuit 400 receives pulse wave width modulation signal S
WAnd according to pulse wave width modulation signal S
WActivation produce blanking signal S
BThe electric current of the capacitance of electric capacity 450 and charging current 430 is decision blanking times.
Seeing also Fig. 8, is the circuit diagram of the output circuit of a preferred embodiment of the present invention.As shown in the figure, resistance 53 (as shown in Figure 1) is matched with a current source 510, holds in RT to produce a voltage.Current source 510 couples supply voltage V
CCAnd couple resistance 53 via RT end.The voltage of RT end connects a positive input terminal of an operational amplifier 520.Operational amplifier 520, a resistance 525 and a transistor 550 form a voltage current adapter, to produce an electric current and to couple transistor 551,552 and 553.The positive input terminal of operational amplifier 520 receives the voltage of RT end, and an output of operational amplifier 520 couples a gate of transistor 550.One negative input end of operational amplifier 520 couples the one source pole of transistor 550.Resistance 525 is connected between the source electrode and earth terminal of transistor 550.One drain of transistor 550 produces electric current and couples transistor 551,552 and 553.
Transistor 551,552 and 553 forms two current mirrors to produce electric current I
T1With I
T2, electric current I
T1With I
T2And couple circuit 700 and 701 time of delay respectively.Transistor 551,552 and 553 source electrode couple supply voltage V
CCTransistor 551,552 and 553 gate and the drain of transistor 551,550 interconnect.One drain of transistor 553 produces electric current I
T1And couple a circuit input of 700 time of delay.One drain of transistor 552 produces electric current I
T2And couple a circuit input of 701 time of delay.Time of delay circuit 700 and 701 produce and switch signal S
HWith S
LTime of delay.Pulse wave width modulation signal S
WConnection delay time circuit 700 and one and a door input of 650.Time of delay, a circuit output of 700 connected another input with door 650.Be connected a buffer 670 with an output of door 650 and switch signal S to produce
HSwitch signal S
HBe according to pulse wave width modulation signal S
WActivation, and result from after the time of delay that time of delay, circuit 700 was produced.
In addition, pulse wave width modulation signal S
WThe connection delay time circuit 701 and one and a door input of 660 via an inverter 610.Time of delay, circuit 701 output connected another input with door 660.Be connected a buffer 680 with an output of door 660 and switch signal S to produce
LSwitch signal S
LBe according to pulse wave width modulation signal S
WForbidden energy, and result from after the time of delay that time of delay, circuit 701 was produced.
Seeing also Fig. 9, is the circuit 700 and 701 circuit diagram time of delay of a preferred embodiment of the present invention.As shown in the figure, time of delay, circuit comprised a charging current I
T, an inverter 715, a transistor 720, an electric capacity 750 and one and door 790.Charging current I
TBe meant electric current I shown in Figure 8
T1With I
T2In the preferred embodiment of the present invention, transistor 720 can be the N transistor npn npn.One gate of N transistor npn npn 720 receives an input signal IP via inverter 715.For shown in Figure 8 time of delay circuit input of 700, input signal IP is pulse wave width modulation signal S
WFor shown in Figure 8 time of delay circuit input of 701, input signal IP also is pulse wave width modulation signal S
WBut, pulse wave width modulation signal S
WMust be anti-phase through inverter 610.Receive input signal IP with a first input end of door 790.The one source pole of N transistor npn npn 720 is coupled to earth terminal.Couple a drain of N transistor npn npn 720 and an end of electric capacity 750 with one second input of door 790.The drain of N transistor npn npn 720 couples charging current I
TThe other end of electric capacity 750 is coupled to earth terminal.Produce an output signal OP with an output of door 790.Therefore, time of delay, circuit received input signal IP, and produced output signal OP (time of delay) according to the activation of input signal IP.The capacitance of electric capacity 750 and charging current I
TElectric current decision time of delay.
Seeing also Figure 10, is the translation function curve chart, and it shows the variation of the corresponding switching frequency of gain.Voltage V in the icon
SWBe the voltage across transistor 20 (consulting Fig. 1), it is the input voltage of resonant circuit.N is a turn ratio (turn ratio) of transformer 30 (consulting Fig. 1).Frequency f
PFor switching signal S
HNumber and S
LMaximum switching frequency.Switch signal S
HMinimum pulse bandwidth must provide enough energy and circulating current to switch with the flexibility that reaches transistor 10 and 20.Frequency f
RResonance frequency for resonant circuit.Switch signal S
HWith S
LMinimum switching frequency should be higher than and near resonance frequency f
R, switch and the maximum power conversion to reach flexible.Figure 10 shows that switching frequency is from frequency f when input voltage minimizing and/or load increase
PBe reduced to frequency f
R, so get final product the extended operation scope and develop efficiency.
In sum, it only is a preferred embodiment of the present invention, be not to be used for limiting scope of the invention process, all equalizations of doing according to the described shape of claim scope of the present invention, structure, feature and spirit change and modify, and all should be included in the claim scope of the present invention.
Claims (11)
1. soft switching power converter is characterized in that it includes:
One resonant circuit;
The plural number transistor switches this resonant circuit; And
One control circuit, produce plural number and switch signal to control those transistors, and the pulse bandwidth of those switching signals of modulation, to adjust an output voltage of this power converter, this control circuit is detected an input voltage of this power converter, and changes the frequency that those switch signal according to the variation of this input voltage.
2. soft switching power converter according to claim 1 is characterized in that, wherein this resonant circuit more comprises an electric capacity and an induction installation, and this electric capacity couples this induction installation.
3. soft switching power converter according to claim 1 is characterized in that wherein this control circuit more produces the complex delay time, and switch signal between to reach flexible switch those transistors at those those time of delays.
4. soft switching power converter according to claim 3 is characterized in that, more comprise one time of delay resistance, it couples this control circuit and switches those time of delays of signals to determine those.
5. soft switching power converter according to claim 1 is characterized in that, wherein those frequencies of switching signal reduce according to the reduction of this input voltage.
6. soft switching power converter according to claim 1 is characterized in that, wherein those frequencies of switching signal reduce according to the increase of an output loading of this power converter.
7. soft switching power converter according to claim 1 is characterized in that, more comprises a frequency setting resistance, and it couples this control circuit, switches a maximum switching frequency of signal to determine those.
8. soft switching power converter according to claim 1 is characterized in that, more comprises a frequency modulating resistance, and it couples this control circuit and switches a minimum switching frequency of signal to determine those.
9. soft switching power converter according to claim 1 is characterized in that, wherein this control circuit comprises:
One oscillator is detected this input voltage and and is feedback signal to produce an oscillation signal;
One pulse width modulation circuit produces a pulse wave width modulation signal according to this oscillation signal, and this pulse width modulation circuit is according to the pulse bandwidth of this this pulse wave width modulation signal of back coupling signal changing; And
One output circuit produces those according to this pulse wave width modulation signal and switches signal, the complex delay time be positioned at those switch signals between switch those transistors with flexibility.
10. soft switching power converter according to claim 9 is characterized in that,
Wherein this control circuit more comprises:
One feedback input circuit, couple an output of this power converter and receive this back coupling signal to produce the biased surely signal that moves, this oscillator receives the biased signal that moves of this standard and produces this oscillation signal to detect this back coupling signal, this pulse width modulation circuit receives the biased signal that moves of this standard, and according to the pulse bandwidth of this back coupling signal with this pulse wave width modulation signal of modulation.
11. soft switching power converter according to claim 9 is characterized in that, wherein this oscillator comprises:
One frequency modulating circuit produces a frequency modulating signal according to this back coupling signal and this input voltage;
One frequency generating circuit produces a charging current and a discharging current according to a frequency setting resistance and this frequency modulating signal, and this frequency setting resistance couples this control circuit and switches a maximum switching frequency of signal to determine those; And
One oscillating circuit receives this charging current and this discharging current to produce this oscillation signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/645,585 | 2009-12-23 | ||
| US12/645,585 US20100202167A1 (en) | 2009-02-10 | 2009-12-23 | Soft switching power converter with a variable switching frequency for improving operation and efficiency |
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| Publication Number | Publication Date |
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| CN101789701A true CN101789701A (en) | 2010-07-28 |
| CN101789701B CN101789701B (en) | 2014-08-27 |
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| US9300206B2 (en) | 2013-11-15 | 2016-03-29 | Power Systems Technologies Ltd. | Method for estimating power of a power converter |
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| CN101789701B (en) | 2014-08-27 |
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