Partial PFC device and control method thereof
Technical Field
The invention relates to a partial PFC device and a control method thereof, in particular to a partial PFC device for a variable-frequency air conditioner controller and a control method thereof.
Background
At present, in the field of control of inverter air conditioners, PFCs are commonly used.
The passive PFC circuit has poor power factor correction effect which can only reach about 0.9 to the maximum extent, and has higher cost under the environment of price rise of the current basic raw materials, and the passive PFC circuit also has the defect that the direct current voltage after rectification is obviously reduced under the condition of high current, so that the rear stage is influenced, for example, the load such as a compressor and the like can not work at high operating frequency.
The full-active PFC power factor has a good correction effect which can reach more than 0.99, but the high-frequency interference is very serious due to high cost, particularly high-speed hard switch chopping, the serious electromagnetic interference (EMC) problem is generated, high stealth cost is indirectly increased for solving the EMC problem, and the total cost is higher.
For example, chinese patent document No. CN 101217254a discloses a semi-active power factor corrector and a correction method in 2008, 9/7, the semi-active power factor corrector is mainly composed of a first bridge circuit, a second bridge circuit, a power frequency inductor, an IGBT, and a back-stage capacitor, the 1 st end and the 3 rd end of the first bridge circuit are respectively connected to the N end and the L end of the alternating current, the power frequency inductor is disposed at the 3 rd end and the L end of the alternating current of the first bridge circuit, the C pole and the E pole of the IGBT are respectively connected to the 2 nd end and the 4 th end of the first bridge circuit, the G pole of the IGBT is connected to the control unit, the 1 st end and the 3 rd end of the second bridge circuit are respectively connected to the 3 rd end and the 1 st end of the first bridge circuit, and the back-stage capacitor is connected between the 2 nd end and the 4 th end of the second bridge circuit. The semi-active power factor correction method is characterized in that after the zero crossing of alternating voltage is detected, the IGBT is immediately controlled to turn on one or more pulses to charge and store energy for the power frequency inductor, and when the IGBT is closed, the power frequency inductor releases the stored energy to a capacitor at the rear stage. The semi-active power factor corrector and the correction method can reduce the electromagnetic interference (EMI) in the active PFC to a certain extent, but the effect is not ideal enough and needs to be improved.
Disclosure of Invention
The invention aims to provide a partial PFC device and a control method thereof, which have the advantages of simple and reasonable structure, flexible operation, partial PFC control, effective reduction of EMC problem, low cost, high power factor and capability of improving output direct-current voltage, and overcome the defects in the prior art.
The partial PFC device designed according to the purpose comprises a rectifier bridge stack BD1 and a mains supply, and is characterized by further comprising a current sampling circuit, a zero-crossing detection circuit, an inductor L1, a diversion diode D1, a diversion diode D2, a power electronic switch G1, a voltage sampling circuit, a PFC drive circuit and a main control MCU;
wherein,
the live wire L of the commercial power is connected with the anode of the flow guide diode D1, the alternating current input end AC1 of the rectifier bridge stack BD1 and one sampling point of the zero-crossing detection circuit; a zero line N of the commercial power is connected with one end of the current sampling circuit; the other end of the current sampling circuit is connected with one end of an inductor L1 and the other sampling point of the zero-crossing detection circuit; the other end of the inductor L1 is connected with the anode of the flow guide diode D2 and the other alternating current input end AC2 of the rectifier bridge stack BD 1; the current inflow end 2 of the power electronic switch G1 is connected with the cathodes of the flow guide diode D1 and the flow guide diode D2; the current outflow end 3 of the power electronic switch G1 is connected with the DC output negative end V-of the rectifier bridge stack BD1, and one sampling end of the voltage sampling circuit; the other sampling end of the voltage sampling circuit is connected with a direct current output positive end V + of the rectifier bridge stack BD 1; the control electrode 1 of the power electronic switch G1 is connected with the output stage of the PFC driving circuit; the master control MCU is respectively connected with the output of the zero-crossing detection circuit, the output of the voltage sampling circuit, the output of the current sampling circuit and the input of the PFC driving circuit;
or,
the live wire L of the commercial power is connected with the cathode of the flow guide diode D1, the alternating current input end AC1 of the rectifier bridge stack BD1 and one sampling point of the zero-crossing detection circuit; a zero line N of the commercial power is connected with one end of the current sampling circuit; the other end of the current sampling circuit is connected with one end of an inductor L1 and the other sampling point of the zero-crossing detection circuit; the other end of the inductor L1 is connected with the cathode of the flow guide diode D2 and the other alternating current input end AC2 of the rectifier bridge stack BD 1; the current output end 3 of the power electronic switch G1 is connected with the anodes of the flow guide diode D1 and the flow guide diode D2; the current inflow end 2 of the power electronic switch G1 is connected with the direct current output positive end V + of the rectifier bridge stack BD1 and one sampling end of the voltage sampling circuit; the other sampling end of the voltage sampling circuit is connected with the DC output negative end V-of the rectifier bridge stack BD 1; the control electrode 1 of the power electronic switch G1 is connected with the output stage of the PFC driving circuit; the master control MCU is respectively connected with the output of the zero-crossing detection circuit, the output of the voltage sampling circuit, the output of the current sampling circuit and the input of the PFC driving circuit;
or,
the live wire L of the commercial power is connected with one end of the inductor L1 and one sampling point of the zero-crossing detection circuit; the other end of the inductor L1 is connected with the cathode of the flow guide diode D1 and the alternating current input end AC1 of the rectifier bridge stack BD 1; a zero line N of the commercial power is connected with one end of the current sampling circuit; the other end of the current sampling circuit is connected with the other sampling point of the zero-crossing detection circuit, the cathode of the flow guide diode D2 and the other alternating current input end AC2 of the rectifier bridge stack BD 1; the current inflow end 2 of the power electronic switch G1 is connected with the direct current output positive end V + of the rectifier bridge stack BD1 and one sampling end of the voltage sampling circuit; the current outflow end 3 of the power electronic switch G1 is connected with the anodes of the flow guide diode D1 and the flow guide diode D2; the other sampling end of the voltage sampling circuit is connected with the DC output negative end V-of the rectifier bridge stack BD 1; the control electrode 1 of the power electronic switch G1 is connected with the output stage of the PFC driving circuit; the main control MCU is respectively connected with the output of the zero-crossing detection circuit, the output of the voltage sampling circuit, the output of the current sampling circuit and the input of the PFC driving circuit.
The master MCU comprises an AD conversion unit AD1, an AD conversion unit AD2, a high-level timer unit timer 3 and a widening pulse signal generation unit PWM 4.
In order to adapt to the rapid change of the power supply voltage and the rapid adjustment of the load, the time constants of the voltage and current sampling circuits of the circuit are designed to be smaller. The current sampling circuit adopts a peak detection mode, and the time constant during detection is within the range of 10-500 milliseconds; the voltage sampling circuit adopts a peak detection mode, and the time constant during detection is within the range of 10-500 milliseconds. This may provide some unexpected benefits: when the voltage of the mains supply fluctuates, part of the PFC devices can quickly respond and can be adjusted in time. Because the frequency conversion air conditioning system is rapidly changed, particularly the running frequency of the compressor is adjusted very violently sometimes according to the change of the air conditioning system, when the load is rapidly changed, the adjustment of part of the PFC device provided by the invention can be rapidly corresponding.
After the time constant is reduced, in order to accurately sample the peak value of the voltage and the peak value of the current, the current value and the voltage value need to be sampled at regular time at the moment when the peak value point of the current and the peak value point of the voltage appear, so that the peak values of the voltage and the current can be accurately sampled, and the specific control is as follows.
A control method of a partial PFC device is characterized in that when a timer 3 of a main control MCU receives rising or falling edge trigger of a zero-crossing signal of a zero-crossing detection circuit, the timer 3 starts timing from zero, and starts to open an AD conversion unit AD1 and an AD conversion unit AD2 to sample a current peak value Ip and a voltage amplitude value Vp of a voltage Vdc rectified by a rectifier bridge stack BD1 when the timing reaches beta milliseconds, wherein a sampling current value is Iad, and a voltage value is Vad; wherein the value range of beta is 4.5-6.
Because the zero-crossing signal detected by the actual zero-crossing detection circuit is a pulse square wave signal surrounding the real zero-crossing point, the rising edge or the falling edge of the pulse square wave signal has deviation from the real zero-crossing point, and the ambient temperature and the voltage of the mains supply can influence the deviation, 4.5-6 milliseconds after the zero-crossing point triggering timing is timed, and the sampling timing moment actually used is determined by combining with a specific hardware circuit after test verification, so that the peak value of the real current and voltage can be detected as the target.
The power factor correction method comprises the following steps: three high-level or low-level pulse signals are generated by the width-widening pulse signal generating unit PWM4 from the zero-crossing time to the next 4 milliseconds, the PFC driving circuit is driven to drive the power electronic switch G1 to be closed three times to charge and store energy for the inductor L1, and during the subsequent disconnection period of each pulse signal, the inductor L1 discharges to the next stage through the rectifier bridge stack BD1 to realize the power factor correction function.
Since the commercial power voltage is a sine wave signal, as can be seen from the characteristics of the sine function, in the phase angle range of 0 to 90 degrees, the smaller the phase angle, the smaller the contribution to the power factor, and also in the phase angle range of 90 to 180 degrees, the larger the phase angle, the smaller the contribution to the power factor; most critical is the phase relationship of voltage to current around 30 degrees phase and around 150 degrees phase. In order to improve the synchronism of the phase of the voltage current near the phase angle of 30 degrees, the control key of the control scheme is the control timing and pulse width of the first pulse, and simultaneously, in order to ensure the similarity of the current and voltage waveforms near the phase of 150 degrees, the inductance of the inductor L1 cannot be too small, and according to the experimental test result, when the maximum load current is changed between 8A and 20A, the inductor value of the inductor L1 is preferably 12 mH-25 mH.
The triple pulse widths (t2-t1), (t4-t3) and (t6-t5) are determined by the inductance of inductor L1 and Iad and Vad; for the same inductance of the inductor L1, the three-time pulse widths (t2-t1), (t4-t3) and (t6-t5) and the pulse intervals (t3-t2) and (t5-t4) corresponding to different Iad and Vad are different;
the turn-off point t2 of the first pulse, which is related to the current Iad, satisfies the following equation:
t2=T+Iad×n,
t is a fixed value; the range is 1500-3500, unit: microseconds, related to the inductance of inductor L1; iad units: a;
n is a coefficient, ranging within 100, in units: microsecond/a, associated with a maximum value of Iad values and its corresponding actual current value;
the first pulse width (t2-t1) is a function of current Iad and voltage Vad, a fuzzy set M { Iad, Vad, (t2-t1) } is established according to the actual product test effect, and a correspondingly determined (t2-t1) value is searched from the fuzzy set M { Iad, Vad, (t2-t1) } through Iad and Vad values detected at the previous time;
the second and third pulses and their off-times follow the following relationship:
(t4-t2)=2×(t6-t4),
namely: the off-point t2 in the first pulse width, the off-point t4 in the second pulse width, and the off-point t6 in the third pulse width are present: (t4-t2) 2 × (t6-t4),
the (t4-t2) is related to the voltage Vad, the range of the Vad (Vad. min, Vad. max) is divided into 4-15 gears, each gear corresponds to a determined (t4-t2) value, the range of (t4-t2) is between 200 microseconds and 600 microseconds, and the higher the voltage Vad is, the smaller the value is.
The numerical values of the cubic pulse widths (t2-t1), (t4-t3) and (t6-t5), and the method adopted in the technical scheme provided by the invention uses a fuzzy set control mode. The original design data is that PFC effect simulation is carried out by using simulation software according to a circuit schematic block diagram of the invention, and the inductance of an inductor L1, a current value corresponding to a current Iad value and a voltage value corresponding to a voltage Vad are simulated according to the current of 2A, 2.5A, 3A, 3.5A, 170V, 180V, 190V, 200V, 210V, 220V, 230V, 240V, 250V and 260V.
Using the above formula, together with the following formula:
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since the value of the inductor L1 is uniquely determined in a real product, the ac mains input voltage amplitude Vp has the following relationship with the peak voltage Vdcp of the rectified voltage Vdc of the bridge rectifier BD1 for a fixed inductor value L1:
Vp=Vdcp+α。
α: correction coefficients related to the current value Ip and the voltage amplitude Vp are used to compensate the voltage drop across the inductor L1 and the voltage drop across all the rectifier diodes in the entire loop; the rectifier diode is referred to herein as a rectifier bridge stack BD 1;
during simulation, alpha participates in the correction operation, so that:
V(t)=(Vdcp+α)SIN(100πt)
after simulation, values of 3-time pulse widths (t2-t1), (t4-t3) and (t6-t5) corresponding to the optimal Iad value and the optimal Vad value under the premise of fixing the L1 inductor value are obtained, a fuzzy set M { Iad, Vad, (t2-t1) } and corresponding (t4-t3) and (t6-t5) values are formed for actual control, and meanwhile, an actual circuit is used for correcting a simulation result, and finally, a practical fuzzy set M { Iad, Vad, (t2-t1) } and corresponding (t4-t3) and (t6-t5) numerical table are obtained.
To ensure that the crossover event where the current is not zero at the zero crossing time does not occur, the interval between the time of the zero crossing t0 and the turn-on time t1 of the first pulse is at least 100 microseconds.
Because the switching frequency of a part of PFC devices is lower, only chopping is carried out for several times in a half-wave period of mains supply, the generated interference is greatly reduced compared with the full-active PFC, and meanwhile, because a BOOST circuit structure is used, the voltage is raised, so that the voltage is not obviously reduced, the power factor can be about 0.95 when the circuit parameters are properly adjusted, and can be adjusted to 0.99 at most; and meanwhile, the device cost is relatively low.
The invention selects a proper inductor L1 according to the maximum power when the practical product is applied, can realize the optimal power factor control after simulation, has simple control software programming and lower cost, the power factor reaches more than 0.94 and can reach 0.99 at most, simultaneously, the output direct current voltage is greatly improved compared with the passive PFC, and the EMC effect is much better than the full active PFC.
Drawings
Fig. 1 is a block diagram illustrating the operation of the first embodiment of the present invention.
FIG. 2 is a block diagram of the working principle of the MCU
FIG. 3 is a 100Hz sine half wave waveform of the first embodiment of the present invention.
FIG. 4 is a diagram of modulation timing and waveforms according to a first embodiment of the present invention.
Fig. 5 is a block diagram illustrating the operation of the second embodiment of the present invention.
Fig. 6 is a functional block diagram of a third embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and examples.
First embodiment
Referring to fig. 1-4, a partial PFC device includes a bridge rectifier BD1, a utility power, a current sampling circuit 1, a zero-crossing detection circuit 2, an inductor L1, a current-steering diode D1, a current-steering diode D2, a power electronic switch G1, a voltage sampling circuit 4, a PFC driving circuit 3, and a main control MCU 5. The live wire L of the commercial power is connected with the anode of the flow guide diode D1, the alternating current input end AC1 of the rectifier bridge stack BD1 and one sampling point of the zero-crossing detection circuit 2; a zero line N of commercial power is connected with one end of the current sampling circuit 1; the other end of the current sampling circuit 1 is connected with one end of an inductor L1 and the other sampling point of the zero-crossing detection circuit 2; the other end of the inductor L1 is connected with the anode of the flow guide diode D2 and the other alternating current input end AC2 of the rectifier bridge stack BD 1; the current inflow end 2 of the power electronic switch G1 is connected with the cathodes of the flow guide diode D1 and the flow guide diode D2; the current outflow end 3 of the power electronic switch G1 is connected with the DC output negative end V-of the rectifier bridge stack BD1, and one sampling end of the voltage sampling circuit 4; the other sampling end of the voltage sampling circuit 4 is connected with a direct current output positive end V + of the rectifier bridge stack BD 1; the control electrode 1 of the power electronic switch G1 is connected with the output stage of the PFC driving circuit 3; the main control MCU5 is connected to the output of the zero-cross detection circuit 2, the output of the voltage sampling circuit 4, the output of the current sampling circuit 1, and the input of the PFC drive circuit 3.
The master MCU5 includes an AD conversion unit AD1, an AD conversion unit AD2, an advanced timer unit timer 3, and a widening pulse signal generation unit PWM 4.
The current sampling circuit adopts a peak detection mode, and the time constant of detection is about 100 milliseconds; the voltage sampling circuit adopts a peak detection mode, and the time constant of detection is about 100 milliseconds; when the timer 3 of the main control MCU5 receives the rising edge trigger of the zero-crossing signal from the zero-crossing detection circuit 2, the timer 3 starts timing from zero to count time to 5.5 ms, and at this time, according to the test of the actual product, the current and voltage Vdc reach the peak value, the AD conversion units AD1 and AD2 start to sample the current peak value and the voltage peak value of the voltage Vdc rectified by the rectifier bridge stack BD1, and the sampled current value is Iad and the voltage value is Vad. Inductor L1 is selected to have a value of 20mH and a maximum workload current of 10A.
When the current peak value reaches 3A, starting the correction function of part of the PFC device; when the current peak value is lower than 2A, part of the regulation function of the PFC device is exited.
The partial PFC adopts a three-time pulse regulation mode, and three-time pulse widths (t2-t1), (t4-t3) and (t6-t5) are determined by inductance of an inductor L1 and Iad and Vad; for the inductor L1, 20mH inductance, the tertiary pulse widths (t2-t1), (t4-t3), (t6-t5) and the pulse intervals (t3-t2) and (t5-t4) corresponding to different Iad and Vad are different.
The turn-off point t2 of the first pulse, which is related to the current Iad, satisfies the following equation:
t2=2000+Iad×n,
and n is a coefficient and is determined according to actual simulation and debugging.
The first pulse width (t2-t1) is a function of current Iad and voltage Vad, and a fuzzy set M { Iad, Vad, (t2-t1) } is established according to a partial PFC effect simulation established by the working principle of FIG. 1 and combined with an actual product test effect, wherein the determined Iad, Vad corresponds to a (t2-t1) value;
in practical applications, the current Iad and Vad are only available after the adjustment of a part of PFC devices, so that the Iad and Vad values detected at the previous time are used, a correspondingly determined (t2-t1) value is searched from the fuzzy set M { Iad, Vad, (t2-t1) }, and the timing moments t1 and t2 of the timer 3 are determined through the processing of the main control MCU 5;
the second and third pulses and their off-times follow the following relationship:
(t4-t2)=2×(t6-t4),
(t4-t2) is related to the voltage Vad, and the range of Vad (Vad. min, Vad. max) is divided into 5 gears, and the value of (t4-t2) corresponding to each gear is as follows: 480 microseconds, 460 microseconds, 440 microseconds, 420 microseconds, and 400 microseconds, the higher the voltage Vad, the smaller its value.
PFC effect simulation is performed by simulation software according to the operational functional block diagram of fig. 1, and the inductor L1 is simulated by 20mH, a current value corresponding to the current Iad, and a voltage value corresponding to the voltage Vad at intervals of 150V, 160V, 170V, 180V, 190V, 200V, 210V, 220V, 230V, 240V, 250V, and 260V with current according to 2A, 2.5A, 3A, 3.5A,. and.. 11A.
While using the above formula, the following formula is used:
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the ac mains input voltage amplitude Vp has the following relationship with the peak voltage Vdcp of the rectified voltage Vdc of the bridge rectifier BD 1:
Vp=Vdcp+α。
α: correction coefficients related to the current value Ip and the voltage amplitude Vp are used to compensate the voltage drop across the inductor L1 and the voltage drop across all the rectifier diodes in the entire loop; the rectifier diode refers to the rectifier bridge stack BD 1;
during simulation, alpha participates in the correction operation, so that:
V(t)=(Vdcp+α)SIN(100πt),
after simulation, on the premise that the L1 is 20mH inductance value, the values of the optimal triple pulse width (t2-t1), (t4-t3) and (t6-t5) corresponding to the Iad value and the Vad value under a higher target power factor are obtained, a fuzzy set M { Iad, Vad, (t2-t1) } and the corresponding values (t4-t3) and (t6-t5) are formed, meanwhile, an actual circuit is used for testing, the simulation result is corrected according to the test result, and finally, a practical fuzzy set M { Iad, Vad, (t2-t1) } and the corresponding numerical value tables (t4-t3) and (t6-t5) are obtained.
The dotted line portion in fig. 3 is a portion of the driving pulse waveform of the PFC device, and a square wave whose amplitude is a little lower is a zero-crossing signal. As shown in fig. 3 and 4, the power factor correction method is to determine the zero-crossing time t0 after the MCU5 detects the rising edge of the zero-crossing signal, start the timer 3 to start timing, and search the fuzzy set M according to the Iad value and Vad value recorded last time to obtain the values of (t2-t1), (t4-t3), and (t6-t 5).
Starting timing by a timer 3 from a zero-crossing time t0, when timing reaches a time t1, generating a driving pulse with a pulse width of (t2-t1) by a width-widening pulse signal generating unit PWM4, controlling a power electronic switch G1 through a PFC driving circuit 3 to enable a power electronic switch G1 to be switched on, and when the commercial power is in a positive half cycle, performing energy storage and charging on an inductor L1 through a diversion diode D1, the power electronic switch G1 and a direct current output negative terminal V-to another alternating current input terminal AC2 of a rectifier bridge stack BD 1; if the current is the negative half cycle of the commercial power, the inductor L1 is charged with stored energy through the diversion diode D2, the power electronic switch G1 and the negative end V-to-AC 1 end of the direct current output of the rectifier bridge stack BD 1; the output of the width-pulse-signal-generating unit PWM4 is turned off at a time t2 clocked by the timer 3, thereby turning off the power electronic switch G1, and the energy stored in the inductor L1 is discharged to the subsequent stage through the bridge rectifier BD 1.
By repeating the above steps, the width-width pulse signal generating unit PWM4 generates three high-level pulse signals in total, the PFC driving circuit 3 drives the power electronic switch G1 to close three times, the inductor L1 is charged with stored energy, and the inductor L1 discharges to the rear stage through the bridge rectifier BD1 during the subsequent off period of each pulse signal, so as to realize the power factor correction function.
To ensure that the crossover event where the current is not zero at the zero crossing time does not occur, the interval between the time of the zero crossing t0 and the turn-on time t1 of the first pulse is at least 100 microseconds.
Second embodiment
Referring to fig. 5 and fig. 2 to 4, a part of the PFC device includes a bridge rectifier BD1, a commercial power, a current sampling circuit 1, a zero-crossing detection circuit 2, an inductor L1, a steering diode D1, a steering diode D2, a power electronic switch G1, a voltage sampling circuit 4, a PFC driving circuit 3, and a main control MCU 5. The live wire L of the commercial power is connected with the cathode of the flow guide diode D1, the alternating current input end AC1 of the rectifier bridge stack BD1 and one sampling point of the zero-crossing detection circuit 2; a zero line N of commercial power is connected with one end of the current sampling circuit 1; the other end of the current sampling circuit 1 is connected with one end of an inductor L1 and the other sampling point of the zero-crossing detection circuit 2; the other end of the inductor L1 is connected with the cathode of the flow guide diode D2 and the other alternating current input end AC2 of the rectifier bridge stack BD 1; the current output end 3 of the power electronic switch G1 is connected with the anodes of the flow guide diode D1 and the flow guide diode D2; the current inflow end 2 of the power electronic switch G1 is connected with the direct current output positive end V + of the rectifier bridge stack BD1 and one sampling end of the voltage sampling circuit 4; the other sampling end of the voltage sampling circuit 4 is connected with the DC output negative end V-of the rectifier bridge stack BD 1; the control electrode 1 of the power electronic switch G1 is connected with the output stage of the PFC driving circuit 3; the main control MCU5 is connected to the output of the zero-cross detection circuit 2, the output of the voltage sampling circuit 4, the output of the current sampling circuit 1, and the input of the PFC drive circuit 3.
The rest of the parts which are not described are seen in the first embodiment and are not repeated.
Third embodiment
Referring to fig. 6 and fig. 2 to 4, a part of the PFC device includes a bridge rectifier BD1, a commercial power, a current sampling circuit 1, a zero-crossing detection circuit 2, an inductor L1, a steering diode D1, a steering diode D2, a power electronic switch G1, a voltage sampling circuit 4, a PFC driving circuit 3, and a main control MCU 5. The live wire L of the commercial power is connected with one end of the inductor L1 and one sampling point of the zero-crossing detection circuit 2; the other end of the inductor L1 is connected with the cathode of the flow guide diode D1 and the alternating current input end AC1 of the rectifier bridge stack BD 1; a zero line N of commercial power is connected with one end of the current sampling circuit 1; the other end of the current sampling circuit 1 is connected with the other sampling point of the zero-crossing detection circuit 2, the cathode of the flow-guiding diode D2 and the other alternating current input end AC2 of the rectifier bridge stack BD 1; the current inflow end 2 of the power electronic switch G1 is connected with the direct current output positive end V + of the rectifier bridge stack BD1 and one sampling end of the voltage sampling circuit 4; the current outflow end 3 of the power electronic switch G1 is connected with the anodes of the flow guide diode D1 and the flow guide diode D2; the other sampling end of the voltage sampling circuit 4 is connected with the DC output negative end V-of the rectifier bridge stack BD 1; the control electrode 1 of the power electronic switch G1 is connected with the output stage of the PFC driving circuit 3; the main control MCU5 is connected to the output of the zero-cross detection circuit 2, the output of the voltage sampling circuit 4, the output of the current sampling circuit 1, and the input of the PFC drive circuit 3.
The rest of the parts which are not described are seen in the first embodiment and are not repeated.