CN101789259B - Order-based layered data processing method and device applied to flash memory - Google Patents
Order-based layered data processing method and device applied to flash memory Download PDFInfo
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Abstract
The invention discloses an order-based layered data processing method and a device thereof applied to a flash memory. In the method, communication between a master control end and the flash memory is processed respectively by a high-order translation layer and a low-order processing layer, wherein the high-order translation layer is in charge of receiving instructions and logic addresses of the master control end and translating the received logic addresses into real addresses of the flash memory; and the low-order processing layer is in charge of controlling a memory unit corresponding to the flash memory in order to process data according to the instructions and the real addresses transmitted by the high-order translation layer. The low-order processing layer is arranged between the high-order translation layer and the flash memory, so that the high-order translation is independent of the structure of the flash memory and is not necessarily redesigned due to the replacement of the flash memory.
Description
Technical field
The present invention relates to a kind of method and relevant flash memory device that is applied to the flash memory processes data, more particularly, relate to a kind of method and relevant flash memory device that is applied to the order-based layered data processing of flash memory.
Background technology
Flash memory (Flash memory) is a kind of nonvolatile solid state memory (Non-violate solid state memory).Flash memory has advantages of that compared to traditional nonvolatile solid state memory the unit carrying cost is low, read or write speed is fast.On the other hand, flash memory has better shock resistance compared to hard disk.That is to say, the data of storage more can not damaged because of vibrations.Therefore because flash memory has above characteristic, often be used in portable apparatus (as digital walkman, digital camera, mobile phone, storage card and USB portable disk etc.) the inside as storage medium.
Flash memory has a lot of different types, such as single-order storage unit (Single LevelCell, SLC) the little independent block of having classified (small block) flash memory, single-order storage unit independent block (large block) flash memory of greatly having classified, and multi-level cell memory (Multi-Level Cell, MLC) independent block (large block) flash memory of greatly having classified ... etc.Flash memory has a lot of different manufacturers, such as Samsung, Hynix and Toshiba... etc.Dissimilar flash memory or the flash memory of different manufacturers have different structures and different control methods.For example, each independent block of having classified of the little independent block flash memory of having classified of SLC comprises 32 block pagings (page) of having classified; Each block paging of having classified comprises 528 bytes (byte), and wherein front 512 bytes are data field (data area), and then 16 bytes are reserved area (spare area).Greatly classified each independent block of having classified of independent block flash memory of SLC comprises 64 block pagings of having classified; Each block paging of having classified comprises 2112 bytes, and wherein front 2048 bytes are the data field, and then 64 bytes are the reserved area.
Please refer to Fig. 1.Fig. 1 is the schematic diagram of flash memory translation layer (Flash TranslationLayer) FTL of explanation prior art.Flash memory translation layer FTL is between a main control end H and a flash memory M
F1Between.
Flash memory M
F1Comprise (the individual independent block BL that classified of M * N)
11～BL
MNFlash memory translation layer FTL is in order to receiving or to respond the requirement from main control end H, and to flash memory M
F1Carry out data and process action.In addition, main control end H can be user side application program and/or a file system.
Flash memory translation layer FTL reads flash memory M
F1The hardware structure information D
SPECMore particularly, flash memory translation layer FTL reads flash memory M
F1Model ID
FLASHTo obtain relevant flash memory M
F1Type (as the SLC independent block of greatly having classified), manufacturer (as Samsung), structure (as the independent number of blocks of classifying), capacity, control method ... the hardware structure information D that waits
SPECFlash memory translation layer FTL is according to the hardware structure information D
SPECDescribed flash memory M
F1Structure, take conversion logic address (Logic Address, LA) as one corresponding to flash memory M
F1The physical address (Physical Address, PA) of an entity stores unit.Then, flash memory translation layer FTL is according to the hardware structure information D that receives
SPEC, find corresponding to flash memory M
F1Control method, to control flash memory M
F1Carry out data and process action.Thus, main control end H just can pass through flash memory translation layer FTL, requires flash memory M
F1, carry out data and process action.For instance, as main control end H to flash memory M
F1When sending data and processing requiring of action and transmit logical address for " P " (table one numerical value) during to flash memory translation layer FTL, flash memory translation layer FTL can translation logic address " P " be physical address " X ", and requires flash memory M
F1In the BL of classification independent blocks
X, carry out the action that data are processed.
It should be noted that because flash memory translation layer FTL needs directly to control flash memory M
F1, therefore, flash memory translation layer FTL needs according to flash memory M
F1Control method and structure design.Yet the flash memory of different manufacturers or dissimilar flash memory have different control methods and structure.Therefore, whenever flash memory M
F1(as the flash memory of Samsung production) is replaced by another novel flash memory M
F2When (as the flash memory of Toshiba production), flash memory translation layer FTL just need to be according to novel flash memory M
F2Control method and structure, redesign.Thus, just can cause user's inconvenience greatly.
Summary of the invention
The invention provides a kind of method that is applied to the order-based layered data processing of a flash memory.the method comprises and a logical address is sent to a high-order translation layer processes action to require to carry out data in this flash memory, obtained by a low-order processing layer belong to this flash memory a hardware structure information so that this hardware structure information is sent to this high-order translation layer, by this high-order translation layer according to this hardware structure information, in this flash memory, one group of entity stores unit that corresponds to this logical address is set, by this high-order translation layer according to this hardware structure information, find out in this group and correspond in the entity stores unit of this logical address, have one can process the entity stores unit that moves for carrying out data, by this high-order translation layer according to this hardware structure information, determine a flow chart of data processing, with this logical address is converted to correspond to this can be for a physical address that carries out data and process the entity stores unit of action, and by low order processing layer basis this physical address by this high-order translation layer transmission, can be in carrying out data and processing the entity stores unit of action at this, carry out these data and process action.This high-order translation layer is processed in order to make a user side application program and a file system can carry out data in this flash memory, and is responsible for collecting this flash memory and uses the relevant information of state to manage this flash memory.The low order processing layer learns that according to the first paragraph address date in this physical address one group of block of having classified, low order processing layer learn that according to the second segment address date in this physical address classified an independent block, low order processing layer learn that according to one the 3rd sector address data in this physical address classified a block paging, low order processing layer learn the block passage of having classified according to one the 4th sector address data in this physical address.
The present invention separately provides a kind of method that is applied to the order-based layered data processing of a flash memory.the method comprises and a logical address is sent to a high-order translation layer processes action to require to carry out data in this flash memory, obtained by a flash architecture processing layer belong to this flash memory a hardware structure information so that this hardware structure information is sent to this high-order translation layer, by this high-order translation layer according to this hardware structure information, in this flash memory, one group of entity stores unit that corresponds to this logical address is set, by this high-order translation layer according to this hardware structure information, find out in this group and correspond in the entity stores unit of this logical address, have one can process the entity stores unit that moves for carrying out data, by this high-order translation layer according to this hardware structure information, determine a flow chart of data processing with this logical address is converted to correspond to this can be for a physical address that carries out data and process the entity stores unit of action, and by this flash architecture processing layer basis this physical address by this high-order translation layer transmission, can be in carrying out data and processing the entity stores unit of action at this, carry out these data and process action.This high-order translation layer is processed in order to make a user side application program and a file system can carry out data in this flash memory, and is responsible for collecting this flash memory and uses the relevant information of state to manage this flash memory.this flash architecture processing layer is learnt one group of block of having classified according to the first paragraph address date in this physical address, this flash architecture processing layer is learnt the independent block of having classified according to the second segment address date in this physical address, this flash architecture processing layer is learnt the block paging of having classified according to one the 3rd sector address data in this physical address, this flash architecture processing layer is learnt the paging section of having classified according to one the 4th sector address data in this physical address, this flash architecture processing layer is learnt the block passage of having classified according to one the 5th sector address data in this physical address.
The present invention separately provides a kind of flash memory device that uses order-based layered data processing.This flash memory device comprises a flash memory, by a plurality of independent blocks of having classified form, order and a logical address change-over circuit, and a fill order and physical address addressing circuit.this order and logical address change-over circuit carry out in order to make a high-order translation layer receive a logical address and a requirement that data are processed action in this flash memory, order a low-order processing layer to obtain and belong to a hardware structure information of this flash memory so that this hardware structure information is sent to this high-order translation layer, and make this high-order translation layer according to this hardware structure information, in these a plurality of independent blocks of having classified, one group of entity stores unit that corresponds to this logical address is set, find out in this group and correspond in the entity stores unit of this logical address, have one can process the entity stores unit that moves for carrying out data, and determine a flow chart of data processing with this logical address is converted to correspond to this can be for a physical address that carries out data and process the entity stores unit of action.This fill order and physical address addressing circuit be in order to making the low order processing layer according to this physical address that is transmitted by this high-order translation layer, can in carrying out data and processing the entity stores unit of action, carry out this data and process action at this.This high-order translation layer is processed in order to make a user side application program and a file system can carry out data in this flash memory, and is responsible for collecting this flash memory and uses the relevant information of state to manage this flash memory.The low order processing layer learns that according to the first paragraph address date in this physical address one group of block of having classified, low order processing layer learn that according to the second segment address date in this physical address classified an independent block, low order processing layer learn that according to one the 3rd sector address data in this physical address classified a block paging, low order processing layer learn the block passage of having classified according to one the 4th sector address data in this physical address.
Description of drawings
Fig. 1 is the schematic diagram of the flash memory translation layer of explanation prior art.
Fig. 2 is applied to the schematic diagram of the order-based layered data processing of flash memory for explanation the present invention.
Fig. 3 is applied to the process flow diagram of method of the order-based layered data processing of a flash memory for explanation the present invention.
According to logical address, reservation information, and in fact question blank finds out the schematic diagram of the entity stores unit that can process for data to Fig. 4 for explanation high-order translation layer.
Fig. 5 is the process flow diagram of one first embodiment of explanation flow chart of data processing of the present invention.
Fig. 6 is the process flow diagram of one second embodiment of explanation flow chart of data processing of the present invention.
Fig. 7 is the process flow diagram of one the 3rd embodiment of explanation flow chart of data processing of the present invention.
Fig. 8 is the schematic diagram of the flash memory device of use order-based layered data processing of the present invention.
[main element symbol description]
The H main control end
FTL flash memory translation layer
M
F, M
F1Flash memory
BL
11～BL
MNThe independent block of having classified
HTL high-order translation layer
The LAL low-order processing layer
CH
1～CH
MThe block passage of having classified
BK
1～BK
NOrganize the block of having classified
PG
0、PG
1、PG
2、PG
3、PG
4、
The block paging of having classified
PG
Y
ST
ZThe paging section of having classified
The P logical address
The X physical address
T
BQuestion blank
D
SPReservation information
301～309、501～505、
Step
601～605、701～705
800 flash memory devices
810 order and logical address change-over circuits
811 logic judging circuits
Fill order and physical address addressing
820
Circuit
Embodiment
In view of this, the present invention is divided into high-order translation layer (High-level Translation Layer with flash memory translation layer FTL, HTL) with low-order processing layer (Low-level AbstractionLayer, LAL), to solve as the flash memory M that is originally used
F1Be replaced by another novel flash memory M
F2The time, whole flash memory translation layer FTL needs the puzzlement that redesigns.Wherein, low-order processing layer LAL can be flash architecture processing layer (Flash Abstraction Layer) FAL; And high-order translation layer HTL can be flash architecture translation layer (Flash Translation Layer, FTL).
Please refer to Fig. 2.Fig. 2 is applied to the schematic diagram of the order-based layered data processing of flash memory for explanation the present invention.As shown in Figure 2, high-order translation layer HTL is between main control end H and low-order processing layer LAL; Low-order processing layer LAL is between high-order translation layer HTL and flash memory M
FBetween.The design of high-order translation layer HTL and flash memory M
FControl method irrelevant; The design of low-order processing layer LAL must be according to flash memory M
FDifference and change.In Fig. 2, CH represent to classify block passage (channel), BK represents one group of block (bank) of having classified, BL independent block (block), PG block paging (page), ST paging section (sector) that represents to classify that represents to classify that represents to classify.
High-order translation layer FTL is in order to make main control end H that (as a user side application program or a file system) can be at flash memory M
FIn carry out data and process, be responsible for collecting flash memory M
FThe relevant information of use state, and management flash memory M
FIn addition, the isolated requirement that is sent by main control end H of high-order translation layer FTL directly enters low order processing layer LAL.
Low-order processing layer LAL is between high-order translation layer HTL and flash memory M
FBetween, in order to the order of execution by high-order translation layer HTL transmission, and with flash memory M
FThe hardware structure information D
SPECAnd by flash memory M
FA reservation information D that obtains
SP(spare data) is back to high-order translation layer HTL.Similarly, low-order processing layer LAL can be by reading flash memory M
FModel ID
FLASHTo obtain relevant flash memory M
FType (as the SLC independent block of greatly having classified), manufacturer (as Samsung), structure (as the independent number of blocks of classifying), capacity, control method ... the hardware structure information D that waits
SPECIn addition, the order of the isolated high-order translation layer HTL transmission of low-order processing layer LAL directly enters flash memory M
F
Thus, because low-order processing layer LAL has completely cut off high-order translation layer HTL and flash memory M
FBetween direct communication (meaning is that flash memory M is controlled in the order that low-order processing layer LAL can send according to high-order translation layer HTL
F, and the order that high-order translation layer HTL sends can not directly be conveyed to flash memory M
F), no matter so flash memory M
FTo be replaced by flash memory M
F1Or M
F2, have any impact for high-order translation layer HTL is neither, and can economize except high-order translation layer HTL because flash memory M
FThe puzzlement that causes of replacing.
Please refer to Fig. 3.Fig. 3 is applied to the process flow diagram of method 300 of the order-based layered data processing of a flash memory for explanation the present invention.Step is described as follows:
Step 301: send the first order CMD by high-order translation layer HTL
1Belong to flash memory M to indicate low-order processing layer LAL, to obtain
F1The hardware structure information D
SPEC1
Step 302: by low-order processing layer LAL, according to the first order CMD
1, obtain and belong to flash memory M
F1The hardware structure information D
SPEC1, and be sent to high-order translation layer HTL;
Step 303: send the second order CMD by high-order translation layer HTL
2Belong to flash memory M to indicate low-order processing layer LAL, to obtain
FThe reservation information D
SP1
Step 304: by low-order processing layer LAL, according to the second order CMD
2, obtain and belong to flash memory M
F1The reservation information D
SP1, and be sent to high-order translation layer HTL;
Step 305: main control end H is sent to high-order translation layer HTL to require at flash memory M with a logical address " P "
F1In carry out data and process action;
Step 306: by high-order translation layer HTL according to the hardware structure information D
SPEC1, at flash memory M
F1In, one group of entity stores unit that corresponds to logical address " P " is set;
Step 307: by high-order translation layer HTL according to keeping information D
SP1, find out in this group and correspond in the entity stores unit of logical address " P ", having one can be for the entity stores unit that carries out data and process action;
Step 308: by high-order translation layer HTL according to the hardware structure information D
SPEC1With the reservation information D
SP1, determine a flow chart of data processing DPS, with logical address " P " is converted to correspond to this can be for a physical address " X " that carries out data and process the entity stores unit of action;
Step 309: according to the physical address " X " that is transmitted by high-order translation layer HTL, can in carrying out data and processing the entity stores unit of action, be carried out this data and process action at this by low-order processing layer LAL.
In method 300, as a novel flash memory M
F2Replace flash memory M
F1The time, method 300 can reset a novel low-order processing layer LAL
2(establishing original low-order processing layer is LAL to replace original low-order processing layer LAL
1), and by novel low-order processing layer LAL
2Obtain and belong to novel flash memory M
F2The hardware structure information D
SPEC2With the reservation information D
SPWith with the hardware structure information D
SPEC2With the reservation information D
SPBe sent to high-order translation layer HTL.In other words, as a novel flash memory M
F2Replace original flash memory M
F1The time, step 301～308 just can re-start once again, need reset to inform high-order translation layer HTL the mode that logical address is translated into physical address.
In step 309, the physical address " X " that low-order processing layer LAL can send according to high-order translation layer HTL is learnt at flash memory M
F1In in fact corresponding one block passage, one group of block (Bank), of having classified independent block, the block paging of having classified of having classified of having classified, and the paging section of having classified.In other words, physical address " X " can be distinguished into five sections for (x
1, x
2, x
3, x
4, x
5).First paragraph physical address " x
1" numerical value represent and correspond to flash memory M on entity
F1The middle block passage of having classified that distributes; Second segment physical address " x
2" numerical value represent and correspond to flash memory M on entity
F1Middle a group of the distributing block of having classified; The 3rd section physical address " x
3" numerical value represent and correspond to flash memory M on entity
F1The middle independent block of having classified that distributes; The 4th section physical address " x
4" numerical value represent and correspond to flash memory M on entity
F1The middle block paging of having classified that distributes; The 5th section physical address " x
5" numerical value represent and correspond to flash memory M on entity
F1The middle paging section of having classified that distributes.For instance, if physical address X is (1,1,1,1,1), is illustrated on entity and can be positioned at flash memory M for the entity stores unary system of carrying out data processing action
F1The block of classification channel C H
1In one group of block BK that classified
1In the independent block BL of classification
1In the block of classification paging PG
1In the paging of classification section ST
1
In addition, hardware structure information D
SPEC1Providing can be at flash memory M
F1Plan row classified block passage, group classified block, classified independent block, the classify information of block paging and the paging section of having classified.For instance, hardware structure information D
SPEC1Can be (10,10,10,64,4), be illustrated in flash memory M
F1In, there are 10 block passages of having classified, each block passage of having classified to comprise 10 groups of blocks of having classified, every group of block of having classified and comprise that 10 independent blocks of having classified, each independent block of having classified comprise 64 block pagings of having classified, each block paging of having classified comprises 4 paging sections of having classified.In addition, the classified size of paging section of one of General Definition is 512 bytes, therefore need to be in the hardware structure information D
SPEC1In provide.
Therefore, high-order translation layer HTL just can be according to the hardware structure information D
SPEC1, physical address " X " corresponding to logical address " P " convert to.As previously mentioned, if the hardware structure information D
SPEC1Be (10,10,10,64,4), logical address " X " is [123456] for example, high-order translation layer HTL can be with [123456] divided by 25600 (10 * 10 * 64 * 4, represent the size of the block passage of having classified), obtain 4 and remaining 21056 (presentation-entity address x
1Be 4); Again with remainder [21056] divided by 2560 (10 * 64 * 4, represent the size of one group of block of having classified), obtain 8 and remaining 576 (presentation-entity address x
2Be 8); Again with remainder [576] divided by 256 (64 * 4, expression one classified the size of independent block), obtain 2 and remaining 64 (presentation-entity address x
3Be 2); Again with remainder [64] divided by 4 (4, expression one classified the size of block paging), obtain 16 and remaining 0 (presentation-entity address x
4Be 4 and physical address x
5Be remainder 0).Briefly, when logical address " P " was [123456], high-order translation layer HTL was according to the hardware structure information D
SPEC1The physical address X that translates out is (4,8,2,16,0), and it is expressed as flash memory M
F1In the 4th the block channel C H that classifies
4In the 8th group of block BK that classifies
8In the 2nd the independent block BL that classifies
2In the 16th the block paging PG that classifies
16In the 0th the paging section ST that classifies
0
Yet in flash memory, one has the block of the classification paging of storage data can't be written into data again.More particularly, if data are write to the block of the classification paging of storage data, must first wipe this affiliated independent block of classification of block paging of having classified.The action of at every turn wiping (erase) data is as unit with one " the independent block of having classified ".That is to say, the action of each obliterated data will be wiped the independent block of having classified at least, and can't only wipe classified block paging or a byte.Hereat, in order to accelerate main control end H for flash memory M
F1The data of carrying out are processed action, in high-order translation layer HTL, a question blank (Look Up Table, LUT) T can be set
B, not store the entity stores unit of data in the independent block of classifying of selecting to correspond to same logical address, carry out the action that data are processed.More particularly, when being physical address " X " in aforementioned high-order translation layer HTL translation logic address " P ", the physical address x that it is translated out
3Can't directly correspond to single the independent block of having classified, but correspond to two different independent blocks of classification, and then according to flash memory M
F1The reservation information D that provides
SP, can provide and carry out the independent block of classification that data are processed wherein is provided.Wherein keep information D
SPWhether the entity stores unit that is used to provide that the institute wish processes has had the storage data to facilitate high-order translation layer HTL to select not store the entity stores unit of data.Below will be explained in more detail its operation principles.
Please refer to Fig. 4.According to logical address, reservation information, and in fact question blank finds out the schematic diagram of the entity stores unit that can process for data to Fig. 4 for explanation high-order translation layer HTL.The same logical address " P " of lifting is that [123456] are example, physical address x as can be known
3Be " 2 ".Therefore can be from question blank T
BIn the 2nd hurdle check in corresponding to physical address x
3The independent block of classification be the independent block BL that classifies
5With BL
13And in fact want to carry out the 0th the paging section of classifying that data process entity stores unit is arranged in the 4th the block paging of classifying.By keeping information D
SPAs can be known, at the independent block BL that classifies
5In the 4th the block paging of classifying existing storage data and at the independent block BL that classifies
13In the 4th the block paging of classifying do not store data.Therefore, high-order translation layer HTL just can select the independent block BL that classified
13As the entity stores unit that in fact will carry out the data processing.More particularly, after logical address [123456] is processed through high-order translation layer HTL, can correspond to physical address for (4,8, " 13 ", 16,0) rather than physical address (4,8, " 2 ", 16,0) originally, also non-(4,8, " 5 ", 16,0).In other words, the entity stores unary system of in fact finding out via high-order translation layer HTL is positioned at flash memory M
F1In the 4th the block channel C H that classifies
4In the 8th group of block BK that classifies
8In the 13rd the independent block BL that classifies
13In the 16th the block paging PG that classifies
16In the 0th the paging section ST that classifies
0
In step 308, flow chart of data processing DPS is with deciding low-order processing layer LAL to obtain first paragraph physical address (x in physical address " X "
1), second segment physical address (x
2), the 3rd section physical address (x
3), the 4th section physical address (x
4) and the 5th section physical address (x
5) order.
Please refer to Fig. 5.Fig. 5 is the process flow diagram of one first embodiment of explanation flow chart of data processing DPS of the present invention.Step is described as follows:
Step 501: make low-order processing layer LAL obtain second segment physical address (x
2), learn at flash memory M
F1In, there is one group of corresponding block of having classified, and can processes action to data;
Step 502: after obtaining this second segment physical address, obtain the 3rd section physical address (x
3), learn at flash memory M
F1In, there is the corresponding one independent block of having classified, can process action to data;
Step 503: after obtaining the 3rd section physical address, obtain the 4th section physical address (x
4), learn at flash memory M
F1In, there is the corresponding one block paging of having classified, can process action to data;
Step 504: after obtaining the 4th section physical address, obtain the 5th section physical address (x
5), learn at flash memory M
F1In, there is the corresponding one paging section of having classified, can process action to data;
Step 505: after obtaining the 5th section physical address, obtain first paragraph physical address (x
1), learn at last at flash memory M
F1In, there is the corresponding one block passage of having classified, can process action to data.
Please refer to Fig. 6.Fig. 6 is the process flow diagram of one second embodiment of explanation flow chart of data processing DPS of the present invention.Step is described as follows:
Step 601: make low-order processing layer LAL obtain first paragraph physical address (x
1), learn at flash memory M
F1In, there is the corresponding one block passage of having classified, and can processes action to data;
Step 602: after obtaining this first paragraph physical address, obtain the 3rd section physical address (x
3), learn at flash memory M
F1In, there is the corresponding one independent block of having classified, can process action to data;
Step 603: after obtaining the 3rd section physical address, obtain the 4th section physical address (x
4), learn at flash memory M
F1In, there is the corresponding one block paging of having classified, can process action to data;
Step 604: after obtaining the 4th section physical address, obtain the 5th section physical address (x
5), learn at flash memory M
F1In, there is the corresponding one paging section of having classified, can process action to data;
Step 605: after obtaining the 5th section physical address, obtain second segment physical address (x
2), learn at last at flash memory M
F1In, there is one group of corresponding block of having classified, can process action to data.
Please refer to Fig. 7.Fig. 7 is the process flow diagram of one the 3rd embodiment of explanation flow chart of data processing DPS of the present invention.Step is described as follows:
Step 701: make low-order processing layer LAL obtain the 3rd section physical address (x
3), learn at flash memory M
F1In, there is the corresponding one independent block of having classified, and can processes action to data;
Step 702: after obtaining the 3rd section physical address, obtain second segment physical address (x
2), learn at flash memory M
F1In, there is one group of corresponding block of having classified, can process action to data;
Step 703: after obtaining this second segment physical address, obtain the 4th section physical address (x
4), learn at flash memory M
F1In, there is the corresponding one block paging of having classified, can process action to data;
Step 704: after obtaining the 4th section physical address, obtain the 5th section physical address (x
5), learn at flash memory M
F1In, there is the corresponding one paging section of having classified, can process action to data;
Step 705: after obtaining the 5th section physical address, obtain first paragraph physical address (x
1), learn at last at flash memory M
F1In, there is one group of corresponding block passage of having classified, can process action to data.
In three embodiment of above-mentioned flow chart of data processing DPS, the 5th section physical address is not for necessary, and meaning is that low-order processing layer LAL not necessarily need to process action as unit carries out data take the paging section of classifying.In other words, if the received physical address of low-order processing layer LAL only is addressed to the block paging of having classified, just low-order processing layer LAL processes action take the block paging of having classified as unit carries out data; And if the received physical address of low-order processing layer LAL is addressed to the paging section of classifying, just the low-order processing layer LAL paging section of can having classified is that unit carries out data and processes action.In addition, physical address x
3Be high-order translation layer HTL, according to logical address " P ", question blank T
BAnd reservation information D
SP, last physical address of trying to achieve (as the demonstration example of Fig. 4).
Please refer to Fig. 8.Fig. 8 is the schematic diagram of the flash memory device 800 of use order-based layered data processing of the present invention.As shown in Figure 8, flash memory device 800 comprises order and logical address change-over circuit 810, a fill order and a physical address addressing circuit 820, and a flash memory M
FFlash memory M
FComprise a plurality of independent block BL that classified
11～BL
MN
Order and logical address change-over circuit 810 are positioned at high-order translation layer HTL; Fill order and physical address addressing circuit 820 are positioned at low-order processing layer LAL.Order and logical address change-over circuit 810 also comprise a logic judging circuit 811.In Fig. 8, main control end H, high-order translation layer HTL, low-order processing layer LAL and flash memory M
FOperation principles all as aforementioned, do not repeat them here.
Order and logical address change-over circuit 810 are used for carrying out following several actions:
1. make high-order translation layer HTL receive the logical address " P " that main control end H transmits, and according to this at flash memory M
FIn carry out the requirement that data are processed action;
2. order low-order processing layer LAL obtains and belongs to flash memory M
FThe hardware structure information D
SPECTo be sent to high-order translation layer HTL;
3. make high-order translation layer HTL according to the hardware structure information D
SPECIn these a plurality of independent blocks of having classified, one group of entity stores unit that corresponds to logical address " P " is set, find out in this group and correspond in the entity stores unit of this logical address, having one can be for the entity stores unit that carries out data and process action, determine a flow chart of data processing with this logical address is converted to correspond to this can be for a physical address that carries out data and process the entity stores unit of action.
Fill order and physical address addressing circuit 820 are used for making low-order processing layer LAL according to the physical address " X " that is transmitted by high-order translation layer HTL, can in carrying out data and processing the entity stores unit of action, carry out data and process action at this.
1. make high-order translation layer HTL send an order (CMD
1Or CMD
2) obtain the hardware structure information D with indication low-order processing layer LAL
SPECAnd reservation information D
SPOne of them;
2. make low-order processing layer LAL according to the order of sending, read flash memory M
FThe hardware structure information D
SPECAnd reservation information D
SPOne of them is to be back to high-order translation layer HTL;
3. make high-order translation layer HTL according to the hardware structure information D
SPECAnd reservation information D
SP, the determination data treatment scheme is take the physical address " X " of the logical address " P " that received of conversion for correspondence.
in sum, by the present invention, the flash memory translation layer is divided into high-order translation layer and low-order processing layer, just can solve when the flash memory that originally uses is replaced by another novel flash memory, whole flash memory translation layer all needs the puzzlement that redesigns, and by low-order processing layer provided by the present invention, can be for various flash memory, the physical address that provides according to the high-order translation layer, and control method corresponding to use, directly the storage unit of correspondence is carried out the action that data are processed, so just can offer the larger convenience of user.
The above is only the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (39)
1. method that is applied to the order-based layered data processing of a flash memory comprises:
One logical address is sent to a high-order translation layer processes action to require carrying out data in this flash memory;
Obtained by a low-order processing layer belong to this flash memory a hardware structure information so that this hardware structure information is sent to this high-order translation layer;
According to this hardware structure information, in this flash memory, one group of entity stores unit that corresponds to this logical address is set by this high-order translation layer;
, found out in this group and correspond in the entity stores unit of this logical address according to this hardware structure information by this high-order translation layer, having one can be for the entity stores unit that carries out data and process action;
According to this hardware structure information, determine a flow chart of data processing by this high-order translation layer, with this logical address is converted to correspond to this can be for a physical address that carries out data and process the entity stores unit of action; And
, can in carrying out data and processing the entity stores unit of action, be carried out this data and process action at this according to this physical address of being changed by this high-order translation layer by the low order processing layer;
wherein, this high-order translation layer is processed in order to make a user side application program and a file system can carry out data in this flash memory, and be responsible for collecting this flash memory and use the relevant information of state to manage this flash memory, and, the low order processing layer is learnt one group of block of having classified according to the first paragraph address date in this physical address, learn the independent block of having classified according to the second segment address date in this physical address, learn the block paging of having classified according to one the 3rd sector address data in this physical address, learn the block passage of having classified according to one the 4th sector address data in this physical address.
2. the method for claim 1, wherein obtain by a low-order processing layer hardware structure information that belongs to this flash memory and comprise so that this hardware structure information is sent to this high-order translation layer:
Sending one first by this high-order translation layer orders to indicate the low order processing layer to obtain this hardware structure information; And
The low order processing layer reads this hardware structure information of this flash memory to be back to this high-order translation layer according to this first order.
3. method as claimed in claim 2, this hardware structure information that wherein reads this flash memory at the low order processing layer according to this first order also comprises after being back to this high-order translation layer:
Sending one second by this high-order translation layer orders to indicate the low order processing layer to obtain a reservation information; And
This reservation information that the low order processing layer reads this flash memory according to this second order to be being back to this high-order translation layer, and
Wherein by this high-order translation layer according to this hardware structure information, determine a flow chart of data processing, correspond to this and can comprise for a physical address that carries out data and process the entity stores unit of action so that this logical address is converted to:
According to this hardware structure information and this reservation information, determine this flow chart of data processing by this high-order translation layer, to be converted to this physical address.
4. the method for claim 1, wherein this high-order translation layer in order to the isolated requirement that is sent by this user side application program and this document system so that this requirement can not directly enter the low order processing layer.
5. the method for claim 1, wherein the low order processing layer is between this high-order translation layer and this flash memory, in order to carrying out the order that is sent by this high-order translation layer, and this hardware structure information and the reservation information that obtained by this flash memory are back to this high-order translation layer.
6. the method for claim 1, wherein the low order processing layer is in order to carry out the order that is sent by this high-order translation layer, the order that isolated this high-order translation layer sends be so that this order can not directly enter this flash memory, and this hardware structure information and the reservation information that obtained by this flash memory are back to this high-order translation layer.
7. the method for claim 1, wherein when the flash memory of an another type replaces this flash memory, the low-order processing layer that one another type is set replaces the low order processing layer, and the hardware structure information that is obtained an another type of the flash memory that belongs to this another type by the low-order processing layer of this another type is sent to this high-order translation layer with the hardware structure information with this another type.
8. the method for claim 1, wherein this hardware structure information provides and can plan the classified information of block, this independent block of having classified, this classified block paging and this block passage of having classified of this group at this flash memory.
9. method as claimed in claim 8, wherein this flow chart of data processing determines that low order processing layer obtains the order of this first paragraph address date, this second segment address date, the 3rd sector address data and the 4th sector address data.
10. method as claimed in claim 9, wherein this flow chart of data processing comprises:
Make the low order processing layer obtain this first paragraph address date, learn in this flash memory, have this group block of having classified, can process action to data;
After obtaining this first paragraph address date, obtain this second segment address date, learn in this flash memory, there is this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data; And
After obtaining the 3rd sector address data, obtain the 4th sector address data, learn at last in this flash memory, there is the block passage of having classified, can process action to data.
11. method as claimed in claim 9, wherein this flow chart of data processing comprises:
Make the low order processing layer obtain the 4th sector address data, learn in this flash memory, have this block passage of having classified, can process action to data;
After obtaining the 4th sector address data, obtain this second segment address date, learn in this flash memory, there is this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data; And
After obtaining the 3rd sector address data, obtain this first paragraph address date, learn at last in this flash memory, there is this group block of having classified, can process action to data.
12. method as claimed in claim 9, wherein this flow chart of data processing comprises:
Make the low order processing layer obtain this second segment address date, learn in this flash memory, have this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain this first paragraph address date, learn in this flash memory, there is this group block of having classified, can process action to data;
After obtaining this first paragraph address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data; And
After obtaining the 3rd sector address data, obtain the 4th sector address data, learn at last in this flash memory, there is the block passage of having classified, can process action to data.
13. the method for claim 1, wherein the low order processing layer is the flash architecture processing layer.
14. a method that is applied to the order-based layered data processing of a flash memory comprises:
One logical address is sent to a high-order translation layer processes action to require carrying out data in this flash memory;
Obtained by a flash architecture processing layer belong to this flash memory a hardware structure information so that this hardware structure information is sent to this high-order translation layer;
According to this hardware structure information, in this flash memory, one group of entity stores unit that corresponds to this logical address is set by this high-order translation layer;
, found out in this group and correspond in the entity stores unit of this logical address according to this hardware structure information by this high-order translation layer, having one can be for the entity stores unit that carries out data and process action;
By this high-order translation layer according to this hardware structure information, determine a flow chart of data processing with this logical address is converted to correspond to this can be for a physical address that carries out data and process the entity stores unit of action; And
, can in carrying out data and processing the entity stores unit of action, be carried out this data and process action at this according to this physical address of being changed by this high-order translation layer by this flash architecture processing layer;
wherein, this high-order translation layer is processed in order to make a user side application program and a file system can carry out data in this flash memory, and be responsible for collecting this flash memory and use the relevant information of state to manage this flash memory, and, this flash architecture processing layer is learnt one group of block of having classified according to the first paragraph address date in this physical address, learn the independent block of having classified according to the second segment address date in this physical address, learn the block paging of having classified according to one the 3rd sector address data in this physical address, learn the paging section of having classified according to one the 4th sector address data in this physical address, learn the block passage of having classified according to one the 5th sector address data in this physical address.
15. method as claimed in claim 14 wherein obtains by a flash architecture processing layer hardware structure information that belongs to this flash memory and comprises so that this hardware structure information is sent to this high-order translation layer:
Sending one first by this high-order translation layer orders to indicate this flash architecture processing layer to obtain this hardware structure information; And
This flash architecture processing layer reads this hardware structure information of this flash memory to be back to this high-order translation layer according to this first order.
16. method as claimed in claim 15, this hardware structure information that wherein reads this flash memory at this flash architecture processing layer according to this first order also comprises after being back to this high-order translation layer:
Sending one second by this high-order translation layer orders to indicate this flash architecture processing layer to obtain a reservation information; And
This reservation information that this flash architecture processing layer reads this flash memory according to this second order to be being back to this high-order translation layer, and
Wherein by this high-order translation layer according to this hardware structure information, determine that a flow chart of data processing corresponds to this and can comprise for a physical address that carries out data and process the entity stores unit of action so that this logical address is converted to:
According to this hardware structure information and this reservation information, determine that this flow chart of data processing is to be converted to this physical address by this high-order translation layer.
17. method as claimed in claim 14, wherein this high-order translation layer in order to the isolated requirement that is sent by this user side application program and this document system so that this requirement can not directly enter this flash architecture processing layer.
18. method as claimed in claim 14, wherein this flash architecture processing layer is between this high-order translation layer and this flash memory, in order to carrying out the order that is sent by this high-order translation layer, and this hardware structure information and the reservation information that obtained by this flash memory are back to this high-order translation layer.
19. method as claimed in claim 14, wherein this flash architecture processing layer is in order to carry out the order that is sent by this high-order translation layer, the order that isolated this high-order translation layer sends be so that this order can not directly enter this flash memory, and this hardware structure information and the reservation information that obtained by this flash memory are back to this high-order translation layer.
20. method as claimed in claim 14, wherein when the flash memory of an another type replaces this flash memory, the flash architecture processing layer that one another type is set replaces this flash architecture processing layer, and the hardware structure information that is obtained an another type of the flash memory that belongs to this another type by the flash architecture processing layer of this another type is sent to this high-order translation layer with the hardware structure information with this another type.
21. method as claimed in claim 14, wherein this hardware structure information provides and can plan the classified information of block, this independent block of having classified, this block paging of having classified, this classified paging section and this block passage of having classified of this group at this flash memory.
22. method as claimed in claim 21, wherein this flow chart of data processing determines that this flash architecture processing layer obtains the order of this first paragraph address date, this second segment address date, the 3rd sector address data, the 4th sector address data and the 5th sector address data.
23. method as claimed in claim 22, wherein this flow chart of data processing comprises:
Make this flash architecture processing layer obtain this first paragraph address date, learn in this flash memory, have this group block of having classified, can process action to data;
After obtaining this first paragraph address date, obtain this second segment address date, learn in this flash memory, there is this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data;
After obtaining the 3rd sector address data, obtain the 4th sector address data, learn in this flash memory, there is this paging section of having classified, can process action to data; And
After obtaining the 4th sector address data, obtain the 5th sector address data, learn at last in this flash memory, there is the block passage of having classified, can process action to data.
24. method as claimed in claim 22, wherein this flow chart of data processing comprises:
Make this flash architecture processing layer obtain the 5th sector address data, learn in this flash memory, have the block passage of having classified, can process action to data;
After obtaining the 5th sector address data, obtain this second segment address date, learn in this flash memory, there is this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data;
After obtaining the 3rd sector address data, obtain the 4th sector address data, learn in this flash memory, there is this paging section of having classified, can process action to data; And
After obtaining the 4th sector address data, obtain this first paragraph address date, learn at last in this flash memory, there is this group block of having classified, can process action to data.
25. method as claimed in claim 22, wherein this flow chart of data processing comprises:
Make this flash architecture processing layer obtain this second segment address date, learn in this flash memory, have this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain this first paragraph address date, learn in this flash memory, there is this group block of having classified, can process action to data;
After obtaining this first paragraph address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data;
After obtaining the 3rd sector address data, obtain the 4th sector address data, learn in this flash memory, there is this paging section of having classified, can process action to data; And
After obtaining the 4th sector address data, obtain the 5th sector address data, learn at last in this flash memory, there is the block passage of having classified, can process action to data.
26. method as claimed in claim 14, wherein this high-order translation layer is the flash architecture translation layer.
27. a flash memory device that uses order-based layered data processing comprises:
One flash memory is comprised of a plurality of independent blocks of having classified;
one order and logical address change-over circuit, carry out in order to make a high-order translation layer receive a logical address and a requirement that data are processed action in this flash memory, order a low-order processing layer to obtain and belong to a hardware structure information of this flash memory so that this hardware structure information is sent to this high-order translation layer, make this high-order translation layer according to this hardware structure information, in these a plurality of independent blocks of having classified, one group of entity stores unit that corresponds to this logical address is set, find out in this group and correspond in the entity stores unit of this logical address, have one can process the entity stores unit that moves for carrying out data, determine a flow chart of data processing with this logical address is converted to correspond to this can be for a physical address that carries out data and process the entity stores unit of action, and
One fill order and physical address addressing circuit in order to making the low order processing layer according to this physical address of being changed by this high-order translation layer, can in carrying out data and processing the entity stores unit of action, carry out this data and process action at this;
wherein, this high-order translation layer is processed in order to make a user side application program and a file system can carry out data in this flash memory, and be responsible for collecting this flash memory and use the relevant information of state to manage this flash memory, and, the low order processing layer is learnt one group of block of having classified according to the first paragraph address date in this physical address, learn the independent block of having classified according to the second segment address date in this physical address, learn the block paging of having classified according to one the 3rd sector address data in this physical address, learn the block passage of having classified according to one the 4th sector address data in this physical address.
28. device as claimed in claim 27, wherein this order and logical address change-over circuit also comprise:
One logic judging circuit, in order to make this high-order translation layer send one order to indicate the low order processing layer obtain this hardware structure information and a reservation information one of them, make the low order processing layer according to this order read this hardware structure information of this flash memory and this reservation information one of them, to be back to this high-order translation layer and to make this high-order translation layer according to this hardware structure information and this reservation information, determine that this flow chart of data processing is to be converted to this physical address.
29. device as claimed in claim 27, wherein this high-order translation layer in order to the isolated requirement that is sent by this user side application program and this document system so that this requirement can not directly enter the low order processing layer.
30. device as claimed in claim 27, wherein the low order processing layer is between this high-order translation layer and this flash memory, in order to carrying out the order that is sent by this high-order translation layer, and this hardware structure information and the reservation information that obtained by this flash memory are back to this high-order translation layer.
31. device as claimed in claim 27, wherein the low order processing layer is in order to carry out the order that is sent by this high-order translation layer, the order that isolated this high-order translation layer sends be so that this order can not directly enter this flash memory, and this hardware structure information and the reservation information that obtained by this flash memory are back to this high-order translation layer.
32. device as claimed in claim 27, wherein when the flash memory of an another type replaces this flash memory, the low-order processing layer that one another type is set replaces the low order processing layer, and the hardware structure information that is obtained an another type of the flash memory that belongs to this another type by the low-order processing layer of this another type is sent to this high-order translation layer with the hardware structure information with this another type.
33. device as claimed in claim 27, wherein this hardware structure information provides and can plan the classified information of block, this independent block of having classified, this classified block paging and this block passage of having classified of this group at this flash memory.
34. device as claimed in claim 33, wherein this flow chart of data processing decision low order processing layer is obtained the order of this first paragraph address date, this second segment address date, the 3rd sector address data and the 4th sector address data.
35. device as claimed in claim 34, wherein this flow chart of data processing comprises:
Make the low order processing layer obtain this first paragraph address date, learn in this flash memory, have this group block of having classified, can process action to data;
After obtaining this first paragraph address date, obtain this second segment address date, learn in this flash memory, there is this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data; And
After obtaining the 3rd sector address data, obtain the 4th sector address data, learn at last in this flash memory, there is the block passage of having classified, can process action to data.
36. device as claimed in claim 34, wherein this flow chart of data processing comprises:
Make the low order processing layer obtain the 4th sector address data, learn in this flash memory, have this block passage of having classified, can process action to data;
After obtaining the 4th sector address data, obtain this second segment address date, learn in this flash memory, there is this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data; And
After obtaining the 3rd sector address data, obtain this first paragraph address date, learn at last in this flash memory, there is this group block of having classified, can process action to data.
37. device as claimed in claim 34, wherein this flow chart of data processing comprises:
Make the low order processing layer obtain this second segment address date, learn in this flash memory, have this independent block of having classified, can process action to data;
After obtaining this second segment address date, obtain this first paragraph address date, learn in this flash memory, there is this group block of having classified, can process action to data;
After obtaining this first paragraph address date, obtain the 3rd sector address data, learn in this flash memory, there is this block paging of having classified, can process action to data; And
After obtaining the 3rd sector address data, obtain the 4th sector address data, learn at last in this flash memory, there is the block passage of having classified, can process action to data.
38. device as claimed in claim 27, wherein the low order processing layer is the flash architecture processing layer.
39. device as claimed in claim 27, wherein this high-order translation layer is the flash architecture translation layer.
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| CN108829348B (en) * | 2018-05-29 | 2022-03-04 | 上海兆芯集成电路有限公司 | Memory device and command reordering method |
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