CN101789259B - Hierarchical and hierarchical data processing method and device applied to flash memory - Google Patents

Abstract

A method and apparatus for hierarchical processing of data for flash memory. The method includes communicating between the host and the flash memory via a high level translation layer and a low level processing layer, respectively. The high-level translation layer is responsible for receiving commands and logical addresses of the master and converting the received logical addresses into physical addresses of the flash memory. The low-level processing layer is responsible for controlling the storage unit corresponding to the flash memory according to the instruction and the physical address transmitted by the high-level translation layer so as to process data. Since the low-level processing layer is disposed between the high-level translation layer and the flash memory, the high-level translation layer is independent of the flash memory architecture, and does not need to be redesigned due to the replacement of the flash memory.

Description

Hierarchical and hierarchical data processing method and device applied to flash memory

technical field

The present invention relates to a method for processing data applied to a flash memory and a related flash memory device, more specifically, to a method for hierarchically and hierarchically processing data applied to a flash memory and a related flash memory device.

Background technique

Flash memory (Flash memory) is a non-volatile solid state memory (Non-violate solid state memory). Compared with traditional non-volatile solid-state storage memory, flash memory has the advantages of low unit storage cost and fast read and write speed. On the other hand, flash memory has better shock resistance than hard disk. That is, stored data is less likely to be damaged by shock. Because flash memory has the above characteristics, it is often used as a storage medium in portable devices (such as digital players, digital cameras, mobile phones, memory cards, and USB flash drives, etc.).

There are many different types of flash memory, such as single-level storage unit (Single Level Cell, SLC) small classified single block (small block) flash memory, single-level storage unit large classified single block (large block) flash memory Flash memory, and multi-level cell (Multi-Level Cell, MLC) large block flash memory...etc. There are many different manufacturers of flash memory, such as Samsung, Hynix and Toshiba...etc. Different types of flash memories or flash memories of different manufacturers have different structures and different control methods. For example, each classified individual block of the SLC small classified individual block flash memory includes 32 classified block pages (page); each classified block page includes 528 bytes (byte), wherein The first 512 bytes are the data area, and the last 16 bytes are the spare area. Each classified individual block of the SLC large classified individual block flash memory includes 64 classified block pages; each classified block page contains 2112 bytes, of which the first 2048 bytes are the data area, and then 64 Bytes are reserved.

Please refer to Figure 1. FIG. 1 is a schematic diagram illustrating a prior art flash translation layer (Flash Translation Layer) FTL. The flash memory translation layer FTL is between a host H and a flash memory _MF1 .

The flash memory _MF1 includes (M×N) classified individual blocks BL ₁₁ ˜BL _MN . The flash memory translation layer FTL is used for receiving or responding to the request from the host H to perform data processing on the flash memory _MF1 . In addition, the host H can be a client application program and/or a file system.

The flash memory translation layer FTL reads the hardware architecture information D _SPEC of the flash memory M _F1 . More specifically, the flash memory translation layer FTL reads the model ID _FLASH of the flash memory _MF1 to obtain information about the type of the flash memory _MF1 (such as SLC or separate block), the manufacturer (such as Samsung), Hardware architecture information D _SPEC of structure (such as the number of classified individual blocks), capacity, control method, etc. The flash memory translation layer FTL, according to the structure of the flash memory _MF1 described in the hardware architecture information D _SPEC , converts the logical address (Logic Address, LA) into an entity corresponding to a physical storage unit of the flash memory _MF1 Address (Physical Address, PA). Then, the flash memory translation layer FTL finds a control method corresponding to the flash memory M _F1 according to the received hardware architecture information D _SPEC , so as to control the flash memory M _F1 to perform data processing actions. In this way, the host H can request the flash memory _MF1 to perform data processing through the flash memory translation layer FTL. For example, when the host H issues a data processing action request to the flash memory _MF1 and transmits the logical address "P" (value in Table 1) to the flash memory translation layer FTL, the flash memory translation layer FTL It will translate the logical address "P" into the physical address "X", and request the classified independent block BL _X in the flash memory _MF1 to perform data processing.

It should be noted that since the flash memory translation layer FTL needs to directly control the flash memory M _F1 , the flash memory translation layer FTL needs to be designed according to the control method and structure of the flash memory M _F1 . However, flash memories from different manufacturers or different types of flash memories have different control methods and structures. Therefore, whenever the flash memory _MF1 (such as the flash memory produced by Samsung) is replaced with another new type of flash memory _MF2 (such as the flash memory produced by Toshiba), the flash memory translation layer FTL needs to be based on the new type The control method and structure of the flash memory _MF2 are redesigned. As a result, great inconvenience will be caused to the user.

Contents of the invention

The invention provides a hierarchical and hierarchical data processing method applied to a flash memory. The method includes sending a logical address to a high-level translation layer to request a data processing operation in the flash memory, obtaining a hardware configuration information belonging to the flash memory from a low-level processing layer to configure the hardware The information is sent to the high-level translation layer, and the high-level translation layer is based on the hardware architecture information. In the flash memory, a group of physical storage units corresponding to the logical address is set, and the high-level translation layer is based on the hardware. Architecture information, find out in the group of physical storage units corresponding to the logical address, there is a physical storage unit that can perform data processing operations, and the high-level translation layer determines a data processing flow according to the hardware architecture information, so as to Converting the logical address into a physical address corresponding to the physical storage unit available for data processing, and the low-level processing layer according to the physical address transmitted by the high-level translation layer, in the available data processing In the physical storage unit of the processing operation, the data processing operation is performed. The high-level translation layer is used to enable a client application program and a file system to process data in the flash memory, and is responsible for collecting relevant information of the use status of the flash memory to manage the flash memory. The low-level processing layer obtains a group of classified blocks according to a first segment address data in the physical address, and the low-level processing layer obtains a classified separate area according to a second segment address data in the physical address block, the low-level processing layer obtains a classified block paging according to a third segment address data in the physical address, and the low-level processing layer obtains a classified block page according to a fourth segment address data in the physical address block channel.

The present invention further provides a method for hierarchically and hierarchically processing data applied to a flash memory. The method includes sending a logical address to a high-level translation layer to request a data processing operation in the flash memory, obtaining a hardware architecture information belonging to the flash memory from a flash architecture processing layer to use the hardware The architecture information is sent to the high-level translation layer. According to the hardware architecture information, the high-level translation layer sets a group of physical storage units corresponding to the logical address in the flash memory. The high-level translation layer according to the Hardware architecture information, find out that among the group of physical storage units corresponding to the logical address, there is a physical storage unit that can perform data processing operations, and the high-level translation layer determines a data processing flow according to the hardware architecture information. converting the logical address into a physical address corresponding to the physical storage unit available for data processing, and the processing layer of the flash architecture according to the physical address sent by the high-level translation layer in the available physical address In the physical storage unit of the data processing operation, the data processing operation is performed. The high-level translation layer is used to enable a client application program and a file system to process data in the flash memory, and is responsible for collecting relevant information of the use status of the flash memory to manage the flash memory. The flash architecture processing layer obtains a group of classified blocks according to a first segment address data in the physical address, and the flash architecture processing layer obtains a classified block according to a second segment address data in the physical address Separate blocks, the flash architecture processing layer obtains a classified block page according to a third segment address data in the physical address, and the flash architecture processing layer obtains a classified block page according to a fourth segment address data in the physical address Knowing a classified paging segment, the flash architecture processing layer obtains a classified block channel according to a fifth segment address data in the physical address.

The present invention further provides a flash memory device for processing data in layers. The flash memory device includes a flash memory, which is composed of a plurality of classified individual blocks, a command and logical address conversion circuit, and an execution command and physical address addressing circuit. The command and logical address conversion circuit is used to make a high-level translation layer receive a logical address and a request to perform a data processing operation in the flash memory, and order a low-level processing layer to obtain a hardware belonging to the flash memory architecture information to transmit the hardware architecture information to the high-level translation layer, and make the high-level translation layer set a group of entities corresponding to the logical address in the plurality of classified individual blocks according to the hardware architecture information The storage unit finds out a physical storage unit available for data processing in the group of physical storage units corresponding to the logical address, and determines a data processing flow to convert the logical address into the available physical storage unit corresponding to the logical address A physical address of the physical storage unit of the data processing action. The execution command and physical address addressing circuit is used to make the low-level processing layer perform the data processing operation in the physical storage unit available for data processing according to the physical address transmitted by the high-level translation layer. The high-level translation layer is used to enable a client application program and a file system to process data in the flash memory, and is responsible for collecting relevant information of the use status of the flash memory to manage the flash memory. The low-level processing layer obtains a group of classified blocks according to a first segment address data in the physical address, and the low-level processing layer obtains a classified separate area according to a second segment address data in the physical address block, the low-level processing layer obtains a classified block paging according to a third segment address data in the physical address, and the low-level processing layer obtains a classified block page according to a fourth segment address data in the physical address block channel.

Description of drawings

FIG. 1 is a schematic diagram illustrating a prior art flash memory translation layer.

FIG. 2 is a schematic diagram illustrating the application of the present invention to process data hierarchically and hierarchically in a flash memory.

FIG. 3 is a flowchart illustrating a method for hierarchically processing data applied to a flash memory according to the present invention.

FIG. 4 is a schematic diagram illustrating that the high-level translation layer finds the actual physical storage unit for data processing according to the logical address, reserved information, and look-up table.

FIG. 5 is a flowchart illustrating a first embodiment of the data processing procedure of the present invention.

FIG. 6 is a flowchart illustrating a second embodiment of the data processing procedure of the present invention.

FIG. 7 is a flowchart illustrating a third embodiment of the data processing procedure of the present invention.

FIG. 8 is a schematic diagram of a flash memory device using hierarchical data processing according to the present invention.

[Description of main component symbols]

H master control terminal

FTL Flash Translation Layer

M _F , M _F1 flash memory

BL ₁₁ ~ BL _MN has been classified as a separate block

HTL High-level translation layer

LAL Low Level Processing Layer

CH ₁ ~ CH _M classified block channels

BK ₁ ~ BK _N group of classified blocks

PG ₀ , PG ₁ , PG ₂ , PG ₃ , PG ₄ ,

                 

PG _Y

ST _Z sorted paged section

P Logical address

X Physical address

T _B query table

_DSP retains information

301～309, 501～505,

Steps

601～605, 701～705

800 Flash memory devices

810 Command and Logical Address Conversion Circuit

811 Logic judgment circuit

Executing commands and addressing physical addresses

820

Circuit

Detailed ways

In view of this, the present invention separates the flash memory translation layer FTL into a high-level translation layer (High-level Translation Layer, HTL) and a low-level processing layer (Low-level Abstraction Layer, LAL), in order to solve the original problem When the flash memory _MF1 is replaced with another new type of flash memory _MF2 , the entire flash memory translation layer FTL needs to be redesigned. Wherein, the low-level processing layer LAL may be a flash abstraction layer (Flash Abstraction Layer) FAL; and the high-level translation layer HTL may be a flash translation layer (Flash Translation Layer, FTL).

Please refer to Figure 2. FIG. 2 is a schematic diagram illustrating the application of the present invention to process data hierarchically and hierarchically in a flash memory. As shown in FIG. 2 , the high-level translation layer HTL is between the host H and the low-level processing layer LAL; the low-level processing layer LAL is between the high-level translation layer HTL and the flash memory _MF . The design of the high-level translation layer HTL has nothing to do with the control method of the flash memory _MF ; the design of the low-level processing layer LAL must be changed according to the difference of the flash memory _MF . In Figure 2, CH represents a classified block channel (channel), BK represents a group of classified blocks (bank), BL represents a classified individual block (block), PG represents a classified block page (page), ST represents a classified paging sector (sector).

The high-level translation layer FTL is used to enable the host control terminal H (such as a client application program or/and a file system) to perform data processing in the flash memory _MF , and is responsible for collecting relevant information on the use status of the flash memory _MF , and manage the flash memory _MF . In addition, the high-level translation layer FTL isolates the request sent by the host H from directly entering the low-level processing layer LAL.

The low-level processing layer LAL is between the high-level translation layer HTL and the flash memory _MF , and is used to execute the commands sent by the high-level translation layer HTL, and transfer the hardware structure information D _SPEC of the flash memory _MF and the A piece of reserved information D _SP (spare data) obtained by the flash memory _MF is sent back to the high-level translation layer HTL. Similarly, the low-level processing layer LAL can obtain the type (such as SLC or separate block), the manufacturer (such as Samsung), and the structure of the relevant flash memory _MF by reading the model ID _FLASH of the flash memory _MF . (such as the number of classified individual blocks), capacity, control method, etc. hardware architecture information D _SPEC . In addition, the low-level processing layer LAL isolates the commands sent by the high-level translation layer HTL from directly entering the flash memory _MF .

In this way, since the low-level processing layer LAL isolates the direct communication between the high-level translation layer HTL and the flash memory _MF (that is, the low-level processing layer LAL will control the flash according to the commands issued by the high-level translation layer HTL memory _MF , and the commands issued by the high-level translation layer HTL cannot be directly transmitted to the flash memory _MF ), so no matter whether the flash memory _MF is replaced with a flash memory _MF1 or _MF2 , for the high-level translation layer The HTL will not have any impact, and the trouble caused by the replacement of the flash memory _MF in the high-level translation layer HTL can be saved.

Please refer to Figure 3. FIG. 3 is a flowchart illustrating a method 300 for hierarchically processing data in a flash memory according to the present invention. The steps are as follows:

Step 301: The high-level translation layer HTL issues a first command CMD ₁ to instruct the low-level processing layer LAL to obtain the hardware architecture information D _SPEC1 belonging to the flash memory _MF1 ;

Step 302: The low-level processing layer LAL obtains the hardware architecture information D _SPEC1 belonging to the flash memory _MF1 according to the first command CMD ₁ , and sends it to the high-level translation layer HTL;

Step 303: The high-level translation layer HTL issues a second command CMD ₂ to instruct the low-level processing layer LAL to obtain reserved information D _SP1 belonging to the flash memory _MF ;

Step 304: The low-level processing layer LAL obtains the reserved information D _SP1 belonging to the flash memory _MF1 according to the second command CMD ₂ , and sends it to the high-level translation layer HTL;

Step 305: The host H sends a logical address "P" to the high-level translation layer HTL to request a data processing operation in the flash memory M _F1 ;

Step 306: According to the hardware architecture information D _SPEC1 , the high-level translation layer HTL sets a group of physical storage units corresponding to the logical address "P" in the flash memory _MF1 ;

Step 307: According to the retained information _DSP1 , the high-level translation layer HTL finds a physical storage unit for data processing among the group of physical storage units corresponding to the logical address “P”;

Step 308: The high-level translation layer HTL determines a data processing flow DPS according to the hardware architecture information D _SPEC1 and reserved information D _SP1 , so as to convert the logical address "P" into a physical storage unit corresponding to the data processing action a physical address "X"of;

Step 309: The low-level processing layer LAL performs the data processing operation in the physical storage unit available for data processing according to the physical address "X" transmitted by the high-level translation layer HTL.

In the method 300, when a new type of flash memory _MF2 replaces the flash memory _MF1 , the method 300 will reset a new type of low-level processing layer LAL ₂ to replace the original low-level processing layer LAL (assuming that the original low-level processing layer LAL The processing layer is LAL ₁ ), and the new low-level processing layer LAL ₂ obtains the hardware architecture information D _SPEC2 and the reserved information D _SP belonging to the new flash memory _MF2 to transmit the hardware architecture information D _SPEC2 and the reserved information D _SP to the high-level Translation layer HTL. In other words, when a new type of flash memory _MF2 replaces the original flash memory _MF1 , steps 301-308 will be performed again to inform the high-level translation layer HTL that the logical address translation needs to be reset. into a physical address.

In step 309, the low _- level processing layer LAL can know the actual corresponding classified block channel and a group of A sorted block (Bank), a sorted individual block, a sorted block page, and a sorted paged section. In other words, the physical address "X" can be divided into five segments (x ₁ , x ₂ , x ₃ , x ₄ , x ₅ ). The value of the physical address "x ₁ " in the first section represents that it is _physically corresponding to a classified block channel allocated in the flash memory _MF1 ; A group of classified blocks allocated in the memory _MF1 ; the numerical value of the third segment entity address "x ₃ " represents an entity corresponding to a classified individual block allocated in the flash memory _MF1 ; the fourth segment entity The numerical value of the address " _x4 " represents that it is physically corresponding to a classified block page allocated in the flash memory _MF1 ; the numerical value of the fifth physical address " _x5 " represents that it is physically corresponding to the flash memory _MF1 A sorted paged section is allocated. For example, if the physical address X is (1, 1, 1, 1, 1), it means that the physical storage unit physically available for data processing is located in the classified block channel CH of the flash memory _MF1 A group of sorted blocks _BK1 in ₁ A sorted block in separate block _BL1 A sorted page segment _ST1 in page _PG1 .

In addition, the hardware architecture information D _SPEC1 provides information on sorted block channels, group sorted blocks, sorted individual blocks, sorted block pages, and sorted page sections that can be planned in the flash memory _MF1 . For example, the hardware architecture information D _SPEC1 can be (10, 10, 10, 64, 4), which means that in the flash memory _MF1 , there are 10 classified block channels, and each classified block channel contains 10 groups of classified blocks, each group of classified blocks contains 10 classified individual blocks, each classified individual block contains 64 classified block pages, each classified block page contains 4 classified Paging section. In addition, the size of a classified paging segment is generally defined as 512 bytes, so it does not need to be provided in the hardware architecture information D _SPEC1 .

Therefore, the high-level translation layer HTL can convert the logical address "P" into the corresponding physical address "X" according to the hardware architecture information D _SPEC1 . As mentioned above, if the hardware architecture information D _SPEC1 is (10, 10, 10, 64, 4), for example, the logical address "X" is [123456], then the high-level translation layer HTL can divide [123456] by 25600 ( 10×10×64×4, indicating the size of a classified block channel), get 4 and the remainder 21056 (indicating that the physical address x ₁ is 4); then divide the remainder [21056] by 2560 (10×64×4, Indicates the size of a group of classified blocks), get 8 and remainder 576 (representing physical address x ₂ is 8); then divide the remainder [576] by 256 (64×4, representing the size of a classified individual block) , get 2 and remainder 64 (meaning that physical address x ₃ is 2); then divide the remainder [64] by 4 (4, representing the size of a classified block page), get 16 and remainder 0 (representing physical address x ₄ is 4 and physical address x ₅ is remainder 0). Simply put, when the logical address "P" is [123456], the physical address X translated by the high-level translation layer HTL according to the hardware architecture information D _SPEC1 is (4, 8, 2, 16, 0), which is expressed as 4th sorted block channel CH ₄ in flash memory M _F1 8th group sorted block BK ₈ 2nd sorted individual block BL ₂ 16th sorted block page PG The 0th sorted paged segment ST ₀ in ₁₆ .

However, in the flash memory, a classified block page with stored data cannot be written into. More specifically, if data is to be written into a classified block page that stores data, the classified individual block to which the classified block page belongs must first be erased. Each action of erasing data is based on a "classified separate block" as a unit. That is to say, at least one classified separate block must be erased each time the data is erased, and it is impossible to erase only one classified block page or one byte. Therefore, in order to speed up the data processing action performed by the host H on the flash memory _MF1 , a look-up table (Look Up Table, LUT) T _B will be set in the high-level translation layer HTL to select the corresponding A physical storage unit that does not store data in a classified separate block of a logical address is used for data processing. More specifically, when the above-mentioned high-level translation layer HTL translates the logical address "P" into the physical address "X", the translated physical address x ₃ does not directly correspond to a single classified individual block, Instead, it corresponds to two different classified individual blocks, and then selects one of them according to the reserved information D _SP provided by the flash memory _MF1 to provide a classified individual block for data processing. The reserved information D _SP is used to provide whether the physical storage unit to be processed has stored data, so as to facilitate the high-level translation layer HTL to select a physical storage unit that does not store data. How this works is explained in more detail below.

Please refer to Figure 4. FIG. 4 is a schematic diagram illustrating that the high-level translation layer HTL finds the actual physical storage unit for data processing according to the logical address, reserved information, and look-up table. Similarly, taking the logical address "P" as [123456] as an example, it can be seen that the physical address x ₃ is "2". Therefore, it can be found from the second column in the look-up table _TB that the classified individual blocks corresponding to the physical address x ₃ are classified individual blocks BL ₅ and BL ₁₃ . In fact, the physical storage unit to be processed is located in the 0th sorted page segment in the 4th sorted block page. It can be seen from the reserved information D _SP that the fourth classified block page in the classified individual block BL ₅ has stored data and the fourth classified block page in the classified individual block BL ₁₃ has not. Storing data. Therefore, the high-level translation layer HTL selects the classified individual block BL ₁₃ as the physical storage unit for actually performing data processing. More specifically, after the logical address [123456] is processed by the high-level translation layer HTL, it will correspond to the physical address (4, 8, "13", 16, 0) instead of the original physical address (4, 8, "2", 16, 0), nor (4, 8, "5", 16, 0). In other words, actually the physical storage unit found through the high-level translation layer HTL is located in the 8th group of classified blocks BK ₈ in the 4th classified block channel CH ₄ in the flash memory _MF1 The 0th sorted page sector ST ₀ in the 16th sorted block page PG ₁₆ in the 13th sorted individual block BL ₁₃ .

In step 308, the data processing flow DPS is used to determine the first physical address (x ₁ ), the second physical address (x ₂ ), and the third physical address of the physical address "X" obtained by the low-level processing layer LAL. (x ₃ ), the fourth physical address (x ₄ ), and the fifth physical address (x ₅ ).

Please refer to Figure 5. FIG. 5 is a flowchart illustrating a first embodiment of the data processing procedure DPS of the present invention. The steps are as follows:

Step 501: Make the low-level processing layer LAL obtain the second physical address (x ₂ ), know that in the flash memory _MF1 , there is a group of corresponding classified blocks, and the data can be processed;

Step 502: After obtaining the second segment physical address, obtain the third segment physical address (x ₃ ), know that there is a corresponding classified separate block in the flash memory _MF1 , and the data can be processed ;

Step 503: After obtaining the third segment physical address, obtain the fourth segment physical address (x ₄ ), know that in the flash memory _MF1 , there is a corresponding classified block page, and the data can be processed ;

Step 504: After obtaining the fourth segment physical address, obtain the fifth segment physical address (x ₅ ), know that there is a corresponding classified paging segment in the flash memory _MF1 , and the data can be processed ;

Step 505: After obtaining the fifth segment physical address, obtain the first segment physical address (x ₁ ), and finally know that there is a corresponding classified block channel in the flash memory _MF1 , and the data can be processed action.

Please refer to Figure 6. FIG. 6 is a flowchart illustrating a second embodiment of the data processing procedure DPS of the present invention. The steps are as follows:

Step 601: Make the low-level processing layer LAL obtain the first physical address (x ₁ ), know that there is a corresponding classified block channel in the flash memory _MF1 , and perform data processing;

Step 602: After obtaining the first physical address, obtain the third physical address (x ₃ ), and know that there is a corresponding classified separate block in the flash memory _MF1 , and the data can be processed ;

Step 603: After obtaining the third segment physical address, obtain the fourth segment physical address (x ₄ ), know that there is a corresponding classified block page in the flash memory _MF1 , and the data can be processed ;

Step 604: After obtaining the fourth segment physical address, obtain the fifth segment physical address (x ₅ ), know that there is a corresponding classified paging segment in the flash memory _MF1 , and the data can be processed ;

Step 605: After obtaining the fifth segment physical address, obtain the second segment physical address (x ₂ ), and finally know that there is a group of corresponding classified blocks in the flash memory _MF1 , and the data can be processed action.

Please refer to Figure 7. FIG. 7 is a flowchart illustrating a third embodiment of the data processing procedure DPS of the present invention. The steps are as follows:

Step 701: Make the low-level processing layer LAL obtain the third physical address (x ₃ ), know that in the flash memory _MF1 , there is a corresponding classified individual block, and the data can be processed;

Step 702: After obtaining the third segment physical address, obtain the second segment physical address (x ₂ ), know that there is a group of corresponding classified blocks in the flash memory _MF1 , and the data can be processed ;

Step 703: After obtaining the second segment physical address, obtain the fourth segment physical address (x ₄ ), know that there is a corresponding classified block page in the flash memory _MF1 , and the data can be processed ;

Step 704: After obtaining the fourth segment physical address, obtain the fifth segment physical address (x ₅ ), know that there is a corresponding classified paging segment in the flash memory _MF1 , and the data can be processed ;

Step 705: After obtaining the fifth segment physical address, obtain the first segment physical address (x ₁ ), and finally learn that there is a group of corresponding classified block channels in the flash memory _MF1 , and the data can be processed Handle actions.

In the above three embodiments of the data processing flow DPS, the fifth segment physical address is not necessary, which means that the low-level processing layer LAL does not necessarily need to perform data processing actions in units of classified paging segments. In other words, if the physical address received by the low-level processing layer LAL is only addressed to a classified block page, then the low-level processing layer LAL performs data processing in units of a classified block page; The physical address received by the low-level processing layer LAL is addressed to the classified paging segment, and then the low-level processing layer LAL can perform data processing in units of a classified paging segment. In addition, the physical address x ₃ is the high-level translation layer HTL, the physical address finally obtained according to the logical address "P", the lookup table _TB and the reserved information D _SP (as shown in the example in FIG. 4 ).

Please refer to Figure 8. FIG. 8 is a schematic diagram of a flash memory device 800 using hierarchical data processing according to the present invention. As shown in FIG. 8 , the flash memory device 800 includes a command and logical address conversion circuit 810 , an execution command and physical address addressing circuit 820 , and a flash memory _MF . The flash memory _MF includes a plurality of classified individual blocks BL ₁₁ ˜BL _MN .

The command and logical address conversion circuit 810 is located in the high-level translation layer HTL; the execution command and physical address addressing circuit 820 is located in the low-level processing layer LAL. The command and logical address translation circuit 810 also includes a logic judgment circuit 811 . In FIG. 8 , the operating principles of the host H, the high-level translation layer HTL, the low-level processing layer LAL, and the flash memory _MF are as described above, and will not be repeated here.

The command and logical address conversion circuit 810 is used to perform the following actions:

1. Make the high-level translation layer HTL receive the logical address "P" sent by the host H, and perform a data processing operation in the flash memory _MF accordingly;

2. Instruct the low-level processing layer LAL to obtain the hardware architecture information D _SPEC belonging to the flash memory _MF to transmit to the high-level translation layer HTL;

3. Let the high-level translation layer HTL set a group of physical storage units corresponding to the logical address "P" in the plurality of classified individual blocks according to the hardware architecture information D _SPEC , and find out the physical storage unit corresponding to the logical address "P" in the group. Among the physical storage units of the address, there is a physical storage unit available for data processing, and a data processing flow is determined to convert the logical address into a physical address corresponding to the physical storage unit available for data processing.

The execution command and physical address addressing circuit 820 is used to make the low-level processing layer LAL perform data processing operations in the physical storage unit available for data processing operations according to the physical address "X" transmitted by the high-level translation layer HTL.

The logic judgment circuit 811 is used to perform the following actions:

1. Make the high-level translation layer HTL issue a command (CMD ₁ or CMD ₂ ) to instruct the low-level processing layer LAL to obtain one of the hardware architecture information D _SPEC and the reserved information D _SP ;

2. Make the low-level processing layer LAL read one of the hardware structure information D _SPEC and the reserved information D _SP of the flash memory _MF according to the issued command, and send it back to the high-level translation layer HTL;

3. Make the high-level translation layer HTL determine the data processing flow according to the hardware architecture information D _SPEC and the reserved information D _SP , so as to convert the received logical address "P" into the corresponding physical address "X".

In summary, the present invention separates the flash memory translation layer into a high-level translation layer and a low-level processing layer, which can solve the problem of the entire flash memory when the original flash memory is replaced with another new type of flash memory. The memory translation layer needs to be redesigned, and through the low-level processing layer provided by the present invention, it is possible to use the corresponding control method according to the physical address provided by the high-level translation layer for various flash memories, The action of data processing is directly performed on the corresponding storage unit, so that greater convenience can be provided to the user.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (39)

1. A method for hierarchically layered data processing applied to a flash memory, comprising: passing a logical address to a high-level translation layer to request a data processing action in the flash memory; Obtaining a hardware architecture information belonging to the flash memory from a low-level processing layer to transmit the hardware architecture information to the high-level translation layer; Setting a group of physical storage units corresponding to the logical address in the flash memory according to the hardware architecture information by the high-level translation layer; The high-level translation layer finds, according to the hardware architecture information, a physical storage unit available for data processing among the group of physical storage units corresponding to the logical address; The high-level translation layer determines a data processing flow according to the hardware architecture information, so as to convert the logical address into a physical address corresponding to the physical storage unit available for data processing; and The low-level processing layer performs the data processing operation in the physical storage unit available for data processing according to the physical address converted by the high-level translation layer; Wherein, the high-level translation layer is used to enable a client application program and a file system to perform data processing in the flash memory, and is responsible for collecting relevant information of the usage status of the flash memory to manage the flash memory, and , the low-level processing layer obtains a group of classified blocks according to a first segment of address data in the physical address, obtains a classified individual block according to a second segment of address data in the physical address, and according to the A classified block page is obtained from a third segment of address data in the physical address, and a classified block channel is obtained from a fourth segment of address data in the physical address. the 2. The method according to claim 1, wherein obtaining a hardware architecture information belonging to the flash memory by a low-level processing layer to transmit the hardware architecture information to the high-level translation layer comprises: issuing a first command from the high-level translation layer to instruct the low-level processing layer to obtain the hardware architecture information; and The low-level processing layer reads the hardware architecture information of the flash memory according to the first command and sends it back to the high-level translation layer. the 3. The method according to claim 2, further comprising: issuing a second command from the high-level translation layer to instruct the low-level processing layer to obtain a reserved message; and The low-level processing layer reads the reserved information of the flash memory according to the second command to return to the high-level translation layer, and Wherein the high-level translation layer determines a data processing flow according to the hardware architecture information, so as to convert the logical address into a physical address corresponding to the physical storage unit available for data processing, including: The high-level translation layer determines the data processing flow according to the hardware architecture information and the reserved information, so as to convert it into the physical address. the 4. The method of claim 1, wherein the high-level translation layer is used to isolate requests sent by the client application and the file system so that the requests cannot directly enter the low-level processing layer. the 5. The method as claimed in claim 1, wherein the low-level processing layer is interposed between the high-level translation layer and the flash memory, and is used to execute commands sent by the high-level translation layer, and configure the hardware Information and a retained information retrieved from the flash memory are passed back to the HTL. the 6. The method as claimed in claim 1, wherein the low-level processing layer is used to execute the command sent by the high-level translation layer, isolating the command sent by the high-level translation layer so that the command cannot directly enter the flash memory , and return the hardware architecture information and a reserved information obtained from the flash memory to the high-level translation layer. the 7. The method as claimed in claim 1, wherein when a flash memory of another type replaces the flash memory, a low-level processing layer of another type is provided to replace the low-level processing layer, and the other type The low-level processing layer obtains another type of hardware architecture information belonging to the other type of flash memory to transmit the other type of hardware architecture information to the high-level translation layer. the 8. The method as claimed in claim 1, wherein the hardware architecture information provides the group of classified blocks, the classified individual blocks, the classified block paging and the classified blocks in the flash memory channel information. the 9. The method as claimed in claim 8, wherein the data processing flow determines that the low-level processing layer obtains the first segment address data, the second segment address data, the third segment address data and the fourth segment address data order. the 10. The method according to claim 9, wherein the data processing flow comprises: Make the low-level processing layer obtain the first address data, know that in the flash memory, there is the group of classified blocks, and the data can be processed; After obtaining the first segment address data, obtain the second segment address data, know that in the flash memory, there is the classified separate block, and the data can be processed; After obtaining the second segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; and After obtaining the third segment of address data, the fourth segment of address data is obtained, and finally it is known that there are classified block channels in the flash memory, and the data can be processed. the 11. The method according to claim 9, wherein the data processing flow comprises: Make the low-level processing layer obtain the fourth segment address data, know that the classified block channel exists in the flash memory, and process the data; After obtaining the fourth segment address data, obtain the second segment address data, know that in the flash memory, there is the classified separate block, and the data can be processed; After obtaining the second segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; and After obtaining the third segment of address data, the first segment of address data is obtained, and finally it is known that the group of classified blocks exists in the flash memory, and the data can be processed. the 12. The method according to claim 9, wherein the data processing flow comprises: Make the low-level processing layer obtain the second segment address data, know that the classified separate block exists in the flash memory, and process the data; After obtaining the second segment address data, obtain the first segment address data, know that in the flash memory, there is the group of classified blocks, and the data can be processed; After obtaining the first segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; and After obtaining the third segment of address data, the fourth segment of address data is obtained, and finally it is known that there are classified block channels in the flash memory, and the data can be processed. the 13. The method of claim 1, wherein the low-level processing layer is a flash architecture processing layer. the 14. A method for hierarchical and layered data processing applied to a flash memory, comprising: passing a logical address to a high-level translation layer to request a data processing action in the flash memory; Obtaining a hardware architecture information belonging to the flash memory from a flash architecture processing layer to transmit the hardware architecture information to the high-level translation layer; Setting a group of physical storage units corresponding to the logical address in the flash memory according to the hardware architecture information by the high-level translation layer; The high-level translation layer finds, according to the hardware architecture information, a physical storage unit available for data processing among the group of physical storage units corresponding to the logical address; According to the hardware architecture information, the high-level translation layer determines a data processing flow to convert the logical address into a physical address corresponding to the physical storage unit available for data processing; and The flash architecture processing layer performs the data processing action in the physical storage unit available for data processing action according to the physical address converted by the high-level translation layer; Wherein, the high-level translation layer is used to enable a client application program and a file system to perform data processing in the flash memory, and is responsible for collecting relevant information of the usage status of the flash memory to manage the flash memory, and , the flash architecture processing layer obtains a group of classified blocks according to a first segment address data in the physical address, and obtains a classified individual block according to a second segment address data in the physical address, according to According to a third section of address data in the physical address, a classified block page is obtained, and a classified paging section is obtained according to a fourth section of address data in the physical address, and a classified paging section is obtained according to a fifth section of the physical address. The segment address data learns a sorted block channel. the 15. The method of claim 14, wherein obtaining a hardware architecture information belonging to the flash memory by a flash architecture processing layer to transmit the hardware architecture information to the high-level translation layer comprises: issuing a first command from the high-level translation layer to instruct the flash architecture processing layer to obtain the hardware architecture information; and The flash architecture processing layer reads the hardware architecture information of the flash memory according to the first command and sends it back to the high-level translation layer. the 16. The method as claimed in claim 15, further comprising: issuing a second command from the high-level translation layer to instruct the flash architecture processing layer to obtain a reserved message; and The flash architecture processing layer reads the reserved information of the flash memory according to the second command to send back to the high-order translation layer, and Wherein, according to the hardware architecture information, the high-level translation layer determines a data processing flow to convert the logical address into a physical address corresponding to the physical storage unit available for data processing, including: The high-level translation layer determines the data processing flow to be converted into the physical address according to the hardware architecture information and the reserved information. the 17. The method of claim 14, wherein the high-level translation layer is used to isolate requests sent by the client application and the file system so that the requests cannot directly enter the flash architecture processing layer. the 18. The method as claimed in claim 14, wherein the flash architecture processing layer is interposed between the high-level translation layer and the flash memory, and is used to execute commands sent by the high-level translation layer and transfer the hardware Architecture information and a reserved information obtained from the flash memory are passed back to the HTL. the 19. The method of claim 14, wherein the flash architecture processing layer is used to execute commands sent by the high-level translation layer, isolating the commands sent by the high-level translation layer so that the commands cannot directly enter the flash memory, and return the hardware architecture information and a reserved information obtained from the flash memory to the high-level translation layer. the 20. The method as claimed in claim 14, wherein when another type of flash memory replaces the flash memory, another type of flash architecture processing layer is provided to replace the flash architecture processing layer, and the other type A type of flash architecture processing layer obtains another type of hardware architecture information belonging to the other type of flash memory to transmit the other type of hardware architecture information to the high-level translation layer. the 21. The method as claimed in claim 14, wherein the hardware architecture information provides that the group of classified blocks, the classified individual blocks, the classified block paging, and the classified paging area can be planned in the flash memory. segment and channel information for this classified block. the 22. The method according to claim 21, wherein the data processing flow determines that the flash architecture processing layer obtains the first segment address data, the second segment address data, the third segment address data, and the fourth segment address data and the sequence of the fifth segment address data. the 23. The method according to claim 22, wherein the data processing flow comprises: Make the flash architecture processing layer obtain the first segment of address data, know that in the flash memory, there is the group of classified blocks, and the data can be processed; After obtaining the first segment address data, obtain the second segment address data, know that in the flash memory, there is the classified separate block, and the data can be processed; After obtaining the second segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; After obtaining the third segment address data, obtain the fourth segment address data, know that in the flash memory, there is the classified paging segment, and the data can be processed; and After obtaining the fourth segment of address data, the fifth segment of address data is obtained, and finally it is known that there are classified block channels in the flash memory, and the data can be processed. the 24. The method according to claim 22, wherein the data processing flow comprises: Make the flash architecture processing layer obtain the fifth segment address data, know that in the flash memory, there is a classified block channel, and the data can be processed; After obtaining the fifth segment address data, obtain the second segment address data, know that in the flash memory, there is the classified separate block, and the data can be processed; After obtaining the second segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; After obtaining the third segment address data, obtain the fourth segment address data, know that in the flash memory, there is the classified paging segment, and the data can be processed; and After obtaining the fourth segment address data, obtain the first segment address data, and finally know that the group of classified blocks exists in the flash memory, and the data can be processed. the 25. The method according to claim 22, wherein the data processing flow comprises: Make the flash architecture processing layer obtain the second segment of address data, know that in the flash memory, there is the classified separate block, and the data can be processed; After obtaining the second segment address data, obtain the first segment address data, know that in the flash memory, there is the group of classified blocks, and the data can be processed; After obtaining the first segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; After obtaining the third segment address data, obtain the fourth segment address data, know that in the flash memory, there is the classified paging segment, and the data can be processed; and After obtaining the fourth segment of address data, the fifth segment of address data is obtained, and finally it is known that there are classified block channels in the flash memory, and the data can be processed. the 26. The method of claim 14, wherein the high-level translation layer is a flash architecture translation layer. the 27. A flash memory device using hierarchical and layered data processing, comprising: A flash memory consisting of a plurality of classified individual blocks; A command and logical address conversion circuit is used to make a high-level translation layer receive a logical address and a request to perform a data processing operation in the flash memory, and order a low-level processing layer to obtain a data belonging to the flash memory hardware architecture information to transmit the hardware architecture information to the high-level translation layer, so that the high-level translation layer sets a group of entities corresponding to the logical address in the plurality of classified individual blocks according to the hardware architecture information The storage unit finds a physical storage unit available for data processing in the group of physical storage units corresponding to the logical address, and determines a data processing flow to convert the logical address into data corresponding to the available data a physical address of the physical storage location where the action is processed; and An execution command and physical address addressing circuit, used to make the low-level processing layer perform the data processing operation in the physical storage unit available for data processing according to the physical address converted by the high-level translation layer ; Wherein, the high-level translation layer is used to enable a client application program and a file system to perform data processing in the flash memory, and is responsible for collecting relevant information of the usage status of the flash memory to manage the flash memory, and , the low-level processing layer obtains a group of classified blocks according to a first segment of address data in the physical address, obtains a classified individual block according to a second segment of address data in the physical address, and according to the A classified block page is obtained from a third segment of address data in the physical address, and a classified block channel is obtained from a fourth segment of address data in the physical address. the 28. The device as claimed in claim 27, wherein the command and logical address translation circuit further comprises: A logic judgment circuit, used to make the high-level translation layer issue a command to instruct the low-level processing layer to obtain one of the hardware structure information and a reserved information, so that the low-level processing layer reads the flash memory according to the command One of the hardware architecture information and the reserved information of the memory is sent back to the high-level translation layer and the high-level translation layer determines the data processing flow for conversion into the entity according to the hardware architecture information and the reserved information address. the 29. The device of claim 27, wherein the high-level translation layer is used to isolate requests sent by the client application and the file system so that the requests cannot directly enter the low-level processing layer. the 30. The device as claimed in claim 27, wherein the low-level processing layer is between the high-level translation layer and the flash memory, and is used to execute commands sent by the high-level translation layer, and configure the hardware Information and a retained information retrieved from the flash memory are passed back to the HTL. the 31. The device according to claim 27, wherein the low-level processing layer is used to execute commands sent by the high-level translation layer, isolating the commands sent by the high-level translation layer so that the commands cannot directly enter the flash memory , and return the hardware architecture information and a reserved information obtained from the flash memory to the high-level translation layer. the 32. The device as claimed in claim 27, wherein when a flash memory of another type replaces the flash memory, a low-level processing layer of another type is provided to replace the low-level processing layer, and the other type The low-level processing layer obtains another type of hardware architecture information belonging to the other type of flash memory to transmit the other type of hardware architecture information to the high-level translation layer. the 33. The device as claimed in claim 27, wherein the hardware architecture information provides the group of classified blocks, the classified individual blocks, the classified block paging and the classified blocks that can be planned in the flash memory channel information. the 34. The device as claimed in claim 33, wherein the data processing flow determines how the low-level processing layer obtains the first segment address data, the second segment address data, the third segment address data, and the fourth segment address data order. the 35. The device of claim 34, wherein the data processing flow comprises: Make the low-level processing layer obtain the first piece of address data, know that the group of classified blocks exists in the flash memory, and process the data; After obtaining the first segment address data, obtain the second segment address data, know that in the flash memory, there is the classified separate block, and the data can be processed; After obtaining the second segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; and After obtaining the third segment of address data, the fourth segment of address data is obtained, and finally it is known that there are classified block channels in the flash memory, and the data can be processed. the 36. The device of claim 34, wherein the data processing flow comprises: Make the low-level processing layer obtain the fourth segment address data, know that the classified block channel exists in the flash memory, and process the data; After obtaining the fourth segment address data, obtain the second segment address data, know that in the flash memory, there is the classified separate block, and the data can be processed; After obtaining the second segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; and After obtaining the third segment of address data, the first segment of address data is obtained, and finally it is known that the group of classified blocks exists in the flash memory, and the data can be processed. the 37. The device of claim 34, wherein the data processing flow comprises: Make the low-level processing layer obtain the second segment address data, know that the classified separate block exists in the flash memory, and process the data; After obtaining the second segment address data, obtain the first segment address data, know that in the flash memory, there is the group of classified blocks, and the data can be processed; After obtaining the first segment address data, obtain the third segment address data, know that in the flash memory, there is the classified block page, and the data can be processed; and After obtaining the third segment of address data, the fourth segment of address data is obtained, and finally it is known that there are classified block channels in the flash memory, and the data can be processed. the 38. The device of claim 27, wherein the low-level processing layer is a flash architecture processing layer. the 39. The apparatus of claim 27, wherein the high-level translation layer is a flash architecture translation layer. the

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