CN101783590A - Boosting clock circuit and charge pump provided with the same - Google Patents
Boosting clock circuit and charge pump provided with the same Download PDFInfo
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- CN101783590A CN101783590A CN 201010121431 CN201010121431A CN101783590A CN 101783590 A CN101783590 A CN 101783590A CN 201010121431 CN201010121431 CN 201010121431 CN 201010121431 A CN201010121431 A CN 201010121431A CN 101783590 A CN101783590 A CN 101783590A
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Abstract
The invention discloses a boosting clock circuit which comprises at least one single-stage boosting clock circuits which are cascaded and is characterized in that at least one single-stage boosting clock circuit of the boosting clock circuit is connected with a comparison and selection circuit; and the comparison and selection circuit adjusts and controls the capacitance of the single-stage boosting clock circuit connected therewith according to the supply voltage of the single-stage boosting clock circuit. A charge pump circuit comprises a charge pump and above boosting clock circuit, wherein the boosting clock circuit charges the charge pump. The boosting clock circuit and the charge pump circuit utilizes the comparison and selection circuit to adjust the charging capacitances necessary for all the corresponding single-stage boosting clock circuits according to the changes of the supply voltages of the single-stage boosting clock signals so as to limit the amplification factor of the boosting clock circuit and to ensure the relative stability of the total accumulated charges of the whole boosting clock circuit. The boosting clock circuit and the charge pump circuit overcome the defect that the conventional boosting clock circuit and the charge pump circuit are easy to have big discharge current.
Description
Technical field
The invention belongs to the charge pumping technique field, be specifically related to a kind of boost clock circuit and with the charge pump of this boost clock circuit.
Background technology
Charge pump is called the switched capacitor voltage changer again, be a kind of utilization " fast " (flying) or " pumping " electric capacity come DC-to-DC (DC-DC) converter of energy storage. charge pump can make input voltage raise or reduce, and also can be used to produce negative voltage.Traditional charge pump makes input voltage with certain factor (0.5,2 or 3) multiplication or reduction by the charging and the discharge of control flying capacitor, obtains needed output voltage.
At present, Chang Yong charge pump all has boost clock circuit.After boosting by boost clock circuit, the clock signal C K of input and reverse clock signal C KB be output as clock signal C KO and reverse clock signal C KOB; The high-low level difference VH of corresponding clock signals CK and reverse clock signal C KB is increased to the clock signal C KO of output and the high-low level difference VOH of reverse clock signal C KOB.This method can make things convenient for, improve effectively the efficient of charge pump, particularly for the lower charge pump of operating voltage.
Figure 1A is the charge pump circuit of band boost clock circuit in a kind of prior art.The input voltage vin of this charge pump (CHARGE PUMP) is generally VDD, output voltage V pump after boosting through boost clock circuit (CLOCK BOOSTCIRCUIT).Under the situation of not considering other factors, output voltage V pump is by the output voltage VO H decision of input voltage vin and boost clock circuit.Boost clock circuit is shown in Figure 1B, and it is formed by a series of single-stage boost clock circuit (CK_BST) cascade.The high-low level difference of the clock signal C K of input and reverse clock signal C KB is operating voltage VH.The high-low level difference VOH of the clock signal C KO of output and reverse clock signal C KOB is higher.CKO and CKOB are used for controlling the discharging and recharging of flying capacitance of charge pump.
Fig. 2 is a kind of common single-stage boost clock circuit in the prior art.As can be seen from the figure, the supply power voltage of this single-stage boost clock circuit (CK_BST) is VDD '.When CK was become low level (ground connection), CKB and become high level VH by low level (ground connection) by high level VH, NMOS pipe m5 closed, PMOS pipe m3 conducting; NMOS pipe m6 conducting, PMOS pipe m4 close; NMOS pipe m1 conducting.The voltage that electric capacity c1 begins to be precharged to two ends is VDD ', because the electric charge at electric capacity two ends can not suddenly change, so its both end voltage value is constant, so the voltage of node A is lifted to a higher voltage VH+VDD ' by electric capacity c1.Because the m3 conducting, so the output voltage of OUTB end is VOUTB=VH+VDD '.Node B is charged to voltage VDD ' in advance by m2 simultaneously, and output OUT is switched to ground (ground) by m6.
When CK was become high level VH, CKB and become low level (ground connection) by high level VH by low level (ground connection), NMOS pipe m5 conducting, PMOS pipe m3 closed; NMOS pipe m6 closes, PMOS pipe m4 conducting; NMOS pipe m2 conducting.The voltage that electric capacity c2 begins to be precharged to two ends is VDD ', because the electric charge at electric capacity two ends can not suddenly change, so its both end voltage value is constant, so the voltage of Node B is lifted to a higher voltage VH+VDD ' by electric capacity c2.Because the m4 conducting, so the output voltage of OUT end is VOUT=VH+VDD '.Node A is charged to voltage VDD ' in advance by m1 simultaneously, and output OUTB is switched to ground (ground) by m5.
In sum, become VOH=VH+VDD ' behind the high-low level difference VH of CK and the CKB process single-stage boost clock circuit.So if form boost clock circuit by the cascade of N level single-stage boost clock circuit, the supply power voltage of each grade single-stage boost clock circuit can be inequality, is respectively VDD 1～VDD N.The CKO of the clock signal of the final output of this boost clock circuit and the oppositely high level point difference VOH=VH+VDD 1+VDD 2+ of clock signal C KOB so ... + VDD N.
Yet, the shortcoming of this structure is that each single-stage boost clock circuit supply power voltage VDD 1～VDD N is when low, output voltage V pump for the charge pump that is met requirement, the progression N of boost clock circuit just needs to increase, and that is to say needs more single-stage boost clock circuit (CK_BST) cascade.In the side circuit, voltage VDD 1～VDD N is not invariable.An amplitude of variation is arranged.In order to guarantee the electric charge pump performance, during the progression of design boost clock circuit, be as the criterion with the minimum voltage of voltage VDD 1～VDD N.So when voltage VDD 1～VDD N all when the highest, because the progression N of boost clock circuit is very big, the clock signal high-low level difference of the output of each grade single-stage boost clock circuit all has increase, the high-low level difference of the clock signal C KO of output and reverse clock signal C KOB will be very big after boosting.Cause big discharging current can bring many bad problems thus, as snap back (snapback) or latch-up.Generally, each single-stage boost clock circuit supply power voltage VDD 1～VDDN gets same magnitude of voltage VDD ' (as shown in Figure 4), and there is this problem too in a shared voltage source.
Summary of the invention
The technical issues that need to address of the present invention are lower and when fluctuation is arranged at supply power voltage, and traditional boost clock circuit multiplication factor is very big and immobilize, and can produce very big discharging current.The charge pump that has traditional boost clock circuit also has same problem.
For solving the problems of the technologies described above, general thought of the present invention is to adjust the size of the used charging capacitor of corresponding each single-stage boost clock circuit according to the situation of change of the supply power voltage of each single-stage boost clock circuit, with the multiplication factor of restriction boost clock circuit, guarantee the clock signal of whole boost clock circuit output and oppositely the high-low level difference and the total stored charge of clock signal is relatively stable.
In order to solve the problems of the technologies described above, the invention provides a kind of boost clock circuit, form by one-level single-stage boost clock circuit cascade at least, have at least one-level single-stage boost clock circuit to link to each other with compare selection circuit in the described boost clock circuit, described compare selection circuit is according to the capacitance size of the described single-stage boost clock circuit that is attached thereto of supply power voltage regulation and control of the described single-stage boost clock circuit that is attached thereto.
Optionally, the supply power voltage of described single-stage boost clock circuit is identical with the input voltage of the compare selection circuit that is attached thereto.
Optionally, described single-stage boost clock circuit comprises variable capacitance, and the compare selection circuit that the size of described variable capacitance is subjected to link to each other with described single-stage boost clock circuit is regulated and control.
Optionally, described single-stage boost clock circuit comprises the charging capacitor of one or more parallel connections.
Optionally, described compare selection circuit comprises the one or more series resistances with the input voltage dividing potential drop, the partial pressure value of described input voltage compares through comparator with a reference voltage respectively, and the comparative result of a described comparator is controlled the operating state of at least one charging capacitor in the described single-stage boost clock circuit.
Optionally, described comparator links to each other with described charging capacitor by switch, and the on off state of described switch is determined by described comparative result.
Optionally, a described comparator is controlled the operating state of a described charging capacitor by a described switch.
Optionally, described comparative result is the partial pressure value of described input voltage when being less than or equal to described reference voltage, corresponding switch conduction.
Optionally, each single-stage boost clock circuit links to each other with a compare selection circuit.
Optionally, the supply power voltage of described each single-stage boost clock circuit is identical.
Optionally, the interior charging capacitor size in parallel of described each single-stage boost clock circuit is identical.
Optionally, the charging capacitor number of parallel connection is identical in each single-stage boost clock circuit.
Optionally, described each single-stage boost clock circuit structure is identical.
Optionally, the compare selection circuit that links to each other of described and each single-stage boost clock circuit is identical.
Optionally, described each single-stage boost clock circuit can a shared compare selection circuit.
For solving the problems of the technologies described above, the present invention also provides a kind of charge pump circuit, comprises charge pump and above-mentioned boost clock circuit, and described boost clock circuit charges to described charge pump.
Optionally, each single-stage boost clock circuit links to each other with a compare selection circuit.
Optionally, the supply power voltage of described each single-stage boost clock circuit is identical.
Optionally, the input voltage of described charge pump is identical with the supply power voltage of described each single-stage boost clock circuit.
Optionally, the interior charging capacitor size in parallel of described each single-stage boost clock circuit is identical.
Optionally, the charging capacitor number of parallel connection is identical in each single-stage boost clock circuit.
Optionally, described each single-stage boost clock circuit structure is identical.
Optionally, the compare selection circuit that links to each other of described and each single-stage boost clock circuit is identical.
Optionally, described each single-stage boost clock circuit can a shared compare selection circuit.
Compare with charge pump circuit with traditional boost clock circuit, advantage that boost clock circuit provided by the invention and charge pump circuit have and beneficial effect are the sizes of adjusting the used charging capacitor of corresponding each single-stage boost clock circuit with compare selection circuit according to the situation of change of the supply power voltage of single-stage boosting timeclock signal, with the multiplication factor of restriction boost clock circuit, guarantee the clock signal of whole boost clock circuit output and oppositely the high-low level difference and the total stored charge of clock signal is relatively stable.Overcome traditional boost clock circuit and charge pump circuit and be easy to generate big discharging current, caused defective as problems such as snap back (snap back) or latch-ups.
Description of drawings
Figure 1A is the charge pump circuit structured flowchart of band boost clock circuit in the prior art;
Figure 1B is the boost clock circuit structured flowchart among Figure 1A;
Fig. 2 is a single-stage boost clock circuit structural representation of the prior art;
Fig. 3 is the structured flowchart that has the boosting timeclock of compare selection circuit provided by the invention;
Fig. 4 is a single-stage boost clock circuit provided by the invention;
Fig. 5 is the circuit diagram of single compare selection circuit provided by the invention;
Fig. 6 is the structured flowchart of the boosting timeclock of a shared compare selection circuit provided by the invention;
Fig. 7 is the charge pump circuit of band boost clock circuit provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
As shown in Figure 2, from the charging angle of electric charge to electric capacity, the electric capacity of each single-stage boost clock circuit is made as C, and charging voltage is VDD ', so the charging charge Q=C*VDD ' of single-stage boost clock circuit.The series connection of N level single-stage boost clock circuit; The electric capacity of each grade single-stage boost clock circuit can be different, is respectively C1～CN; The supply power voltage of each grade single-stage boost clock circuit also can be different, is respectively VDD 1～VDD N (as shown in Figure 3).The charge Q of so whole boost clock circuit accumulation '=Q1+Q2+ ... + QN=C1*VDD 1+C2*VDD 2+ ... + CN*VDD N.Reduce to cause charge Q ' too much adverse effect that produces, can reduce the capacitor C 1～CN of corresponding each single-stage boost clock circuit respectively according to the situation of change of voltage VDD 1～VDDN because of VDD 1～VDD N is excessive.Also can reduce the electric capacity of part single-stage boost clock circuit, just its effect is not as the former.When the supply power voltage of each single-stage boost clock circuit all is VDD ' time, only need reduce the capacitor C 1～CN of each single-stage boost clock circuit according to the situation of change of shared voltage VDD '.At this moment, Q '=Q1+Q2+ ... + QN=(C1+C2+ ... + CN) * VDD '.Generally, the electric capacity of each single-stage boost clock circuit equates, all is C, i.e. C1=C2=...=CN=C.
In sum, can detect the situation of change of voltage VDD 1～VDD N earlier respectively, change the size of adjusting corresponding each single-stage boost clock circuit electric capacity according to it then, with the multiplication factor of restriction boost clock circuit, the high-low level difference VOH of assurance clock signal C KO and reverse clock signal C KOB and total stored charge Q ' are relatively stable.As a kind of preferred mode, the electric capacity of single-stage boost clock circuit can be the charging capacitor of one or more parallel connections, and the number of the charging capacitor of the parallel connection by changing each single-stage boost clock circuit changes the size of single-stage boost clock circuit electric capacity.Each single-stage boost clock circuit is attached thereto with a compare selection circuit, controls the number of charging capacitor in parallel in this single-stage boost clock circuit.In addition, the electric capacity of single-stage boost clock circuit also can as the charging capacitor of one or more series connection, be not limited to the described mode of present embodiment for other variable capacitances that can adjust size.
Fig. 3 is exactly the structured flowchart that has an embodiment of boost clock circuit of compare selection circuit provided by the invention.As can be seen from Figure 3, boost clock circuit is formed by a single-stage boost clock circuit or a plurality of (N level) single-stage boost clock circuit CK_BST 1～CK_BST N cascade.The power supply of each single-stage boost clock circuit CK_BST 1～CK_BST N is VDD 1～VDD N.In one or more (among the figure for all) single-stage boost clock circuit each is equipped with a compare selection circuit respectively.This compare selection circuit can be controlled the size of the electric capacity of this single-stage boost clock circuit according to the variation of the supply power voltage of coupled single-stage boost clock circuit.Specifically, there is a fixing corresponding relation in the input voltage of each compare selection circuit with the supply power voltage of the corresponding single-stage boost clock circuit that links to each other.When the supply power voltage of single-stage boost clock circuit changes, corresponding variation also takes place in the input voltage of corresponding compare selection circuit, so compare selection circuit just can be controlled the size of the corresponding single-stage boost clock circuit electric capacity that links to each other with it according to this change in voltage.The input voltage of the compare selection circuit shown in Fig. 3 equates with the supply power voltage of the corresponding single-stage boost clock circuit that links to each other, but also can be by other fixed correspondence, as the input voltage of compare selection circuit is the multiple (2 times, 3 times etc.) of the supply power voltage of the corresponding single-stage boost clock circuit that links to each other, and it is described to be not limited to present embodiment.
The single-stage boost clock circuit that is adopted in the boost clock circuit of present embodiment as shown in Figure 4.As can be seen, the single-stage boost clock circuit of present embodiment only is to contain one or more charging capacitors in parallel with the difference of traditional single-stage boost clock circuit, and each charging capacitor links to each other with a switch SW among comparison diagram 4 and Fig. 2.Just can control the operating state of the electric capacity that links to each other with this switch SW by control switch SW, promptly whether contribute boosting.Charging capacitor size in parallel can be identical, also can be inequality.Preferably get the identical charging capacitor parallel connection of size.
Fig. 5 is the circuit diagram of single compare selection circuit provided by the invention.As can be seen from Figure 5, compare selection circuit carries out dividing potential drop with the resistance R 1～Rm of input voltage VDD ' by series connection, and the partial pressure value V1～Vm and the reference voltage VREF of each resistance correspondence compared by comparator.The m that an is obtained comparative result is respectively in order to m switch SW in control and the single-stage boost clock circuit that this compare selection circuit links to each other.Each switch SW is according to the switch of the comparative result decision self of the comparator that is attached thereto, and then whether the electric capacity that control links to each other with this switch SW contributes to boosting.Certainly, each comparative result also can be controlled the operating state of a plurality of shunt capacitances by one or more switches.Be used for the number of resistance of dividing potential drop and the size and the relativeness of each resistance, can select flexibly in conjunction with reference voltage VREF and actual needs.For example, input voltage VDD ' minimum value is 3V, and the single-stage boost clock circuit has 3 charging capacitors and 3 switches.Compare selection circuit has 3 resistance R 1=R2=R3=1 ohms, and pairing partial pressure value is respectively 1V, 2V, 3V.The setting reference voltage is 3V.When input voltage VDD ' was 3V, all dividing potential drops all were not less than reference voltage, 3 of the single-stage boost clock circuit switch opens so, and 3 charging capacitors all participate in charging, satisfy the requirement of whole boost clock circuit to stored charge.When input voltage VDD ' surpasses 3V, when for example being 3.6V, each partial pressure value is respectively 1.2V, 2.4V, 3.6V, having only preceding two partial pressure value so is less than reference voltage through the result of comparator comparison, the switch opens that links to each other with this comparator, corresponding electric capacity participates in charging; And the partial pressure value of 3.6V is closed with the switch that corresponding comparator links to each other greater than reference voltage, and corresponding electric capacity does not participate in charging.Therefore, after input voltage VDD ' increase, the charging capacitor number of single-stage boost clock circuit parallel connection becomes 2 by 3, thereby makes the capacitance size of single-stage boost clock circuit reduce.Can select suitable resistance R 1～Rm, the size and the number of charging capacitor according to the situation of change of input voltage VDD ' and the precision of circuit adjustment.
As previously described, each single-stage boost clock circuit can be adjusted the size of charging capacitor separately according to the size variation of supply power voltage separately by said method.The charge Q of whole boost clock circuit accumulation '=Q1+Q2+ ... + QN=C1*VDD 1+C2*VDD 2+ ... + CN*VDD N, the reducing of the increase of each single-stage boost clock circuit charging voltage VDD 1～VDD N and each single-stage boost clock circuit charging capacitors at different levels cancelled out each other, thus keep the charge Q of whole boost clock circuit accumulation ' relatively stable.In order to obtain effect preferably, the charge Q of feasible accumulation ' remain unchanged need be taken all factors into consideration the charging capacitor number of each single-stage boost clock circuit parallel connection, the number of divider resistance and the selection of relative size and reference voltage.
As a kind of preferred mode, each charging capacitor size in parallel in the single-stage boost clock circuit is identical.
Further, as a kind of preferred mode, charging capacitor number in parallel in each single-stage boost clock circuit is identical, so the capacitance size of each single-stage boost clock circuit is identical.
As a kind of preferred mode, each single-stage boost clock circuit structure is identical.Being boost clock circuit is formed by the single-stage boost clock circuit cascade of one or more levels repetition.
As a kind of preferred mode, the supply power voltage of each single-stage boost clock circuit is identical.
As a kind of preferred mode, the compare selection circuit that links to each other with each single-stage boost clock circuit is identical.
As a kind of preferred mode, each single-stage boost clock circuit supply power voltage is identical, is VDD ', can a shared compare selection circuit (as shown in Figure 6).Each comparator of the compare selection circuit that this is shared is controlled the on off state of a corresponding switch in each single-stage boost clock circuit (CK_BST) respectively.VDD ' and VIN have previously described fixing corresponding relation.
Fig. 7 is the above-mentioned charge pump circuit that has the boost clock circuit of compare selection circuit of application provided by the invention.As can be seen from the figure, the input voltage of charge pump (CHARGE PUMP) is Vin, and output voltage is Vpump, by the previously described boost clock circuit (CLOCK BOOST CIRCUIT) that has compare selection circuit it is charged.
As a kind of preferred mode, the input voltage of charge pump (CHARGE PUMP) is that Vin is identical with the charging voltage VDD ' of each single-stage boost clock circuit, and all the supply voltage VDD that provides of the system of getting economizes on resources so more.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (24)
1. boost clock circuit, form by one-level single-stage boost clock circuit cascade at least, it is characterized in that, have at least one-level single-stage boost clock circuit to link to each other with compare selection circuit in the described boost clock circuit, described compare selection circuit is according to the capacitance size of the described single-stage boost clock circuit that is attached thereto of supply power voltage regulation and control of the described single-stage boost clock circuit that is attached thereto.
2. boost clock circuit according to claim 1 is characterized in that, the supply power voltage of described single-stage boost clock circuit is identical with the input voltage of the compare selection circuit that is attached thereto.
3. boost clock circuit according to claim 1 is characterized in that the electric capacity of described single-stage boost clock circuit comprises variable capacitance, and the compare selection circuit that the size of described variable capacitance is subjected to link to each other with described single-stage boost clock circuit is regulated and control.
4. boost clock circuit according to claim 1 is characterized in that described single-stage boost clock circuit comprises the charging capacitor of one or more parallel connections.
5. boost clock circuit according to claim 4, it is characterized in that, described compare selection circuit comprises the one or more series resistances with the input voltage dividing potential drop, the partial pressure value of described input voltage compares through comparator with a reference voltage respectively, and the comparative result of a described comparator is controlled the operating state of at least one charging capacitor in the described single-stage boost clock circuit.
6. boost clock circuit according to claim 5 is characterized in that, described comparator links to each other with described charging capacitor by switch, and the on off state of described switch is determined by described comparative result.
7. boost clock circuit according to claim 6 is characterized in that, a described comparator is controlled the operating state of a described charging capacitor by a described switch.
8. boost clock circuit according to claim 6 is characterized in that, described comparative result is the partial pressure value of described input voltage when being less than or equal to described reference voltage, corresponding switch conduction.
9. according to a described boost clock circuit in the claim 1～8, it is characterized in that each single-stage boost clock circuit links to each other with a compare selection circuit.
10. according to a described boost clock circuit in the claim 1～8, it is characterized in that the supply power voltage of described each single-stage boost clock circuit is identical.
11. a described boost clock circuit according in the claim 1,4～8 is characterized in that, charging capacitor size in parallel in described each single-stage boost clock circuit is identical.
12. a described boost clock circuit according in the claim 11 is characterized in that, charging capacitor number in parallel in each single-stage boost clock circuit is identical.
13. a described boost clock circuit according in the claim 1～8 is characterized in that, described each single-stage boost clock circuit structure is identical.
14. a described boost clock circuit according in the claim 1～8 is characterized in that, the described compare selection circuit that links to each other with each single-stage boost clock circuit is identical.
15. a described boost clock circuit according in the claim 1～8 is characterized in that, the shared compare selection circuit of described each single-stage boost clock circuit.
16. a charge pump circuit comprises charge pump, it is characterized in that, described charge pump circuit also comprises a described boost clock circuit in the claim 1～8, and described boost clock circuit charges to described charge pump.
17. charge pump circuit according to claim 16 is characterized in that, each single-stage boost clock circuit links to each other with a compare selection circuit.
18. charge pump circuit according to claim 16 is characterized in that, the supply power voltage of described each single-stage boost clock circuit is identical.
19. charge pump circuit according to claim 18 is characterized in that, the input voltage of described charge pump is identical with the supply power voltage of described each single-stage boost clock circuit.
20. charge pump circuit according to claim 16 is characterized in that, charging capacitor size in parallel in described each single-stage boost clock circuit is identical.
21. charge pump circuit according to claim 16 is characterized in that, charging capacitor number in parallel in each single-stage boost clock circuit is identical.
22. charge pump circuit according to claim 16 is characterized in that, described each single-stage boost clock circuit structure is identical.
23. charge pump circuit according to claim 16 is characterized in that, the described compare selection circuit that links to each other with each single-stage boost clock circuit is identical.
24. charge pump circuit according to claim 16 is characterized in that, the shared compare selection circuit of described each single-stage boost clock circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101214315A CN101783590B (en) | 2010-03-10 | 2010-03-10 | Boosting clock circuit and charge pump provided with the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101214315A CN101783590B (en) | 2010-03-10 | 2010-03-10 | Boosting clock circuit and charge pump provided with the same |
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| CN101783590A true CN101783590A (en) | 2010-07-21 |
| CN101783590B CN101783590B (en) | 2012-08-29 |
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| CN2010101214315A Active CN101783590B (en) | 2010-03-10 | 2010-03-10 | Boosting clock circuit and charge pump provided with the same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386762A (en) * | 2010-09-01 | 2012-03-21 | 上海宏力半导体制造有限公司 | Boosting clock circuit and charge pump with same |
| CN103872904A (en) * | 2014-03-17 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Charge pump and storage |
| CN107453722A (en) * | 2017-06-12 | 2017-12-08 | 合肥市汤诚集成电路设计有限公司 | Charge pump is adaptively boosted F class power amplifiers |
| CN111917286A (en) * | 2019-05-10 | 2020-11-10 | 北京兆易创新科技股份有限公司 | Charge pump system |
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| JP2003339156A (en) * | 2002-05-20 | 2003-11-28 | Denso Corp | Boosting circuit |
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| US20080054991A1 (en) * | 2006-08-28 | 2008-03-06 | Kabushiki Kaisha Toshiba | Booster circuit and voltage supply circuit |
| US20090146750A1 (en) * | 2007-12-05 | 2009-06-11 | Mobius Microsystems, Inc. | Common Mode Controller for a Clock, Frequency Reference, and Other Reference Signal Generator |
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| JP2000060110A (en) * | 1998-08-11 | 2000-02-25 | Oki Electric Ind Co Ltd | Drive control circuit for charge pump circuit |
| JP2003339156A (en) * | 2002-05-20 | 2003-11-28 | Denso Corp | Boosting circuit |
| CN1731681A (en) * | 2005-08-12 | 2006-02-08 | 北京大学 | Double-loop frequency synthesizer and method for tuning coarse loop |
| US20080054991A1 (en) * | 2006-08-28 | 2008-03-06 | Kabushiki Kaisha Toshiba | Booster circuit and voltage supply circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386762A (en) * | 2010-09-01 | 2012-03-21 | 上海宏力半导体制造有限公司 | Boosting clock circuit and charge pump with same |
| CN102386762B (en) * | 2010-09-01 | 2014-03-05 | 上海宏力半导体制造有限公司 | Boosting clock circuit and charge pump with same |
| CN103872904A (en) * | 2014-03-17 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Charge pump and storage |
| CN103872904B (en) * | 2014-03-17 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Electric charge pump and memorizer |
| CN107453722A (en) * | 2017-06-12 | 2017-12-08 | 合肥市汤诚集成电路设计有限公司 | Charge pump is adaptively boosted F class power amplifiers |
| CN107453722B (en) * | 2017-06-12 | 2022-02-08 | 合肥市汤诚集成电路设计有限公司 | Self-adaptive boosting F-type power amplifier of charge pump |
| CN111917286A (en) * | 2019-05-10 | 2020-11-10 | 北京兆易创新科技股份有限公司 | Charge pump system |
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| Publication number | Publication date |
|---|---|
| CN101783590B (en) | 2012-08-29 |
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