CN101782847B - Data storage method and processor using same - Google Patents
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Abstract
The invention discloses a data storage method, which is applied to a processor with a pipelined processing unit. The pipelined processing unit comprises a plurality of levels which at least comprise a source capturing level and a data writing level. The method comprises the following steps: firstly, capturing and decoding a storage command; secondly, allowing the storage command to enter the source capturing level and judging whether a later completion command is in the pipelined processing unit, wherein the later completion command is not later than the storage command and a later arrival result is generated before the later completion command enters the data writing level; thirdly, if the later completion command is judged to be in the pipelined processing unit, capturing the later arrival result before the storage command enters the data writing level; and finally, allowing the storage command to enter the data writing level and storing the captured later arrival result into a target memory corresponding to the storage command.
Description
Technical field
The invention relates to a kind of data storage method and the processor of using it, and particularly relevant for a kind of data storage method and its processor that is applied to have the processor of pipelined processing unit.
Background technology
Pipeline (pipeline) is a kind of technology that instruction can parallel execution that can allow, and can improve the hardware usefulness of processor.That is (output capacity means: the quantity of the instruction that the time per unit inner treater can be finished) to use the processor of pipeline mode can increase the output capacity (throughput) of instruction.And this kind processor also can not reduce the required processing time of each instruction.
Yet, under some situation, the execution usefulness that causes the processor that uses pipeline being reduced, this kind situation is referred to as the danger barrier (hazard) of processor.A kind of common danger barrier is data danger barrier.For instance, processing in the period, when processor will capture the corresponding storage data of save command in pipeline, and this storage data just in time is the execution result of a predetermined instruction (such as load instructions), at this moment, if this predetermined instruction not yet produces its execution result, just data danger barrier can occur.At this moment, processor just needs to suspend the carrying out of (stall) this save command when processing save command.So, will cause the execution Efficiency Decreasing of processor.
Therefore, how making processor need not suspend the carrying out of save command when data danger barrier occurs, improve the execution efficient of processor, is one of problem of endeavouring of industry.
Summary of the invention
The invention relates to a kind of data storage method and the processor of using it, can make processor when data danger barrier occurs, need not suspend the carrying out of save command.So, can increase the instruction output capacity of processor, reduce processor required time when executive routine, and can improve the execution efficient of processor.
According to a first aspect of the invention, a kind of data storage method is proposed, the processor of (pipeline) processing unit that is applied to have pipeline.Pipelined processing unit comprises a plurality of levels (stage), and these a plurality of levels comprise that at least a source capturing level and data write level.The method comprises the following steps.At first, acquisition (fetch) save command, and this save command of decoding.Then, make save command enter the source capturing level, and judged whether that late finish instruction (late-done instruction) is arranged in pipelined processing unit.The late finish instruction keeps abreast with save command, and the late finish instruction produces slow arrival result (late-coming result) before writing level entering data.Afterwards, be arranged in pipelined processing unit if be determined with the late finish instruction, then enter before data write level at save command, capture slow arrival result.Then, make save command enter data and write level, and the slow arrival result that captures is stored to the corresponding destination memory of save command.
According to a second aspect of the invention, propose a kind of data memory device, comprising: the parts of acquisition save command and this save command of decoding; Make this save command enter this source capturing level and judge whether that the late finish instruction is arranged in the parts of this pipelined processing unit, this late finish instruction keeps abreast with this save command, and this late finish instruction produces slow arrival result before writing level entering these data; If have this late finish instruction be arranged in this pipelined processing unit then this save command enter these data write level before the acquisition this slow arrival result parts; And make this save command enter the parts that these data write level and this slow arrival result that captures are stored to the corresponding destination memory of this save command.
According to a further aspect in the invention, propose a kind of processor, comprise pipelined processing unit and the first temporary storage location.Pipelined processing unit comprises a plurality of levels, and these a plurality of levels comprise that at least a source capturing level and data write level.Pipelined processing unit is in order to capturing save command, and this save command of decoding.Pipelined processing unit is with writing level so that save command sequentially enters source capturing level and data at least.Pipelined processing unit is also in order to have judged whether that the late finish instruction is arranged in pipelined processing unit.The late finish instruction keeps abreast with save command, and the late finish instruction produces slow arrival result before writing level entering data.The first temporary storage location is arranged at data and writes before the level, in order to store slow arrival result.Instruction is arranged in pipelined processing unit if pipelined processing unit is determined with late finish, and then pipelined processing unit also in order to enter at save command before data write level, captures slow arrival result.Pipelined processing unit also in order to enter data when save command when writing grade, is stored to the corresponding destination memory of save command with the slow arrival result that captures.
For foregoing of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the process flow diagram according to the data storage method of one embodiment of the invention.
Fig. 2 illustrates the process flow diagram according to the detailed step of the data storage method of one embodiment of the invention.
It is the synoptic diagram of an example of using the processing sequence of the pipelined processing unit of processor of data storage method of the present invention and instruction that Fig. 3 illustrates.
It is another routine synoptic diagram of using the processing sequence of the pipelined processing unit of processor of data storage method of the present invention and instruction that Fig. 4 illustrates.
Fig. 5 illustrates the calcspar for the processor of using data storage method of the present invention.
[main element label declaration]
320,420,520: pipelined processing unit 500: processor
560: the second temporary storage locations of 540: the first temporary storage locations
580: selected cell ALU: the arithmetic and logical unit instruction
E: execution level I: instruction acquisition level
LW: load instructions M: memory access level
MEM: destination memory S: source capturing level
S110～S140, S202～S222: process step SW: save command
W: data write level
Embodiment
Please refer to Fig. 1, it illustrates the process flow diagram according to the data storage method of one embodiment of the invention.The processor of this data storage method is applied to have pipeline (pipeline) processing unit.Pipelined processing unit comprises a plurality of levels (stage), and these a plurality of levels comprise that source capturing level and data write level.The method comprises the following steps.
At first, shown in step S110, acquisition (fetch) save command, and this save command of decoding.
Then, shown in step S120, make save command enter the source capturing level, and judged whether that late finish instruction (late-done instruction) is arranged in pipelined processing unit.The late finish instruction keeps abreast with save command, and the late finish instruction produces slow arrival result (late-coming result) before writing level entering data.
Be arranged in pipelined processing unit if be determined with the late finish instruction, execution in step S130 then enters before data write level at save command, captures slow arrival result.Then, shown in step S140, make save command enter data and write level, and the slow arrival result that captures is stored to the corresponding destination memory of save command.
Hereby the step-by-step procedures of the data storage method of Fig. 1 is as follows.Please refer to Fig. 2, it illustrates the process flow diagram according to the detailed step of the data storage method of one embodiment of the invention.
At first, shown in step S202, the acquisition save command.Then, shown in step S204, this save command of decoding.Decode after this save command the index value that just can obtain the corresponding storage data working storage of save command and working storage index value in order to the address that stores destination memory.
Then, shown in step S206, make save command enter the source capturing level.Then, shown in step S208, judged whether that the late finish instruction is arranged in pipelined processing unit.
Please note, in one embodiment, when having judged whether that the late finish instruction is arranged in pipelined processing unit, step S208 can also comprise following detailed step: at first, whether the index value of judging the corresponding storage data working storage of save command is identical with the index value of the corresponding destination of late finish instruction working storage, and wherein the destination working storage is in order to store slow arrival result.Afterwards, judge that save command enters in the source capturing level, whether the late finish instruction not yet produces slow arrival result.Then, judge that save command enters data and writes before the level, whether the late finish instruction has produced slow arrival result.In one embodiment, the slow arrival result that produces is stored in the temporary storage location.
If there is the late finish instruction to be arranged in pipelined processing unit, execution in step S210 then is made as a flag and is not ready for.If there is not the late finish instruction to be arranged in pipelined processing unit, execution in step S212 then is made as flag and is ready for.
Then, be positioned at before data write level at save command, execution in step S214 judges whether flag is set as to be ready for.
If flag is not to be set as to be ready for, execution in step S216 then, from then on temporary storage location captures slow arrival result.Then, shown in step S218, make save command enter data and write level, and the slow arrival result that captures is stored to the corresponding destination memory of save command.
If flag is set as and is ready for, then execution in step S220 captures storage data from the corresponding storage data working storage of save command.Then, shown in step S222, make save command enter data and write level, and storage data is stored to the corresponding destination memory of save command, and method ends.
Data storage method of the present invention can be applicable to have in the processor of pipelined processing unit, and above-mentioned late finish instruction can be arbitrary instruction.In one embodiment, the late finish instruction is for loading (load) instruction exclusive disjunction logical block (Arithmetic Logic Unit) instruction.Hereby with two examples that late finish instruction of the present invention is as follows.
First example
In first example, the late finish instruction is load instructions LW, and the loading data that the late finish result that the late finish instruction produces is load instructions LW to be produced.
Please refer to Fig. 3, it illustrates is the synoptic diagram of an example of using the processing sequence of the pipelined processing unit 320 of processor of data storage method of the present invention and instruction.Pipelined processing unit 320 comprise an instruction acquisition level I, source capturing level S, execution level E, memory access level M, and data write a grade W.
In Fig. 3, the direction that illustrates as " clock " is the order that is expressed as the time, and wherein, each processes the represented length of period C1～C6 is a machine cycle (machine cycle).In other words, the processing period at different levels of pipelined processing unit 320 is a machine cycle.
In this example, load instructions LW and save command SW are sequentially captured in instruction acquisition level I by pipelined processing unit 320.The load instructions LW that captures and save command SW are as follows respectively:
“lw?$1，0?($2)”
“sw?$1，0?($3)”
Wherein, load instructions LW (" lw $ 1; 0 ($ 2) ") is loaded in the destination working storage (its working storage index value is $ 1) in order to will load data (it is stored in the address in the destination memory of [$ 2]), and save command SW (" sw $ 1,0 ($ 3) ") in order to the data storing in the storage data working storage (its working storage index value is $ 1) to the address in the destination memory of [$ 3].
According to the detailed step of step S208, the index value ($ 1) that pipelined processing unit 320 will be judged the corresponding storage data working storage of save command SW is identical with the index value ($ 1) of the corresponding destination of load instructions LW working storage.
Moreover, as shown in Figure 3, load data and produced by load instructions LW (as processing period C4) when entering memory access level M.The old friend, pipelined processing unit 320 will judge that save command SW enters (as processing period C3) in the source capturing level S, load instructions LW not yet produces the loading data.And pipelined processing unit 320 judges that also save command SW enters data and writes before grade W (as processing before the period C6), and load instructions LW has produced the loading data.
The old friend, in first example, pipelined processing unit 320 will be considered as above-mentioned load instructions LW the late finish instruction, is arranged in pipelined processing unit 320 and be determined with the late finish instruction.
Second example
In second example, the late finish instruction is arithmetic and logical unit instruction ALU, and the late finish result that the late finish instruction produces is the operation result that arithmetic and logical unit instruction ALU produces.
Please refer to Fig. 4, it illustrates is another routine synoptic diagram of using the processing sequence of the pipelined processing unit 420 of processor of data storage method of the present invention and instruction.In this example, processor for example is SuperScale (superscalar) microprocessor of binary channels (two way) for carrying out simultaneously the processor of two instructions.Pipelined processing unit 420 comprise two instructions acquisition level I arranged side by side, two source capturing level S, two execution level E, two memory access level M, and two data write a grade W.
In this example, arithmetic and logical unit instruction ALU and save command LW are captured in instruction acquisition level I by pipelined processing unit 420 and 420 ' simultaneously.The arithmetic and logical unit instruction ALU that captures and save command LW are as follows respectively:
“add?$1，$1，1”
“sw?$1，0?($3)”
Wherein, arithmetic and logical unit instruction ALU (" add $ 1; $ 1; 1 ") add 1 in order to the numerical value that will be stored in the working storage that the working storage index value is $ 1, again operation result is stored in the destination working storage (its working storage index value is $ 1), and save command (" sw $ 1,0 ($ 3) ") in order to the data storing in the storage data working storage (its working storage index value is $ 1) to the address in the destination memory of [$ 3].
Similar in first example ground, the index value ($ 1) that pipelined processing unit 420 also can be judged the corresponding storage data working storage of save command SW is identical with the index value ($ 1) of the corresponding destination of arithmetic and logical unit instruction ALU working storage.
Moreover as shown in Figure 4, operation result is produced by arithmetic and logical unit instruction ALU (as processing period C3) when entering execution level E.The old friend, pipelined processing unit 420 will judge that save command SW enters (as processing period C2) in the source capturing level S, arithmetic and logical unit instruction ALU not yet produces operation result.And pipelined processing unit 420 judges that also save command SW enters data and writes before grade W (as processing before the period C5), and arithmetic and logical unit instruction ALU has produced operation result.
The old friend, in second example, pipelined processing unit 420 will be considered as the late finish instruction to above-mentioned arithmetic and logical unit instruction ALU, is arranged in pipelined processing unit 420 and be determined with the late finish instruction.
In above-mentioned two examples, when being determined with late finish instruction (such as load instructions LW exclusive disjunction logical block instruction ALU) when being arranged in pipelined processing unit, arrival result (loading data exclusive disjunction result) will be stored in temporary storage location 540 (not being illustrated in Fig. 3 and 4) late.Afterwards, be positioned at before data write grade W at save command SW, for example save command SW is being positioned at memory access level M or when execution level E (shown in the dotted line of Fig. 3 or Fig. 4), the slower arrival result of from then on temporary storage location 540 acquisitions.Then, enter data when writing grade W at save command SW, this slow arrival result is stored to the corresponding destination memory of save command SW.
So, by Fig. 3 and 4 as can be known, data danger barrier occurs in the source capturing level S even save command SW enters, meaning is that processor not yet can be obtained the slow arrival result that slow arriving instruction produces, processor also need not suspend the carrying out of this save command SW, obtain this slow arrival result as long as can be positioned at data at save command SW before writing grade W, just can finish the indicated operation of save command SW.
Therefore, the present invention can make processor need not suspend the carrying out of save command when data danger barrier occurs.So, can increase the instruction output capacity of processor, reduce processor required time when executive routine, and can improve the execution efficient of processor.
In addition, the present invention also proposes a kind of processor of using above-mentioned data storage method.Please refer to Fig. 5, it illustrates the calcspar for the processor 500 of using data storage method of the present invention.
The first temporary storage location 540 is to be arranged at data to write before grade W.Similarly, the second temporary storage location 560 also can be arranged at data with selected cell 580 and writes before grade W.
Hereby for example with two temporary storage locations 540 and 560 and the set-up mode of selected cell 580 be described as follows.In an embodiment, a plurality of level of this of pipelined processing unit 520 can also comprise at least one pipeline level, and this at least one pipeline level is to be arranged at source capturing level S and data write between grade W.
For instance, these a plurality of levels of pipelined processing unit 520 can also comprise such as Fig. 3 or memory access level M and execution level E shown in Figure 4.The late finish instruction produces slow arrival result when being positioned at memory access level M.And save command SW produces the address of corresponding destination memory MEM when carrying out execution level E.
Because memory access level M and execution level E all are arranged at data and write before grade W, so the first temporary storage location 540 can be arranged at memory access level M or execution level E.Similarly, the second temporary storage location 560 also can be arranged at memory access level M or execution level E with selected cell 580, in one embodiment, two temporary storage locations 540 and 560 and selected cell 580 be arranged on same one-level, wherein, store late order and when being positioned at this grade, produce slow arrival result.
The first temporary storage location 540 is in order to store slow arrival result, and it is by pipelined processing unit 520 stored person when the late finish instruction produces slow arrival result.The second temporary storage location 560 is in order to store storage data, and it is by pipelined processing unit 520 taker of picking from the corresponding storage data working storage of save command SW.Selected cell 580 is coupled to two temporary storage locations 540 and 560, is used to provide under the control of pipelined processing unit 520 one of them of slow arrival result and storage data.
Afterwards, be not ready for if flag is set as, then pipelined processing unit 520 is also in order to enter at save command SW before data write grade W, from the slow arrival result of the first temporary storage location 540 acquisitions.For example: pipelined processing unit 520 can be controlled selected cell 580, to capture slow arrival result from the first temporary storage location 540.Then, pipelined processing unit 520 enters data when writing grade W at save command SW, and the slow arrival result that captures is stored to the corresponding destination memory MEM of save command SW.
Accordingly, be ready for if flag is set as, pipelined processing unit 520 also in order to enter at save command SW data write grade W before control selected cell 580, with from the second temporary storage location 560 acquisition storage datas.Afterwards, pipelined processing unit 520 is positioned at data at save command SW and writes in grade W, and storage data is stored to the corresponding destination memory MEM of save command SW.
In the above embodiment of the present invention, be to explain as example just like the pipeline unit of Fig. 3 or Pyatyi shown in Figure 4 take preparation implement, it is explanation the present invention's usefulness, and is non-in order to limit the present invention.The disclosed data storage method of the present invention and the processor of using it also are applicable to the pipeline unit of other type.
The disclosed data storage method of the above embodiment of the present invention and the processor of using it can make processor need not suspend the carrying out of save command when data danger barrier occurs.So, can increase the instruction output capacity of processor, reduce processor required time when executive routine, and can improve the execution efficient of processor.
In sum, although the present invention discloses as above with embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (7)
1. data storage method, the processor that is applied to have pipelined processing unit, this pipelined processing unit comprises a plurality of levels, and these a plurality of levels comprise that at least a source capturing level and data write level, and the method comprises:
Acquisition save command, and this save command of decoding;
Make this save command enter this source capturing level, and judged whether that the late finish instruction is arranged in this pipelined processing unit, this late finish instruction keeps abreast with this save command, and this late finish instruction produces slow arrival result before writing level entering these data;
If there is this late finish instruction to be arranged in this pipelined processing unit, then enter before these data write level at this save command, capture this slow arrival result; And
Make this save command enter these data and write level, and this slow arrival result that captures is stored to the corresponding destination memory of this save command.
2. data storage method according to claim 1 judges whether that wherein the step that this late finish instruction is arranged in this pipelined processing unit comprises:
Whether the index value of judging the corresponding storage data working storage of this save command is identical with the index value of this corresponding destination of late finish instruction working storage, and wherein this destination working storage is in order to store this slow arrival result;
Judge that this save command enters in this source capturing level, whether this late finish instruction not yet produces this slow arrival result; And
Judge that this save command enters these data and writes before the level, whether this late finish instruction has produced this slow arrival result.
3. data storage method according to claim 1, wherein capture the step of this slow arrival result before, the method also comprises:
When this save command is positioned at this source capturing level, and when having this late finish instruction to be arranged in this pipelined processing unit, a flag is made as is not ready for; And
If this flag is set as be not ready for, then carry out this save command enter these data write level before the acquisition this slow arrival result step.
4. data storage method according to claim 1 also comprises:
When this save command is positioned at this source capturing level, and when this late finish instruction is not arranged in this pipelined processing unit, a flag is made as is ready for, and from the corresponding storage data working storage of this save command, capture storage data; And
If this flag is set as be ready for, then when this save command is positioned at these data and writes grade, this storage data be stored to corresponding this destination memory of this save command, and method ends.
5. data storage method according to claim 1 also comprises:
When this late finish instruction produces this slow arrival result, should slow arrival result be stored in the first temporary storage location.
6. data storage method according to claim 1, wherein these a plurality of levels comprise that also at least one pipeline level, this at least one pipeline level are to be arranged at this source capturing level and this data write between the level.
7. data memory device comprises:
The parts of acquisition save command and this save command of decoding;
Make this save command enter the source capturing level and judge whether that the late finish instruction is arranged in the parts of pipelined processing unit, this late finish instruction keeps abreast with this save command, and this late finish instruction produces slow arrival result before writing level entering these data;
If have this late finish instruction be arranged in this pipelined processing unit then this save command enter these data write level before the acquisition this slow arrival result parts; And
Make this save command enter the parts that these data write level and this slow arrival result that captures are stored to the corresponding destination memory of this save command.
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Citations (3)
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| CN1188932A (en) * | 1996-12-27 | 1998-07-29 | 国际商业机器公司 | Background completion of instruction and associated fetch request in multithread processor |
| CN1349160A (en) * | 2001-11-28 | 2002-05-15 | 中国人民解放军国防科学技术大学 | Correlation delay eliminating method for streamline control |
| CN1545026A (en) * | 2003-11-26 | 2004-11-10 | 中国人民解放军国防科学技术大学 | Dynamic VLIW command dispatching method according to determination delay |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1188932A (en) * | 1996-12-27 | 1998-07-29 | 国际商业机器公司 | Background completion of instruction and associated fetch request in multithread processor |
| CN1349160A (en) * | 2001-11-28 | 2002-05-15 | 中国人民解放军国防科学技术大学 | Correlation delay eliminating method for streamline control |
| CN1545026A (en) * | 2003-11-26 | 2004-11-10 | 中国人民解放军国防科学技术大学 | Dynamic VLIW command dispatching method according to determination delay |
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