CN101777796A - DSP (Digital Signal Processor)-based distributed fault recorder for electric system - Google Patents

DSP (Digital Signal Processor)-based distributed fault recorder for electric system Download PDF

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CN101777796A
CN101777796A CN 201010046548 CN201010046548A CN101777796A CN 101777796 A CN101777796 A CN 101777796A CN 201010046548 CN201010046548 CN 201010046548 CN 201010046548 A CN201010046548 A CN 201010046548A CN 101777796 A CN101777796 A CN 101777796A
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module
dsp
data
recording
wave
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CN 201010046548
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周俭节
李林
杨锐俊
金冶夫
陶维青
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合肥工业大学;上海科大鲁能集成科技有限公司
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Priority to CN 201010046548 priority Critical patent/CN101777796A/en
Publication of CN101777796A publication Critical patent/CN101777796A/en

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Abstract

The invention discloses a DSP (Digital Signal Processor)-based distributed fault recorder for an electric system, which is characterized in that the DSP is taken as a core control unit, and the peripheral modules of the DSP comprises an AC (alternating current) sampling module, a switching value input module, a voltage/current signal conditioning circuit, a zero-crossing detection circuit, a data storage module, a CAN (Controller Area Network) communication module, an RS485 communication module, an RS232 communication module, an Ethernet control module, a GPS (Global Position System) synchronous clock, a real-time clock, a switching value output module, a power module, an indicator light/press key module and an LCD (liquid crystal display) display module. The invention has greater strengthened capability of detection recording, enables the fault detection recording function to be more approaching perfect and has faster speed and higher precision and better satisfies the needs of rapid development in power sector.

Description

基于DSP的电力系统分布式故障录波装置 DSP-Based Distributed Power fault recorder

技术领域 FIELD

[0001] 本发明涉及一种电力系统故障检测录波装置,尤其是一种基于DSP的高性能分布式电力故障录波装置,属于电力供应配套设施技术领域。 [0001] The present invention relates to an electric power system fault detection wave recording means, in particular a high-performance DSP-based distributed power fault recording means belonging to a power supply facilities technical field.

背景技术 Background technique

[0002] 电力系统的故障录波装置是常年投入监视电力系统运行状况的一种自动记录装 Fault Recorder [0002] perennial power system input power system monitoring the health of an automatic recording apparatus

置,它可以记录因短路故障、系统振荡、频率崩溃、电压崩溃等大扰动引起的系统电流、系统 Position, it may be recorded by a short-circuit fault, the system oscillation, the frequency of crashes, crashes large disturbance voltage due to the current system, the system

电压及其导出量,如系统频率、有功、无功的全过程变化现象,同时还记录继电保护与安全 And deriving the amount of voltage, system frequency, active, reactive phenomena change the whole process, while also recording and security protection

自动装置的动作行为。 Automatic operation action apparatus. 性能优良的故障录波器对保证电力系统的安全可靠运行具有非常重 Excellent performance of the fault recorder has a very heavy to ensure safe and reliable operation of power systems

要的作用。 To the role. 80年代后,微机型故障录波器在电力系统中得到了广泛的应用,录波器的故障记 After 80 years, computer fault fault recorder has been widely used in mind, oscillograph in the power system

录进入已经成为分析事故发生原因,帮助寻找故障点,迅速处理事故,特别是分析继电保护 Has been recorded into the cause of the accident analysis to help find the point of failure, dealing with incidents quickly, especially protection analysis

动作行为的依据。 The basis of an action. 目前,它已成为电力系统自动化及系统管理的重要组成部分。 At present, it has become an important part of power system automation and systems management.

[0003] 国内对故障录波装置的研制和开发已经有多年的历史,早期的录波装置有机电式 [0003] domestic research and development of fault recorder has many years of history, the early wave recording devices have electromechanical

录波装置、光纤式录波装置和采用固态数据存储器的录波装置,目前很多场合使用的录波 Recording wave device, an optical fiber type recording apparatus and recording wave wave device employs a solid-state data storage is currently used in many instances recorded wave

器正逐渐由基于PC机的集中式录波器向基于微处理器的分布式录波器发展,集中式系统 It is being distributed gradually by the waveform recorder based on microprocessor-based development to centralized Fault Recorder the PC, centralized system

除了其固有的体积大、安装不灵活等缺陷外,还存在如下主要问题:a、同一个厂站内,系统 In addition to its inherent bulky, inflexible mounting defects, there is also a major problem: a, the same station within a plant, the system

采集器往往具有单一的动态存储器,在数据尚未转存的情况下,若系统又发生新的故障,受 Collector tend to have a single dynamic memory, when the data transfer has not been stored, the new system and if failure occurs, by

动态存储器容量的限制,往往采用简化记录甚至覆盖以前故障的方法,因此在现场,经常出 Dynamic memory capacity limitations, a method often used to cover even a simplified record previously failed, so in the field, frequently the

现由于误启动覆盖故障记录的问题,没有起到故障录波系统的作用;b、对远方录波主站来 Now the problem due to false start fault record cover, no fault record system functions; B, wave recording on remote master station

说,由于各个厂站故障录波装置数据采集不同步,给分析系统故障,特别是超高压环网或联 He said fault recording means since each plant data acquisition station is not synchronized to the analysis system failures, particularly ultra high pressure or a biphenyl ring

络线故障带来很大的困难。 Envelope failures caused great difficulties. 与集中式故障录波系统不同,分布式故障录波系统的录波数据 Recorded data with the centralized fault recording systems, distributed fault recording system

分布存储在各个录波装置中,在录波结束后,转发到远方的录波主站中。 Distribution stored in the respective recording wave device, after the recording wave, the distance A record forwarded to the master station. 分布式故障录波装 Distributed Fault Recorder installed

置克服了上述集中式的很多缺陷,而且适应电力自动化技术光纤化、网络化的发展趋势。 Counter overcomes the above centralized many defects, and adapt to the trend of automation technology optical and network power. near

几年,很多分布式故障录波装置多以单片机为前置机,以工控机为后台机的模块化结构,其 Years, many distributed fault recorder plurality microcontroller as FEP to back IPC structures modular machine which

录波数据存入工控机硬盘中,但是,采用单片机完成数据的采集、计算和判断难以提高数据 IPC recorded data stored in the hard disk, however, SCM complete data collection, calculation, and determination is difficult to increase data

采集的速度和精度,难以保证装置的准确启动录波,难以实现网络功能和多种通信能力。 Acquisition speed and accuracy, it is difficult to ensure accurate recording start wave device, it is difficult to achieve a variety of network functions and communication capabilities.

发明内容 SUMMARY

[0004] 本发明是为避免上述现有技术所存在的不足之处,提供一种基于DSP的电力系统分布式故障录波装置,以期检测录波能力更为强大、从而使故障检测录波装置功能更为完善、速度更快、精度更高,更好地满足电力行业迅速发展的需求。 [0004] The present invention is to avoid the above shortcomings of the prior art is present to provide a DSP-based distributed power system fault recording means to record the wave detection capability of more powerful, so that the failure detection wave recording means function more perfect, faster, more accurate, and better meet the needs of the rapid development of the power industry. [0005] 本发明为解决技术问题采用如下技术方案: [0005] The present invention adopts the following technical solution to solve the technical problem:

[0006] 本发明基于DSP的电力系统分布式故障录波装置的特点是以数字信号处理器DSP 为核心控制单元,所述数字信号处理器DSP的外围模块包括:交流采样模块、开关量输入模块、电压/电流信号调理电路、过零点检测电路、数据存储模块、CAN通讯模块、RS485通讯模块、RS232通讯模块、以太网控制模块、GPS同步时钟、实时时钟、开关量输出模块、电源模块、指示灯/按键模块和LCD显示模块; [0006] The present invention is based on the characteristics of fault recorder Distributed Power DSP is a digital signal processor DSP is a control unit, said digital signal processor DSP peripheral module comprises: a sampling module AC switch input module , the voltage / current signal conditioning circuit, zero-crossing detection circuit, a data storage module, CAN communication module, RS485 communication module, RS232 communication module, Ethernet control module, GPS synchronous clock, real time clock, digital output modules, power modules, indicated light / button module and LCD display module;

[0007] 所述交流采样模块通过设置有电流互感器CT和电压互感器PT的电压/电流信号调理电路与被测电网耦合,以所述电压/电流信号调理电路对被监测信号依次进行CT/PT 变换、滤波和分压处理,处理后的信号以差分方式输入交流采样模块中的多片级联采样芯片AD73360进行采样,所述多片级联采样芯片AD73360的采样输出数据由数字信号处理器DSP存入数据存储模块; [0007] By setting the sampling module AC voltage / current signal conditioning circuit under test is coupled with the grid transformers CT and the potential transformer PT current to the voltage / current signal is monitored for signal conditioning circuit sequentially CT / PT conversion, filtering, and dividing processing, the processed signal differentially cascade input sampling chip multi-chip module AD73360 AC sampling sample the output data of the multi-chip sampling chip AD73360 cascade by a digital signal processor DSP stored in the data storage module;

[0008] 以所述数字信号处理器DSP接受启动录波的控制信号,并启动录波;在启动录波后,通过数字信号处理器DSP的SPI接口将故障录波数据由数据存储模块中的外扩SDRAM 转存入存储SD卡内,故障录波数据通过RS485总线或以太网上传至远方录波主站,各录波装置之间是以CAN接口相互级联。 [0008] In the digital signal processor DSP receives a control signal to start the recording wave, and starts recording wave; wave after starting recording, a digital signal processor DSP via the SPI interface fault data by the data storage module SDRAM transfected into the extended SD card memory, fault data uploaded to the remote master record wave through the RS485 bus or Ethernet, CAN interfaces are cascaded to each other among the recording wave device.

[0009] 本发明基于DSP的电力系统分布式故障录波装置的特点也在于: [0009] The present invention also features that the DSP power system based on a distributed fault recorder:

[0010] 在未启动录波时,所述数字信号处理器DSP按照采样率si将采集数据更新在所述 [0010] When recording is not started the wave, according to the digital signal processor DSP sampling rate si updating the data collected

外扩SDRAM中的A段数据缓存区;录波启动后,所述数字信号处理器DSP按照采样率s2将 A SDRAM extended segment of data buffer; wave recorded after starting the digital signal processor (DSP) according to the sampling rate s2

采样数据存入紧随A段数据缓存区后的地址空间中,并且有:s2 > si ;以接入故障信号的 Sampling data stored immediately after the address space of the data cache segment A, and has: s2> si; access to the fault signal

录波装置作为主录波装置,在故障条件被检出后由所述主录波装置控制其余各录波装置的 Recording wave device as a master recording wave device, the rest of the recording wave device after the fault condition is detected by the primary recording wave controlled apparatus

采样频率。 Sampling frequency.

[0011] 所述交流采样模块中的级联采样芯片AD73360与数字信号处理器DSP的高速同步缓冲接口McBSP连接,设置McBSP的FIFO有效,来自所述DSP接收通道的数据将被进行栈式缓存,缓存的数据在达到设置的值后,所述DSP以中断方式取走缓存的数据,完成采样数据接收。 [0011] AD73360 cascade sampling chip digital signal processor DSP sampling module in the AC high-speed synchronous buffered interface connecting McBSP is provided a FIFO McBSP valid data received from the DSP channel will be performed stack caching, cached data after reaching the set value, the DSP to interrupt the removal of cached data, sample data receiving completion.

[0012] 将所述数据信号处理器DSP的GPI0F输入/输出接口分别配置为用于RS232、 RS485总线通信以及CAN总线通信的功能接口。 [0012] The GPI0F said input data signal processor DSP / output interfaces are configured to function interface RS232, RS485 communication bus and CAN bus communication.

[0013] 所述以太网控制模块采用W5100网络芯片,所述W5100网络芯片的相应引脚分别 [0013] The control module uses Ethernet network chip W5100, W5100 network the corresponding chip pins are

与所述数字信号处理器DSP的地址线AB、数据线DB和控制线CB连接。 AB address line of the digital signal processor DSP, the data lines DB and CB connected to the control line.

[0014] 在所述各录波装置之间采用基于GPS定位系统的同步采样,在任一录波装置满足 [0014] The synchronous sampling based GPS positioning system wave between said recording means in a recording wave device satisfies any

录波起动判据后,以起动脉冲信号同步起动各录波装置。 After recording start criterion wave, each wave recording means to start pulse signal synchronized start.

[0015] 已有技术相比,本发明具有以下有益效果: [0015] compared to the prior art, the present invention has the following advantages:

[0016] 1、本发明通过选用AD采样芯片AD73360与高速、高精度DSP芯片TMS320F2812 相结合,可实现对供电线路的实时、高速、多通道数据采集,该AD采样芯片分辨率为16位、 6通道,各通道有自己独立的AD转换器,通道间延时小,同步性好,采样数据串行输出,其输出端可与DSP的高速多通道缓冲串行口McBSP配合,完成数据高速传输,而且AD73360采用了E _ AA/D转换原理,所以具有良好的抗混叠性能,装置对模拟信号前端滤波器的要求不高,使电路结构趋于简洁; [0016] 1, the present invention is selected by the AD sampling chip AD73360 high-speed, high-precision TMS320F2812 DSP chip combining, enables real-time, high-speed, multi-channel data acquisition power supply line, a resolution of the AD sampling chip 16, 6 channels, each with its own separate AD converters, interchannel delay is small, good synchronization, sampling data serial output, which output can be buffered serial port McBSP conjunction with high-speed multichannel DSP, and high-speed data transmission is completed, Further AD73360 uses E _ AA / D conversion principle, and therefore have less demanding good anti-aliasing performance, means the front-end filter the analog signal, the circuit structure more simple;

[0017] 2、本发明由于利用SD卡与DSP芯片的SPI接口完成大容量录波数据以文件方式实现数据快速存储,满足了庞大的录波数据对存储空间的要求; [0017] 2, the present invention since the SD card and the SPI interface DSP chip mass recorded data in files stored data quickly to meet the enormous demand for recorded data storage space;

[0018] 3、本发明利用单片DSP芯片为核心器件,建立起多路互为备用的远程通信方式, 有RS485通信、CAN通信以及以太网通信,其中利用带有硬件协议栈的网络控制芯片W5100 实现大量数据高速远程传输,使得软件开发时间大大縮短,可靠性也得到提高; [0019] 4、本发明装置为消除非周期分量的影响,可以采用基于准同步采样的DFT变换实现谐波分析,同时通过Hilbert滤波方法计算无功量,具有很高的可靠性和准确度,在编程时力求有效、快速地实现这些复杂的算法,实现对数据的综合、统计等各种监测与录波功能,满足电力行业迅速发展的需求。 [0018] 3, the present invention utilizes a single DSP chip as the core components, establish mutual backup multiple remote communication system, a communication with RS485, CAN communication, and Ethernet communication, using a network control chip with which the hardware protocol stack W5100 large amount of data to achieve high-speed long-distance transmission, so that software development time is greatly reduced, reliability is improved; [0019] 4. the apparatus of the present invention to eliminate the influence of the non-periodic component, harmonic analysis can be based on the quasi-synchronous sampling uses DFT transform , while the amount of reactive power calculated by the Hilbert filter method, having high reliability and accuracy, efforts to make effective when programming, these complex algorithms quickly realize the integrated data, statistics and other monitoring and oscillograph the rapid development of the power industry to meet the demand.

[0020] 5、本发明采用的DSP运算速度快,所以可以实现丰富的录波启动方式,包括模拟量启动、开关量启动、手动启动和远方启动四种基本方式,其中模拟量启动方式含模拟量及其派生量的突变量启动、过量启动和欠量启动方式。 [0020] 5, DSP operation speed of the present invention uses fast, it is possible to achieve a rich start recording wave mode, including analog start, start switch, and remote manual start start four basic embodiment, in which the analog mode having an analog promoter the amount of mutation and its derivatives starting amount, the excess amount of start-up and under-start mode.

[0021] 6、各录波装置之间采用基于GPS定位系统的同步采样,全球定位系统GPS能够提供误差在1 PS以内的高精度时钟,而且采样模块的采样脉冲信号可以在每个整秒被GPS的秒脉冲信号同步1次,并为相应的采样值打上时间标记(分、秒),因此为各种装置提供了共同的时间基准。 [0021] 6, using the recorded wave between sampling means based on the synchronization of the GPS positioning system, GPS global positioning system capable of providing high-precision clock error within 1 PS, and the sampling pulse signal may be sampled in each module the second, second pulse signal synchronized GPS 1, and time stamped (minutes, seconds) for the corresponding sampling values, thus providing a common time reference for a variety of devices.

附图说明 BRIEF DESCRIPTION

[0022] 图1、图2分别为本发明的两种不同的网络通信结构图。 [0022] FIGS. 1 and 2 two different network communication structure of the present invention, respectively, FIG. [0023] 图3为本发明的硬件总体结构框图。 [0023] FIG 3 a block diagram showing the overall structure of a hardware of the present invention.

[0024] 图4为本发明中多片级联的采样芯片与DSP的接口电路图。 [0024] FIG. 4 is a circuit diagram of the invention interfaces with a DSP sampling chip multi-chip cascade.

[0025] 图5为本发明中测量电路原理图,是以单片AD采样芯片的单通道为代表,其余部分结构相同。 [0025] FIG. 5 of the present invention, the measurement circuit diagram, is a monolithic single-channel AD sampling chip represented same rest of the structure.

[0026] 图6为本发明中F2812与W5100硬件接口电路。 [0026] FIG. 6 F2812 W5100 with hardware interface circuit of the present invention. 具体实施方式 Detailed ways

[0027] 本实施例选用TMS320F2812芯片,充分利用其丰富的内部资源。 [0027] Example embodiment of the present TMS320F2812 chip selection, the full use of its abundant internal resources. TMS320F2812具有一个高速同步串行通信接口SPI,两个异步串行通信接口SCIA、 SCIB,改进的局域网络eCAN,多通道缓冲串行口McBSP。 TMS320F2812 McBSP port having a serial high-speed synchronous serial communication interface SPI, two asynchronous serial communication interfaces SCIA, SCIB, improved local area network eCAN, multi-channel buffer. 其中McBSP 口具有特色的FIFO单元使得通信操作变得更为可靠、快速、编程更加方便。 Wherein the FIFO unit McBSP port having characteristics such that communication operation becomes more reliable, rapid, easier programming.

[0028] 如图1、图2,具体实施可以用四种通信方式,RS232总线、RS485总线,CAN总线和以太网。 [0028] As shown in FIG 1, FIG. 2, the specific embodiment of four kinds of communication mode may be, RS232 bus, RS485 bus, CAN bus and Ethernet. 图1中,以一个装置为主设备,其它装置为从设备,主从设备之间有两种互为备用的通信方式,分别为:RS485总线通信方式和CAN总线通信方式,通过主设备的以太网接口通过路由器接入广域网。 In Figure 1, a device to the master device, the other device is a slave device, the master from each other there are two spare communication between devices, respectively: RS485 communication bus and CAN bus communication, the main device Ether network through a router interface to access the WAN. 图2中,各录波装置不分主从,通过各装置上的以太网接口直接由路由器接入广域网。 In FIG. 2, each of the recording means regardless of the wave from the primary access a wide area network, via the Ethernet interface on each device directly from the router. F2812内部集成了两个异步串行通信接口SCIA,SCIB,目前已经实现了通用的RS232和RS485标准接口,可以按国家电力行业标准104规约或自定义规约与子站通信,可以通过CAN总线实现与多个就地监测装置通信,通过RS232总线通信方式与上位机通信。 F2812 internal integration of two asynchronous serial communication interfaces SCIA, SCIB, has now achieved a common RS232 and RS485 standard interface, according to the national power industry standard or custom statute statute 104 communicates with the sub-station may be implemented with a CAN bus a plurality of communication devices in situ monitoring, through the RS232 bus communication to communicate with the host computer.

[0029] 如图3,本实施例中,对于需要监测的信号通过电压/电流互感器PT/CT变换、电阻取样和电容滤波变换为适合采集的交流信号,然后输入AD转换芯片内进行采样转换,带时标的采样值序列将存入RAM,同时对需要监测的信号做过零点检测,以获得其频率。 [0029] FIG. 3, in this embodiment, the signal need to be monitored by the voltage / current transformers PT / CT conversion, sampling resistor and capacitor filter for converting an AC signal acquisition, and then enter the sample conversion chip AD converter when the target sequence of sample values ​​with the stored RAM, while the need to monitor the signal detection done zero, to obtain its frequency. [0030] 录波器没有启动时,采样率为8kHz, DSP采集到的数据在经过计算、判断后就用来更新RAM中的一段数据缓存区,该区域大小可由用户设定,录波器启动后这段数据作为录波记录的A段。 [0030] When the waveform recorder does not start, the sampling rate is 8kHz, DSP collected data starts after calculation, it is determined after a period used to update the RAM data buffer, the size of the region set by the user, oscillograph after this data is recorded as the segment a wave recorded. 以24个模拟输入量为例,记录故障前7个周波,则A段数据存储空间为: 24X (8kHz/50Hz) X7X4 = 105kB,通过AD级联最多可扩充为48个模拟输入量,这时A段数据存储空间为:48X (8kHz/50Hz) X7X4 = 210kB,采用一片256kB的RAM很容易满足要求。 To 24 analog input, for example, before recording the fault seven cycles, the storage space for the data segment A: 24X (8kHz / 50Hz) X7X4 = 105kB, it can be expanded to 48 analog input through the AD cascade up, then a data segment storage space: 48X (8kHz / 50Hz) X7X4 = 210kB, 256kB of using a RAM to meet the requirements easily.

[0031] 录波器启动后,利用数据记录的间隙完成数据传送的任务,同时采样率由8kHz提高到16kHz,录波器将这批数据存入紧随A段后的地址空间中,待上位机有空闲后作为B段数据存入SD卡中,并通过RS485(备用)或以太网上传至远方录波主站。 After the [0031] recorded wave starts, the data recorded using the gap data transfer task, while up to 16kHz sampling rate 8kHz, oscillograph these data into the address space immediately following the segment A to be the upper after the machine into an idle section of data B as the SD card, and uploaded to the remote master station via the RS485 wave recording (standby) or Ethernet. 在进入D、E时段后,采样率恢复到8kHz。 After entering D, E period, to restore the sample rate 8kHz. 在有多个分布式装置的情况下,接入故障信号的分布式装置被作为主录波装置,当故障条件被检出后由该装置控制其余分布式装置的采样频率。 In the case where a plurality of distributed devices, the distributed device access failure signal is recorded as the main wave device, after the fault condition is detected when the sampling frequency of the rest of the distributed control apparatus by the device. 装置通过RS232接口与上位机通信,实现装置的就地维护;通过CAN总线,实现多个分布式故障检测录波装置的级联。 Apparatus via the RS232 interface to communicate with the host computer, achieve local maintenance of the apparatus; CAN bus, cascading a plurality of distributed failure detection wave recording apparatus. [0032] 具体电路详细介绍如下: [0033] 1、装置的主控电路实现 [0032] The specific circuit details are as follows: [0033] 1, a main control circuit means to achieve

[0034] 对于丰富的录波启动方式和多种通信能力,需要大量快速的数字信号处理,而DSP 芯片作为整个系统的核心部分,必须要具有丰富的内部资源和易于扩展的外部硬件接口。 [0034] A record for a rich variety of start-up mode and communication capabilities, requires a lot of fast digital signal processing, the DSP chip as the core of the whole system must be internal resources with rich and easily extensible external hardware interface. 本实施例选用TI公司的C2000系列中控制能力很强的DSP芯片TMS320F2812,其内部集成有128KX16的Flash和18KX16的单访问周期RAM,大量的通用或专用1/0,同时集成多通道缓冲串行口McBSP、UART通用异步串行口、SPI串行外围接口、SCI串行通讯接口、CAN控制器区域网络和看门狗等常用的外围接口电路。 The present embodiment selection of TI's C2000 series, a strong ability to control the DSP chip of TMS320F2812, integrated inside a single access cycle of 18KX16 128KX16 Flash and RAM, a large number of general purpose or special 1/0, while the integrated multi-channel buffered serial port McBSP, UART universal asynchronous serial port, SPI serial peripheral interface, SCI serial communication interface, CAN controller Area network, and other common peripheral interface watchdog circuit. TMS320F2812内部集成了CAN总线模块, 完全兼容CAN2. OB标准协议,速度可达1M。 TMS320F2812 internal integrated CAN bus module is fully compatible CAN2. OB standard protocols, speeds of up to 1M. 具有32个可编程消息邮箱,可运行于低功耗模式,可编程总线唤醒,对远程请求消息自动应答,仲裁丢失或传送出错后自动重发。 32 having programmable mail message, can operate in low power mode, the programmable bus wake, remote automatic response request message, transmits an arbitration lost, or automatic repeat the mistakes made. 本装置利用其自带的增强型CAN控制器ECAN设计CAN总线硬件与下位机通信。 This device uses its own Enhanced ECAN CAN controller hardware design CAN bus communicate with the lower bits. ECAN对外接口弓| 脚CANTXA和CANRXA经过光电耦合器的隔离后,外接CAN总线接口芯片共同构成CAN总线通信单元。 ECAN external interface bow | CANTXA foot through the isolation and CANRXA optocouplers, CAN external bus interface chip constitute the CAN bus communication unit.

[0035] 2 、装置的数据采集电路实现 [0035] 2, the data acquisition circuit apparatus achieved

[0036] 为了提高录波精度及监测实时性,本实施例结合DSP的多通道缓冲串行口McBSP 的特点,采用多通道、高分辨率16位、同步串口的AD采样芯片AD73360,实现数据采集。 [0036] In order to improve the accuracy of recording and monitoring of real-time wave, in conjunction with a DSP embodiment of the present multi-channel buffered serial port McBSP characteristics embodiment, multi-channel, high-resolution 16-bit, synchronous serial chip AD73360 AD sampling, data acquisition . 由于所选择的AD采样芯片和TMS320F2812型DSP都支持工业标准的六线同步串行接口,所以二者之间的接口电路非常简单。 Because of the selected type AD sampling chip TMS320F2812 DSP and support industry-standard six-wire synchronous serial interface, the interface circuit between the two is very simple. TMS320F2812的McBSP是一种同步串行接口,支持多种通信方式和SPI方式,可以比较灵活地进行配置,使用方便,尤其是用两个16级、32位的FIF0 代替DMA直接存储器存储方式,可节省大量时间以用于内部数据处理。 The TMS320F2812 McBSP is a synchronous serial interface, and supports a variety of communication SPI mode, can be configured more flexible, easy to use, especially with the two 16, 32 in place of the FIF0 DMA direct memory access manner, save a lot of time for the internal data processing. [0037] 3、数据存储模块实现 [0037] 3, the data storage module implemented

[0038] 本实施例通过外扩SDRAM来存储数据。 [0038] In this embodiment, extended SDRAM to store the data. 但由于模拟量的输入通道数较多、采样率高时,需要处理的数据就比较庞大,尤其在出现故障时,需要了解故障前后多个周波的数据,数据存储更为庞大,基于这种情况,本实施例中结合DSP的SPI接口,采用SD卡来存储数据,存储容量大,读取速度快。 However, due to large number of analog input channels, sampling rate, data to be processed is relatively large, in particular when a fault occurs, the fault before and after a plurality of cycles needed to understand the data, much larger data storage, based on this situation , SPI interfaces in conjunction with a DSP embodiment of the present embodiment, an SD card uses to store data, the storage capacity, fast read speed. SD卡有两种总线模式,即SD总线模式和SPI总线模式。 SD card, there are two bus modes, i.e., mode SD bus and SPI bus modes. 其中SD总线模式采用四条数据线并传输数据,数据传输速率高,但是传输协议杂,而用软件方法模拟SD总线又比较繁琐,并会降低SD卡数据传输速率;而SPI总线模式只有一条数据传输线,尽管数据传输速率较低,但是SPI总线模式的传输协议简单,易于实现,而且TMS320F2812具有一个高速SPI接口,为此本设计可采用SPI总线模式。 Wherein SD bus mode uses four data lines and transmitting data, the high data transfer rate, but the transmission protocol heteroaryl, while the analog SD bus by software methods and cumbersome, and would reduce the SD-card data transmission rate; and SPI bus modes only one data transmission line , despite the lower data transmission rate, but the SPI bus mode transmission protocol is simple, easy to implement, and having a high-speed TMS320F2812 SPI interface SPI bus may be employed for this mode of the present design. SPI总线主要通过三根线进行数据传输:同步时钟线SCK,主机输入/从机输出数据线MISO、主机输出/从机输入数据线MOSI,另外还有一条低电平有效从机片选线CS。 SPI bus data transfer mainly by three lines: a synchronization clock line SCK, the host input / output data lines from the MISO, master output / slave input data lines MOSI, in addition to an active low slave chip select line CS. SPI系统的片选信号以及同步时钟脉冲由主机提供。 SPI chip select signal and the system synchronizing clock pulses provided by the host.

[0039] 如图4,本实施例通过多片AD73360级联实现对多路模拟信号的高速同步采样, AD73360是6通道模拟输入的16位串行可编程A/D转换器,其内部有8个控制寄存器,分别为CRA、 CRB、 CRC、 CRD、 CRE、 CRF、 CRG、 CRH。 [0039] FIG 4, the present embodiment achieves high-speed synchronous sampling of analog signals by multiple cascade multiple AD73360, AD73360 6 is a 16-bit serial channel programmable analog input A / D converter, its internal 8 control registers, respectively, CRA, CRB, CRC, CRD, CRE, CRF, CRG, CRH. 由于采用E - AA/D转换原理,具有良好的内置抗混叠性能,所以对模拟前端滤波器的要求不高,用一阶RC低通滤波器就能满足要求; AD73360能保证六路模拟信号同时采样,在变换过程中延迟很小,并且无须CPU干预,有效地减少了由于采样时间不同而产生的相位误差。 Due E - AA / D converter principle, having a built-in anti-aliasing good performance, so the less demanding analog front end filter with a first-order RC low-pass filter to a demand; AD73360 ensure six analog signals simultaneously sampling, the delay in the transformation process is small, and without intervention by the CPU, effectively reducing the phase errors due to the different sampling times generated. 每个通道可以允许从直流到4kHz的模拟信号通过,且能提供77dB的信噪比。 Each channel can allow DC to 4kHz by the analog signal, and can provide a signal to noise ratio of 77dB. 由于其采样率和输入信号增益都是可编程的,当输入时钟为16. 384MHz时,采样率可分别设置为8kHz、16kHz、32kHz、64kHz ;增益可在OdB到38dB之间选择,因而它既适合于大信号的应用,也适合于小信号的应用。 Because of its input signal sampling rate and gain are programmable, when the input clock 16. 384MHz, the sampling rate may be respectively set to 8kHz, 16kHz, 32kHz, 64kHz; gain selectable between OdB to 38dB, and thus both suitable for large signal applications, also suitable for small-signal applications. AD73360还可以多片级联使用,从而扩充模拟输入的通道数,最多可级联8片即48个通道。 AD73360 multiple sheets may also be cascaded to expand the number of analog input channels, cascade up to 8 or 48 channels. 级联芯片数量与最高采样率关系如下: The number of cascaded chips with maximum sampling rate relationship is as follows:

[0040] [0040]

级联芯片数 2 3 4 5 6 7 8 Cascade number of chips 2345678

公式计算采样率上限(KHz) 82. 74 52. 72 42. 01 33. 71 28. 05 24. 16 21. 16 Sampling rate upper limit formula (KHz) 82. 74 52. 72 42. 01 33. 71 28. 05 24. 16 21. 16

芯片可取采样率fs(KHz) 64/32 /16/8 32/16/8 32/16/8 32/16/8 16/8 16/8 16/8 Preferably chip sampling rate fs (KHz) 64/32 / 16/8 32/16/8 32/16/8 32/16/8 16/8 16/8 16/8

工频信号每周波采样点数N 1280/640 /320/160 640/320 /160 640/320 /160 640/320 /160 320 /160 320 /160 320 /160 Frequency signal sampling points per cycle N 1280/640 / 320/160 640/320 / 160 640/320 / 160 640/320 / 160 320/160 320/160 320/160

[0041] 对AD73360的控制简单,只需完成其内部8个控制寄存器的初始化后,即可进入采样状态,而无需CPU干涉,选用AD73360芯片很好地满足了多路故障录波的设计要求。 [0041] AD73360 simple control, just after the completion of its internal initialization control register 8, to enter a sampling state, without CPU intervention, the chip selection AD73360 satisfy the design requirements of multiple fault record. AD73360与DSP TMS320F 2812之间通过串口连接,接口电路极其简单。 AD73360 between the DSP TMS320F 2812 via the serial port, the interface circuit is extremely simple. 在TMS320F2812依次写入各片AD73360各控制寄存器的控制字后,AD73360便可进入数据模式或混合模式开始对模拟信号进行同步采样,并采用时分多用技术将各通道采样数据依次送入TMS320F2812 中进行数字信号处理。 After the sheets are sequentially written TMS320F2812 control words of the control register AD73360, AD73360 can enter data mode or hybrid mode starts synchronous sampling an analog signal, and by using the TDMA technique TMS320F2812 sequentially into each channel in the sampled data digital signal processing. AD73360在这种方式下的级联方式相当于其内部各个ADC的一种延续,当四片级联时可以看成组成一片具有24个通道的AD73360,由于具有一致的匿CLK,且各通道之间的延时小, 一般为(25*M) uS (M为AD芯片级联的数量),所以级联的AD采样芯片之间具有很好的同步性。 AD73360 In this manner a cascade manner therein corresponds to a continuation of the respective ADC, when four cascade can be viewed as having a composition of 24 channels AD73360, because of the same hide the CLK, and each of the channels delay between small, typically (25 * M) uS (M is the number of cascaded AD chip), and they have good synchronization between the AD sampling chip cascade.

[0042] 图5为本实施例中测量电路原理图,多路电压、多路电流分别经过电压互感器PT、 电流互感器CT变换、电阻取样和电容滤波变换为适合采集的交流信号,然后以差分方式输入AD转换芯片内进行采样转换。 [0042] FIG. 5 is a schematic circuit diagram of the measuring embodiment, multiple voltage, multiple currents through the voltage transformer PT, converting the current transformer CT, resistor and capacitor sampling filter for converting an AC signal acquisition, and then differentially inputs the AD converting chip sample conversion.

[0043] 图6为F2812与W5100硬件接口电路,通过网络芯片W5100实现与以太网之间的远程通信。 [0043] FIG. 6 is a hardware interface circuit F2812 and W5100, W5100 remote communication with the network via an Ethernet chip. W5100是WIZnet公司2006年最新推出的固件网络芯片,它是在W3150A+的基础上,集成了以太网物理层RTL8201CP核,因此W5100集TCP/IP协议栈、以太网MAC和PHY 为一体。 WIZnet W5100 is the company's latest firmware 2006 network chip, which is based on the W3150A +, integrated Ethernet physical layer RTL8201CP nuclear, so W5100 set TCP / IP protocol stack, Ethernet MAC and PHY as a whole. W5100支持TCP、UDP、 ICMP、 IGMP、 IPv4、 ARP、PPPoe、Ethernet等网络协议;支持4 个独立的Socket通信,内部16K字节的发送/接收缓冲区可快速进行数据交换,最大通信速率达到25Mbps ;支持直接并行总线接口、间接并行总路线接口以及SPI串行总线接口方式,可以很方便地与各种单片机或DSP连接。 W5100 supports TCP, UDP, ICMP, IGMP, IPv4, ARP, PPPoe, Ethernet and other network protocols; supports four independent Socket Communications, 16K bytes of internal transmit / receive buffer fast data exchange, to achieve the maximum communication rate 25Mbps ; supports direct parallel bus interface, a parallel indirect general line interface and SPI serial bus interface, it can be easily connected to various microcontroller or DSP. 使用W5100不需要考虑以太网的控制,只需要进行简单的端口Socket编程。 W5100 does not need to consider using Ethernet control, need only a simple port Socket programming.

Claims (6)

  1. 基于DSP的电力系统分布式故障录波装置,其特征是以数字信号处理器DSP为核心控制单元,所述数字信号处理器DSP的外围模块包括:交流采样模块、开关量输入模块、电压/电流信号调理电路、过零点检测电路、数据存储模块、CAN通讯模块、RS485通讯模块、RS232通讯模块、以太网控制模块、GPS同步时钟、实时时钟、开关量输出模块、电源模块、指示灯/按键模块和LCD显示模块;所述交流采样模块通过设置有电流互感器CT和电压互感器PT的电压/电流信号调理电路与被测电网耦合,以所述电压/电流信号调理电路对被监测信号依次进行CT/PT变换、滤波和分压处理,处理后的信号以差分方式输入交流采样模块中的多片级联采样芯片AD73360进行采样,所述多片级联采样芯片AD73360的采样输出数据由数字信号处理器DSP存入数据存储模块;以所述数字信号处理器DSP接受启动 Fault recording means based DSP distributed power system, which is characterized as the core digital signal processor DSP control means, the digital signal processor DSP peripheral module comprises: a module AC sampling, digital input module, a voltage / current signal conditioning circuit for zero-crossing detection circuit, a data storage module, CAN communication module, RS485 communication module, RS232 communication module, Ethernet control module, GPS synchronous clock, real time clock, digital output module, power module, the indicator / key module and LCD display module; the AC sampling module provided with a voltage / current signal conditioning circuit coupled to the grid and the measured current transformer CT and the potential transformer PT to the voltage / current signal conditioning circuit is sequentially monitoring signal CT / PT conversion, filtering, and dividing processing, the processed signal differentially cascade input sampling chip multi-chip module AD73360 AC sampling sample the output data of the multi-chip sampling chip AD73360 cascade by a digital signal stored in the data storage module processor DSP; a digital signal processor DSP to start receiving 录波的控制信号,并启动录波;在启动录波后,通过数字信号处理器DSP的SPI接口将故障录波数据由数据存储模块中的外扩SDRAM转存入存储SD卡内,故障录波数据通过RS485总线或以太网上传至远方录波主站,各录波装置之间是以CAN接口相互级联。 Recording wave control signal, and starts recording wave; wave after starting recording, a digital signal processor DSP via the SPI interface fault data from the data storage module stores the extended rotation SDRAM memory SD card, recording failure wave data uploaded to the remote master record wave through the RS485 bus or Ethernet, CAN interfaces are cascaded to each other among the recording wave device.
  2. 2. 根据权利要求1所述的基于DSP的电力系统分布式故障录波装置,其特征是在未启动录波时,所述数字信号处理器DSP按照采样率sl将采集数据更新在所述外扩SDRAM中的A段数据缓存区;录波启动后,所述数字信号处理器DSP按照采样率s2将采样数据存入紧随A段数据缓存区后的地址空间中,并且有:s2 > sl ;以接入故障信号的录波装置作为主录波装置,在故障条件被检出后由所述主录波装置控制其余各录波装置的采样频率。 2. The DSP-based distributed power system fault recording apparatus according to claim 1, characterized in that the wave does not start recording when the digital signal processor (DSP) according to the sampling rate sl collecting data updated in said outer a segment expanding the SDRAM data buffer; wave recorded after starting the digital signal processor (DSP) according to the sampling rate s2 sample data into an address space immediately after the data cache segment a, and has: s2> sl ; wave recording means to access a main fault signal recording wave device, the rest of the recording sampling frequency wave apparatus after the fault condition is detected by the primary wave recording control means.
  3. 3. 根据权利要求1所述的基于DSP的电力系统分布式故障录波装置,其特征是所述交流采样模块中的级联采样芯片AD73360与数字信号处理器DSP的高速同步缓冲接口McBSP 连接,设置McBSP的FIFO有效,来自所述DSP接收通道的数据将被进行栈式缓存,缓存的数据在达到设置的值后,所述DSP以中断方式取走缓存的数据,完成采样数据接收。 3. DSP-based distributed power system fault recording apparatus according to claim 1, characterized in that the cascade AD73360 sampling chip digital signal processor DSP with the exchange of high-speed synchronous sampling module McBSP buffered interface connector, McBSP is provided a FIFO valid data received from the DSP channel will be performed stacker cache, the cached data after reaching the set value, the DSP to interrupt the removal of cached data, sample data receiving completion.
  4. 4. 根据权利要求1所述的基于DSP的电力系统分布式故障录波装置,其特征是将所述数据信号处理器DSP的GPIOF输入/输出接口分别配置为用于RS232、RS485总线通信以及CAN总线通信的功能接口。 4. The distributed power system fault recorder based on DSP according to claim 1, wherein said input data is GPIOF signal processor DSP / output interfaces are configured for RS232, RS485 and CAN bus communication functional interface bus communication.
  5. 5. 根据权利要求1所述的基于DSP的电力系统分布式故障录波装置,其特征是所述以太网控制模块采用W5100网络芯片,所述W5100网络芯片的相应引脚分别与所述数字信号处理器DSP的地址线AB、数据线DB和控制线CB连接。 The DSP-based distributed power system fault recording apparatus according to claim 1, wherein said control module uses Ethernet network chip W5100, W5100 network corresponding pin of the chip with the digital signal, respectively DSP processor address lines AB, DB and a data line connected to a control line CB.
  6. 6. 根据权利要求1所述的基于DSP的电力系统分布式故障录波装置,其特征是在所述各录波装置之间采用基于GPS定位系统的同步采样,在任一录波装置满足录波起动判据后,以起动脉冲信号同步起动各录波装置。 6. A DSP-based distributed power system fault recording apparatus according to claim 1, characterized in that the synchronous sampling based GPS positioning system between said recording wave device satisfies any record in a recording wave wave device after starting criterion, each of the recording means to start pulse signal wave synchronized start.
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CN103840554A (en) * 2014-03-04 2014-06-04 国电南京自动化股份有限公司 Distributed type fault recording and network analyzing system of intelligent substation
CN104215878A (en) * 2014-08-12 2014-12-17 上海交通大学 Device and method for recording fault waveforms of power distribution lines
CN104237827A (en) * 2014-09-13 2014-12-24 安徽鑫龙电器股份有限公司 Electric power meter fault recording method
CN104360611A (en) * 2014-09-28 2015-02-18 国家电网公司 Concentrated automatic power supply switch on and off control system for fault recorder
CN104407551A (en) * 2014-12-08 2015-03-11 东莞市毫克检测仪器有限公司 Synchronous control acquisition card for mechanical instrument
CN105259395A (en) * 2015-11-13 2016-01-20 国网江西省电力科学研究院 Metering condition characteristic detector
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