CN101777796A - DSP (Digital Signal Processor)-based distributed fault recorder for electric system - Google Patents
DSP (Digital Signal Processor)-based distributed fault recorder for electric system Download PDFInfo
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Abstract
The invention discloses a DSP (Digital Signal Processor)-based distributed fault recorder for an electric system, which is characterized in that the DSP is taken as a core control unit, and the peripheral modules of the DSP comprises an AC (alternating current) sampling module, a switching value input module, a voltage/current signal conditioning circuit, a zero-crossing detection circuit, a data storage module, a CAN (Controller Area Network) communication module, an RS485 communication module, an RS232 communication module, an Ethernet control module, a GPS (Global Position System) synchronous clock, a real-time clock, a switching value output module, a power module, an indicator light/press key module and an LCD (liquid crystal display) display module. The invention has greater strengthened capability of detection recording, enables the fault detection recording function to be more approaching perfect and has faster speed and higher precision and better satisfies the needs of rapid development in power sector.
Description
Technical field
The present invention relates to a kind of electrical power system malfunction detection wave recording device, especially a kind of high-performance distributed power failure recorder based on DSP belongs to supply of electric power auxiliary facility technical field.
Background technology
The fault wave recording device of electric power system is to drop into a kind of self-recording unit that monitors the power system operation situation throughout the year; it can write down system power, system voltage and the derived quantity thereof that causes because of big disturbance such as short trouble, system oscillation, frequency collapse, voltage collapse; as system frequency, meritorious, idle overall process variation phenomenon, also write down the action behavior of relaying protection and automatic safety device simultaneously.The fault oscillograph of function admirable has important effect to the safe and reliable operation that guarantees electric power system.After the eighties; the microcomputer type fault oscillograph has obtained using widely in electric power system, and the failure logging of oscillograph enters becomes analysis accident occurrence cause, helps the trouble-shooting point; rapid processing accident is particularly analyzed the foundation of relaying protection action behavior.At present, it has become the important component part of Automation of Electric Systems and system management.
Domestic development and exploitation to fault wave recording device had for many years history, early stage wave recording device has the electromechanical wave recording device, the wave recording device of optical fiber type wave recording device and the solid-state data storage of employing, the oscillograph that at present a lot of occasions are used is developed to the distributed wave recording device based on microprocessor by the centralized oscillograph based on PC just gradually, integrated system is big except its intrinsic volume, install outside the defective such as dumb, also there is following subject matter: a, in the same factory station, the system acquisition device often has single dynamic memory, in data as yet not under the situation of unloading, if new fault takes place again in system, be subjected to the restriction of dynamic memory capacity, often adopt and simplify the method that writes down even cover with prior fault, therefore at the scene, often occur not playing the effect of fault recording system because error starting covers the problem of failure logging; B, concerning distant place record ripple main website because each factory's station failure wave recording device data acquisition is asynchronous, bring very big difficulty for analytical system fault, particularly superhigh pressure looped network or interconnection fault.Different with centralized fault recording system, the recorder data distributed store of distributed fault record wave system system after the record ripple finishes, is forwarded in the record ripple main website in a distant place in each wave recording device.The distributed fault wave recording device has overcome above-mentioned centralized a lot of defectives, and adapts to the development trend of the fiberize of power automation technology, networking.In recent years, a lot of distributed fault wave recording devices are many to be front end processor with the single-chip microcomputer, with the industrial computer is the modular construction of background computer, its recorder data deposits in the industrial computer hard disk, but, collection, calculating and the judgement of adopting single-chip microcomputer to finish data are difficult to improve the speed and the precision of data acquisition, are difficult to the accurate startup record ripple of assurance device, are difficult to realize network function and multiple communication capacity.
Summary of the invention
The present invention is for avoiding above-mentioned existing in prior technology weak point, a kind of electric power system distributed fault wave recording device based on DSP is provided, thereby record wave energy power is more powerful to make that the malfunction detection wave recording device function is more perfect, speed is faster, precision is higher in the hope of detecting, and satisfies the demand that power industry develops rapidly better.
The present invention adopts following technical scheme for the technical solution problem:
The characteristics that the present invention is based on the electric power system distributed fault wave recording device of DSP are to be key control unit with the digital signal processor DSP, and the peripheral module of described digital signal processor DSP comprises: AC sampling module, switching input module, voltage/current signals modulate circuit, zero-crossing detection circuit, data memory module, CAN communication module, RS485 communication module, RS232 communication module, ethernet control module, GPS synchronised clock, real-time clock, switching value output module, power module, indicator light/key-press module and LCD display module;
Voltage/current signals modulate circuit and the tested electrical network coupling of described AC sampling module by being provided with current transformer CT and voltage transformer pt, with described voltage/current signals modulate circuit monitored signal is carried out CT/PT conversion, filtering and voltage division processing successively, signal after the processing is sampled with the multi-disc cascade sampling A AD73360 in the differential mode input AC sampling module, and the sampling dateout of described multi-disc cascade sampling A AD73360 deposits data memory module in by digital signal processor DSP;
Accept to start the control signal of record ripple with described digital signal processor DSP, and start the record ripple; After starting the record ripple, SPI interface by digital signal processor DSP is gone into to store in the SD card by the SDRAM unloading that extends out in the data memory module with fault recorder data, fault recorder data is uploaded to distant place record ripple main website by RS485 bus or Ethernet, is with the mutual cascade of CAN interface between each wave recording device.
The characteristics that the present invention is based on the electric power system distributed fault wave recording device of DSP also are:
When not starting the record ripple, described digital signal processor DSP is updated in A segment data buffer area among the described SDRAM of extending out according to sample rate s1 with image data; After the record ripple started, described digital signal processor DSP deposited sampled data in the address space that follows closely behind the A segment data buffer area in according to sample rate s2, and has: s2＞s1; As main wave recording device, be detected all the other each wave recording devices are controlled in the back by described main wave recording device sample frequency with the wave recording device that inserts fault-signal at fault condition.
Cascade sampling A AD73360 in the described AC sampling module is connected with the high-speed synchronous buffer interface McBSP of digital signal processor DSP, the FIFO that McBSP is set is effective, data from described DSP receive path will be carried out stack formula buffer memory, data in buffer is after reaching the value of setting, described DSP takes data in buffer away with interrupt mode, finishes sampled data and receives.
The GPIOF input/output interface of described data signal processor DSP is configured to be used for the functional interface of RS232, RS485 bus communication and CAN bus communication respectively.
Described ethernet control module adopts the W5100 network chip, and the respective pins of described W5100 network chip is connected with control line CB with address wire AB, the data wire DB of described digital signal processor DSP respectively.
Between described each wave recording device, adopt synchronized sampling, after arbitrary wave recording device satisfies record ripple starting criterion, with each wave recording device of start dialing signal synchronous initiation based on the GPS navigation system.
Prior art is compared, and the present invention has following beneficial effect:
1, the present invention is by selecting AD sampling A AD73360 and high speed for use, high accuracy dsp chip TMS320F2812 combines, can realize to supply line in real time, at a high speed, multi-channel data acquisition, this AD sampling A resolution is 16,6 passages, each passage has oneself independently AD converter, the interchannel time-delay is little, synchronism is good, sampled data serial output, its output can cooperate with the high-speed multiple channel buffering serial port McBSP of DSP, finish data high-speed transmission, and AD73360 adopted ∑-Δ A/D transfer principle, so have good anti-aliasing performance, device is less demanding to the analog signal front end filter, makes circuit structure be tending towards succinct;
2, the present invention realizes the data quick storage owing to utilize the SPI interface of SD card and dsp chip to finish big capacity recorder data with file mode, has satisfied the requirement of huge recorder data to memory space;
3, the present invention utilizes the monolithic dsp chip to be core devices, set up the standby each other telecommunication mode of multichannel, RS485 communication, CAN communication and ethernet communication are arranged, wherein utilize the network control chip W5100 that has hardware protocol stacks to realize the transmission of mass data high-speed remote, make the software development time shorten greatly, reliability also is improved;
4, apparatus of the present invention are for eliminating the influence of aperiodic component, can adopt DFT conversion to realize harmonic analysis based on accurate synchronized sampling, calculate idle amount by the Hilbert filtering method simultaneously, have very high reliability and accuracy, when programming, make every effort to realize effectively and quickly these complicated algorithm, realization is satisfied the demand that power industry develops rapidly to the various monitorings and record wave energy such as comprehensive, statistics of data.
5, the DSP fast operation of the present invention's employing, so can realize the record ripple Starting mode enriched, comprise that analog quantity starts, switching value starts, manually boot and four kinds of basic modes of distant place startup that wherein the analog quantity Starting mode contains the sudden change amount startup of analog quantity and derivation amount thereof, excessive startup and the amount of owing Starting mode.
6, adopt synchronized sampling between each wave recording device based on the GPS navigation system, global position system GPS can provide error at 1 μ S with interior high precision clock, and the sampling pulse signal of sampling module can be whole second by synchronous 1 time of the pps pulse per second signal of GPS at each, and stamp time mark (minute, second) for corresponding sampled value, therefore provide common time reference for various devices.
Description of drawings
Fig. 1, Fig. 2 are respectively two kinds of different network service structure charts of the present invention.
Fig. 3 is a hardware architecture block diagram of the present invention.
Fig. 4 is the sampling A of multi-disc cascade among the present invention and the interface circuit figure of DSP.
Fig. 5 is measuring circuit schematic diagram among the present invention, is that the single channel with monolithic AD sampling A is representative, and the remainder structure is identical.
Fig. 6 is F2812 and W5100 hardware interface circuit among the present invention.
Embodiment
Present embodiment is selected the TMS320F2812 chip for use, makes full use of its abundant internal resource.TMS320F2812 has a high-speed synchronous serial communication interface SPI, two asynchronous serial communication interface SCIA, SCIB, improved LAN eCAN, multichannel buffer serial port McBSP.Wherein the characteristic cell fifo of McBSP mouth makes that traffic operation becomes more reliable, quick, programming is convenient.
As Fig. 1, Fig. 2, concrete enforcement can be with four kinds of communication modes, RS232 bus, RS485 bus, CAN bus and Ethernet.Among Fig. 1, with a device is main equipment, and other device has two kinds of standby each other communication modes for slave unit between the master-slave equipment, be respectively: RS485 bus communication mode and CAN bus communication mode, the Ethernet interface by main equipment inserts wide area network by router.Among Fig. 2, each wave recording device is regardless of the principal and subordinate, directly inserts wide area network by router by the Ethernet interface on each device.Inner integrated two the asynchronous serial communication interface SCIA of F2812, SCIB, general RS232 and RS485 standard interface have been realized at present, can communicate by letter with the substation by State Grid's industry standard 104 stipulations or self-defined stipulations, can realize communicating by letter by the CAN bus, communicate by letter with host computer by RS232 bus communication mode with a plurality of monitoring devices on the spot.
As Fig. 3, in the present embodiment, for needing monitored signal to be transformed to the AC signal that is fit to collection by voltage/current instrument transformer PT/CT conversion, resistance sampling and capacitor filtering, import then and carry out sample conversion in the AD conversion chip, target sampled value sequence row will deposit RAM in during band, simultaneously the needs monitored signal is done zero crossing and detect, to obtain its frequency.
When oscillograph was not activated, sample rate was 8kHz, and the data that DSP collects just are used for upgrading the one piece of data buffer area among the RAM after through calculating, judgement, and this area size can be set by the user, and oscillograph starts the A section that this segment data of back writes down as the record ripple.With 24 analog input amounts is example, preceding 7 cycles of record trouble, then A segment data memory space is: 24 * (8kHz/50Hz) * 7 * 4=105kB, extendible at most by the AD cascade is 48 analog input amounts, at this moment A segment data memory space is: 48 * (8kHz/50Hz) * 7 * 4=210kB, adopt the RAM of a slice 256kB to be easy to meet the demands.
After oscillograph starts, utilize the gap of data record to finish the task that data transmit, sample rate is brought up to 16kHz by 8kHz simultaneously, oscillograph deposits this batch data in the address space that follows closely after the A section, treat that host computer has idle back to deposit in the SD card as the B segment data, and be uploaded to distant place record ripple main website by RS485 (standby) or Ethernet.Entering D, E after the period, sample rate returns to 8kHz.Having under the situation of a plurality of distributed devices, the distributed devices that inserts fault-signal is used as main wave recording device, is controlled the sample frequency of all the other distributed devices after fault condition is detected by this device.Device is communicated by letter with host computer by the RS232 interface, the maintenance on the spot of implement device; By the CAN bus, realize that a plurality of distributed faults detect the cascade of wave recording device.
Physical circuit is described in detail as follows:
1, the governor circuit of device is realized
For abundant record ripple Starting mode and multiple communication capacity, need in a large number Digital Signal Processing fast, and dsp chip must have abundant internal resource and the external hardware interface that is easy to expand as the core of whole system.Present embodiment is selected the very strong dsp chip TMS320F2812 of control ability in the C2000 series of TI company for use, its inside is integrated with single access cycle of the RAM of the Flash of 128K * 16 and 18K * 16, a large amount of universal or special I/O, peripheral interface circuit commonly used such as integrated multichannel buffer serial port McBSP, the universal asynchronous serial port of UART, SPI serial peripheral interface, SCI serial communication interface, CAN controller zone network and house dog simultaneously.The inner integrated CAN bus module of TMS320F2812, complete compatible CAN2.0B standard agreement, speed can reach 1M.Have 32 message mailbox able to programme, can run on low-power consumption mode, programmable bus wakes up, and to the automatic-answering back device of remote request message, arbitration is lost or transmitted the back of makeing mistakes and retransmit automatically.This device utilizes its enhancement mode CAN controller ECAN that carries design CAN bus hardware to communicate by letter with slave computer.ECAN external interface pin CANTXA and CANRXA are through after the isolation of photoelectrical coupler, and external CAN Bus Interface Chip constitutes CAN bus communication unit jointly.
2, the data acquisition circuit of device is realized
In order to improve record ripple precision and monitoring real-time, present embodiment adopts the AD sampling A AD73360 of multichannel, 16 of high-resolution, synchronous serial interface in conjunction with the characteristics of the multichannel buffer serial port McBSP of DSP, realizes data acquisition.Because selected AD sampling A and TMS320F2812 type DSP be six line locking serial line interfaces of supporting industry standard, so the interface circuit between the two is very simple.The McBSP of TMS320F2812 is a kind of synchronous serial interface, support multiple communication mode and SPI mode, can be configured more neatly, easy to use, especially with two 16 grades, 32 FIFO replacement DMA direct memory storage mode, can save the plenty of time and handle to be used for internal data.
3, data memory module is realized
Present embodiment is stored data by extending out SDRAM.But because the input channel number of analog quantity is more, when sample rate is high, need the data of processing just huger, especially when breaking down, need to understand the data of a plurality of cycles in fault front and back, storage is more huge, in view of the situation, in the present embodiment in conjunction with the SPI interface of DSP, adopt the SD card to store data, memory capacity is big, and reading speed is fast.The SD card has two kinds of mode bus, i.e. SD mode bus and spi bus pattern.Wherein the SD mode bus adopts four data wires and transmits data, the message transmission rate height, but host-host protocol is assorted, and more loaded down with trivial details with software approach simulation SD bus, and can reduce SD card message transmission rate; And the spi bus pattern has only a data line, although message transmission rate is lower, the host-host protocol of spi bus pattern is simple, be easy to realize, and TMS320F2812 has a high speed SPI interface, and the design can adopt the spi bus pattern for this reason.Spi bus mainly carries out transfer of data by three lines: synchronised clock line SCK, main frame input/slave output data line MISO, main frame output/slave input data line MOSI also have the effective slave chip select line of a low level CS in addition.The chip selection signal and the synchronous clock pulse of SPI system are provided by main frame.
As Fig. 4, present embodiment is realized the high-speed synchronous of multichannel analog signals is sampled by multi-disc AD73360 cascade, AD73360 is the 16 Bits Serial programmable A/D transducer of 6 tunnels analogies input, there are 8 control registers its inside, is respectively CRA, CRB, CRC, CRD, CRE, CRF, CRG, CRH.Owing to adopt ∑-Δ A/D transfer principle, has good built-in anti-aliasing performance, so less demanding to the AFE (analog front end) filter just can meet the demands with single order RC low pass filter; AD73360 can guarantee that six tunnel analog signals sample simultaneously, postpones very for a short time in conversion process, and need not intervene by CPU, has reduced effectively because the phase errors that the sampling time difference produces.Each passage can allow the analog signal from the direct current to 4kHz to pass through, and the signal to noise ratio of 77dB can be provided.Because its sample rate and input signal gain all are programmable, when input clock was 16.384MHz, sample rate can be set to 8kHz, 16kHz, 32kHz, 64kHz respectively; Gain can be selected between the 38dB at 0dB, thereby it both had been suitable for the application of large-signal, also is suitable for the application of small-signal.AD73360 can also use in the multi-disc cascade, thereby expands the port number of analog input, but 8 of cascades are 48 passages at most.Cascade chip quantity is as follows with high sampling rate relation:
| The cascade chip number | ??2 | ??3 | ??4 | ??5 | ??6 | ??7 | ??8 |
| The formula calculating sampling rate upper limit (KHz) | ??82.74 | ??52.72 | ??42.01 | ??33.71 | ??28.05 | ??24.16 | ??21.16 |
| The desirable sample rate f s of chip (KHz) | ??64/32??/16/8 | ??32/16/8 | ??32/16/8 | ??32/16/8 | ??16/8 | ??16/8 | ??16/8 |
| Power frequency component is ripple sampling number N weekly | ??1280/640??/320/160 | ??640/320??/160 | ??640/320??/160 | ??640/320??/160 | ??320??/160 | ??320??/160 | ??320??/160 |
Control to AD73360 is simple, only need finish the initialization of its inner 8 control registers after, can enter sample states, interfere and need not CPU, select for use the AD73360 chip to satisfy the designing requirement of multichannel failure wave-recording well.Be connected by serial ports between AD73360 and the DSP TMS320F 2812, interface circuit is extremely simple.Write the control word of each each control register of sheet AD73360 successively at TMS320F2812 after, AD73360 just can enter data pattern or mixed mode to begin analog signal is carried out synchronized sampling, and adopts the timedivision multiplexing technology that each channel sample data is sent into successively and carry out Digital Signal Processing among the TMS320F2812.AD73360 cascade system in this manner is equivalent to a kind of continuity of its inner each ADC, when four cascades, can regard as and form the AD73360 that a slice has 24 passages, owing to have consistent DMCLK, and the time-delay between each passage is little, be generally (25*M) uS (M is the quantity of AD chip cascade), so have good synchronism between the AD sampling A of cascade.
Fig. 5 is a measuring circuit schematic diagram in the present embodiment, plurality of voltages, multichannel electric current are transformed to the AC signal that is fit to collection through voltage transformer pt, current transformer CT conversion, resistance sampling and capacitor filtering respectively, then to carry out sample conversion in the differential mode input AD conversion chip.
Fig. 6 is F2812 and W5100 hardware interface circuit, by the telecommunication between network chip W5100 realization and the Ethernet.W5100 is the firmware networks chip of WIZnet company up-to-date release in 2006, and it is on the basis of W3150A+, integrated ethernet physical layer RTL8201CP nuclear, so W5100 collection ICP/IP protocol stack, ethernet mac and PHY are one.W5100 supports TCP, UDP, ICMP, IGMP, IPv4, ARP, procotols such as PPPoe, Ethernet; Support 4 independently Socket communications, the transmission of inner 16K byte/reception buffering area can carry out exchanges data fast, and maximum communication rate reaches 25Mbps; Support direct parallel bus interface, parallel general line interface and SPI serial bus interface mode indirectly, can be connected with various single-chip microcomputers or DSP easily.Use W5100 not need to consider the control of Ethernet, only need carry out simple port Socket programming.
Claims (6)
1. based on the electric power system distributed fault wave recording device of DSP, it is characterized in that with the digital signal processor DSP being key control unit, the peripheral module of described digital signal processor DSP comprises: AC sampling module, switching input module, voltage/current signals modulate circuit, zero-crossing detection circuit, data memory module, CAN communication module, RS485 communication module, RS232 communication module, ethernet control module, GPS synchronised clock, real-time clock, switching value output module, power module, indicator light/key-press module and LCD display module;
Voltage/current signals modulate circuit and the tested electrical network coupling of described AC sampling module by being provided with current transformer CT and voltage transformer pt, with described voltage/current signals modulate circuit monitored signal is carried out CT/PT conversion, filtering and voltage division processing successively, signal after the processing is sampled with the multi-disc cascade sampling A AD73360 in the differential mode input AC sampling module, and the sampling dateout of described multi-disc cascade sampling A AD73360 deposits data memory module in by digital signal processor DSP;
Accept to start the control signal of record ripple with described digital signal processor DSP, and start the record ripple; After starting the record ripple, SPI interface by digital signal processor DSP is gone into to store in the SD card by the SDRAM unloading that extends out in the data memory module with fault recorder data, fault recorder data is uploaded to distant place record ripple main website by RS485 bus or Ethernet, is with the mutual cascade of CAN interface between each wave recording device.
2. the electric power system distributed fault wave recording device based on DSP according to claim 1, it is characterized in that when not starting the record ripple described digital signal processor DSP is updated in A segment data buffer area among the described SDRAM of extending out according to sample rate s1 with image data; After the record ripple started, described digital signal processor DSP deposited sampled data in the address space that follows closely behind the A segment data buffer area in according to sample rate s2, and has: s2＞s1; As main wave recording device, be detected all the other each wave recording devices are controlled in the back by described main wave recording device sample frequency with the wave recording device that inserts fault-signal at fault condition.
3. the electric power system distributed fault wave recording device based on DSP according to claim 1, it is characterized in that the cascade sampling A AD73360 in the described AC sampling module is connected with the high-speed synchronous buffer interface McBSP of digital signal processor DSP, the FIFO that McBSP is set is effective, data from described DSP receive path will be carried out stack formula buffer memory, data in buffer is after reaching the value of setting, described DSP takes data in buffer away with interrupt mode, finishes sampled data and receives.
4. the electric power system distributed fault wave recording device based on DSP according to claim 1 is characterized in that the GPIOF input/output interface of described data signal processor DSP is configured to respectively be used for the functional interface of RS232, RS485 bus communication and CAN bus communication.
5. the electric power system distributed fault wave recording device based on DSP according to claim 1, it is characterized in that described ethernet control module adopts the W5100 network chip, the respective pins of described W5100 network chip is connected with control line CB with address wire AB, the data wire DB of described digital signal processor DSP respectively.
6. the electric power system distributed fault wave recording device based on DSP according to claim 1, it is characterized in that between described each wave recording device, adopting synchronized sampling based on the GPS navigation system, after arbitrary wave recording device satisfies record ripple starting criterion, with each wave recording device of start dialing signal synchronous initiation.
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Application publication date: 20100714 |