CN101777507A - Random test method for complexly controlled chips - Google Patents
Random test method for complexly controlled chips Download PDFInfo
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Abstract
The invention discloses a random test method for complexly controlled chips, belonging to the technical field of integrated circuit testing. By fully considering influence factors of random data or transactions, adopting constant constraint conditions and combining a completely random mode and a directionally random mode, the method configures constraint conditions of transaction generation files to realize test verification of complexly controlled chips, namely chips with random constraints. Factors needing to be considered and configuration needing to be realized comprise network structures of the complexly controlled chips, factors influencing generation of random transactions, test platform structures, random generation files of transactions, random generation files of initialization and random generation files of network transmission delay. In the test process within limited time, by adopting the random test method and aiming at known and unknown test spaces of the chips, the invention randomly generates test transaction excitation, thereby greatly saving the labor cost, reducing the verified error probability and expanding the verified test space simultaneously.
Description
Technical field
The present invention relates to the integrated circuit testing field, specifically a kind of random testing method to complexity control class chip.
Background technology
Along with the develop rapidly of IC industry, the performance of integrated circuit and function all constantly promote, and the design complexities of integrated circuit is more and more higher, and this brings unprecedented difficulty with regard to the test of giving chip.The control class chip particularly huge, that function is complicated for logic, huge logical design and complicated functional requirement make test job extremely loaded down with trivial details, and test period is also very very long.Its functional test is the emphasis of design verification work, realize the high coverage rate test, needs great amount of manpower expense and time overhead.
Therefore producing the test affairs at random is to reduce the effective ways of Test Engineer's workload, affairs have a lot of limitation yet the blindness of completely random causes at random, for example, the affairs of random test excitation own are huge, cause the testing time expense huge, the test coverage of several days even tens days is also unsatisfactory.
In sum, complicated control class chip is the function complexity often, and directed test has significant limitation, its function that the unimaginable corner of Test Engineer situation is arranged; And can reach the requirement of test coverage on the completely random theory of testing, but need the test and excitation of huge size, need to consume the insufferable testing time.
Summary of the invention
Technical assignment of the present invention provides a kind of in time-limited test process, adopt random testing method, at the known and unknown test space of chip, produce the excitation of test affairs at random, saved the manpower expense greatly, while also on the basis that the validation failure probability reduces, has enlarged a kind of random testing method to complexity control class chip of the test space of checking.
Technical assignment of the present invention is realized in the following manner, take into full account the factor that influences random data or affairs, adopt fixed constraint condition, completely random and the directed method that combines at random, the constraints of configuration transaction spanned file, complexity that realization is huge to logic, function is complicated control class chip---promptly with the testing authentication of the efficient high coverage rate of the chip of random constraints, thereby shorten the design cycle, reduce design and production cost; Factor of need considering and the configuration that needs to realize comprise: the factor, test platform architecture, affairs that network configuration, the influence of complicated control class chip produces affairs at random be spanned file, initialization spanned file, the Network Transmission spanned file at random of delaying time at random at random.
The network configuration of complicated control class chip, the mode of employing multi-node configuration makes it can cover every protocol function of chip; Considering the factor of the complexity of test coverage and test structure, take rational network configuration configuration, is to finish the assurance that test assignment shortens the testing time.
Influence produces at random, and the factor of affairs comprises: test platform, test affairs, initialization condition, network delay and collision error occurrence condition; Be the realization of configuration file, the generation of affairs is ready at random.
Test platform architecture loads the test affairs that many groups produce at random automatically, and test result is analyzed, and coverage rate is added up; Thereby realized test efficiently.
Affairs spanned file at random consider from complexity control class chip functions, and completely random or orientation produce one group or organize things sequence at random at random.
Initialization is spanned file at random, and completely random generates all parameter conditions of complicated control class chip initiation.
The Network Transmission that the network delay program produces the excitation of the affairs at random spanned file at random of delaying time, Network Transmission delay time spanned file completely random at random or the directed time-delay that produces each channel in the complicated control class chip network configuration at random, the network delay program adopts channel to enumerate the method for transmission path.
A kind of random testing method to complexity control class chip of the present invention is compared with traditional orientation test, at aspects such as testing efficiency and coverage rates many advantages is arranged all, has the following advantages:
1, the characteristic in extend testing space mainly is meant by random device to produce test and excitation, finds the directed corner condition that does not detect, and makes the test coverage maximization;
2, the method for testing of band random constraints has efficiently realized the function coverage of complicated control class chip; Thereby, have good value for applications.
Description of drawings
The present invention is further described below in conjunction with accompanying drawing.
Accompanying drawing 1 is the network configuration that a kind of complexity of complexity being controlled the random testing method of class chip is controlled the class chip;
Accompanying drawing 2 is a kind of test platform architecture schematic block diagram of complexity being controlled the random testing method of class chip;
Accompanying drawing 3 is that a kind of excitation of affairs at random of complexity being controlled the random testing method of class chip produces schematic diagram;
Accompanying drawing 4 is enumerated schematic diagram for a kind of channel of the random testing method to complexity control class chip.
Embodiment
Explain below with reference to Figure of description and specific embodiment a kind of random testing method to complexity control class chip of the present invention being done.
Embodiment:
A kind of random testing method of the present invention to complexity control class chip, take into full account the factor that influences random data or affairs, adopt fixed constraint condition, completely random and the directed method that combines at random, the constraints of configuration transaction spanned file, complexity that realization is huge to logic, function is complicated control class chip---promptly with the testing authentication of the efficient high coverage rate of the chip of random constraints, thereby shorten the design cycle, reduce design and production cost; Factor of need considering and the configuration that needs to realize comprise: the factor, test platform architecture, affairs that network configuration, the influence of complicated control class chip produces affairs at random be spanned file, initialization spanned file, the Network Transmission spanned file at random of delaying time at random at random.
The network configuration of complicated control class chip, the mode of employing multi-node configuration makes it can cover every protocol function of chip; Considering the factor of the complexity of test coverage and test structure, take rational network configuration configuration, is to finish the assurance that test assignment shortens the testing time.
Influence produces at random, and the factor of affairs comprises: test platform, test affairs, initialization condition, network delay and collision error occurrence condition; Be the realization of configuration file, the generation of affairs is ready at random.
Test platform architecture loads the test affairs that many groups produce at random automatically, and test result is analyzed, and coverage rate is added up; Thereby realized test efficiently.
Affairs spanned file at random consider from complexity control class chip functions, and completely random or orientation produce one group or organize things sequence at random at random.
Initialization is spanned file at random, and completely random generates all parameter conditions of complicated control class chip initiation.
The Network Transmission that the network delay program produces the excitation of the affairs at random spanned file at random of delaying time, Network Transmission delay time spanned file completely random at random or the directed time-delay that produces each channel in the complicated control class chip network configuration at random, the network delay program adopts channel to enumerate the method for transmission path.
The network configuration of complicated control class chip as shown in Figure 1, control chip C is responsible in the network read-write operation between four or a plurality of node and other nodes, constitute huge network configuration by many groups of such textural associations, bear the access control of processor in the high-performance architecture, storage, IO etc.Control chip in such huge network structure is tested, needed the factor of consideration a lot, because the 26S Proteasome Structure and Function complexity of this class chip, logic is huge.Therefore except the orientation test, random testing method is absolutely necessary.
The test factor that needs to consider in the random test of complicated control class chip mainly comprises: 1, test platform architecture, 2, affairs excitation generation strategy at random, 3, network configuration configuration and system initialization, 4, the Network Transmission time-delay, 5, the random constraints condition.
The test platform architecture schematic diagram as shown in Figure 2, the affairs excitation that produces at random is loaded in the Control Network, after simulation, analog result is analyzed comparison, and the statistical test coverage rate.The affairs excitation that produces at random comprises a plurality of files, as: read-write affairs file1, system initialization file2, Network Transmission time-delay file3 etc., their generative process as shown in Figure 3, random file generates test and excitation through compiling, operation, is loaded into and carries out simulation test in the test structure.
Read-write affairs excitation generator produces the read-write transaction file of affairs excitation at random, because read-write operation is the primary condition of test, for maximized extend testing space, needs this program can generate various operative combination.Need to consider the generation at random of other necessary conditions of read-write operation in addition, for example, operation zero-time, running node, operation address, operand or the like.The order of supposing read-write operation is respectively Rd_ccommand1, Rd_command2, Rd_command3 and Wr_command1, Wr_command2, node is node (0), node (1) in the network configuration ... node (n-1), operation address is address1, address2 ... operand is a random number, can select above operational elements at random by random function, generate test stimulus file, for example generate at random:
trans_time
Rd_command2
node(1)
address2
ff…ff
In addition, also can design the multiple network structure and carry out random test.
In condition at random, the covering efficient that can cover by analytic function, physical characteristic in the network configuration (comprising quantity, position etc.), factors such as read write command number of combinations retrain the quantity of affairs at random.Can be by analyzing the characteristic that affairs take place, the zero-time of constraint read-write affairs.Can be according to the requirement of test, the constraint manipulation address is the full address simulation, or the single-address simulation.Can determine different test constraint strategies according to different testing requirements in a word.
The initialize routine of network configuration and system produces the starter system condition of test, need be under the condition of understanding each system parameters, and the utilization random function generates the possible random value of each system parameters at random.Can be quantitative values or orientation values also simultaneously, produce some test scene excitation file at random by retraining certain or some system parameterss.
The Network Transmission that the network delay program produces the excitation of the affairs at random spanned file at random of delaying time, because the setting of network delay is the key factor of control operation conflict, therefore condition imposes restriction in the random test for convenience, make that each channel time delay has controllability in the network, and the otherness of each bar channel time delay of the overall situation in the consideration real system, the network delay program adopts channel to enumerate the method for transmission path, as shown in Figure 4, suppose to have n node (node (0), node (1) ... node (n-1)), channel has i type of (channel (1) in the system, channel (2), channel (i)), the possible path of every kind of channel:
p(i)＝(n-1)+(n-2)+(n-3)+…+[n-(n-1)]
Global channel total path quantity is:
In the network delay program, call random function, generate each channel random number (r1, r2 ... ri), generate the random delay of every kind of each paths of channel simultaneously
, this has realized overall i kind channel with regard to stratified,
Paths enumerate random delay.
In condition at random, can take multiple randomized policy according to the requirement of systemic-function and the analysis of test, the generation of constraint arbitrary excitation.For example, need to test certain conflict in the test, need to increase the time-delay of channel i, reduce the time-delay of channel i-1, just can realize easily by the randomized policy of revising channel random number ri and r (i-1).Certainly, the random test of this band random constraints, the also quantitatively time-delay of each each paths of channel realizes directed test.
Except that the described technical characterictic of specification, be the known technology of those skilled in the art.
Claims (7)
1. random testing method to complexity control class chip, it is characterized in that taking into full account the factor that influences random data or affairs, adopt fixed constraint condition, completely random and the directed method that combines at random, the constraints of configuration transaction spanned file, realize complexity control class chip---promptly with the testing authentication of the chip of random constraints; Factor of need considering and the configuration that needs to realize comprise: the factor, test platform architecture, affairs that network configuration, the influence of complicated control class chip produces affairs at random be spanned file, initialization spanned file, the Network Transmission spanned file at random of delaying time at random at random.
2. a kind of random testing method to complexity control class chip according to claim 1 is characterized in that the complicated network configuration of controlling the class chip, adopts the mode of multi-node configuration, makes it can cover every protocol function of chip.
3. a kind of random testing method to complexity control class chip according to claim 1 is characterized in that influencing and produces at random that the factor of affairs comprises: test platform, test affairs, initialization condition, network delay and collision error occurrence condition.
4. a kind of random testing method to complexity control class chip according to claim 1 is characterized in that test platform architecture, loads the test affairs that many groups produce at random automatically, and test result is analyzed, and coverage rate is added up.
5. a kind of random testing method according to claim 1 to complexity control class chip, it is characterized in that affairs at random spanned file consider that from complexity control class chip functions completely random or orientation produce one group or organize things sequence at random at random.
6. a kind of random testing method to complexity control class chip according to claim 1 is characterized in that initialization spanned file at random, and completely random generates all parameter conditions of complicated control class chip initiation.
7. a kind of random testing method according to claim 1 to complexity control class chip, it is characterized in that Network Transmission that the network delay program produces the excitation of the affairs at random spanned file at random of delaying time, Network Transmission delay time spanned file completely random at random or the directed time-delay that produces each channel in the complicated control class chip network configuration at random, the network delay program adopts channel to enumerate the method for transmission path.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102542088A (en) * | 2010-12-27 | 2012-07-04 | 北京国睿中数科技股份有限公司 | Coverage ratio driven random authentication method |
| CN105301480A (en) * | 2015-11-19 | 2016-02-03 | 四川和芯微电子股份有限公司 | Test method of SOC chip |
| CN115168241A (en) * | 2022-09-08 | 2022-10-11 | 济南新语软件科技有限公司 | Test method and system based on combined function coverage rate |
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2010
- 2010-01-04 CN CN201010011309A patent/CN101777507A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102542088A (en) * | 2010-12-27 | 2012-07-04 | 北京国睿中数科技股份有限公司 | Coverage ratio driven random authentication method |
| CN102542088B (en) * | 2010-12-27 | 2014-03-12 | 北京国睿中数科技股份有限公司 | Coverage ratio driven random authentication method |
| CN105301480A (en) * | 2015-11-19 | 2016-02-03 | 四川和芯微电子股份有限公司 | Test method of SOC chip |
| CN115168241A (en) * | 2022-09-08 | 2022-10-11 | 济南新语软件科技有限公司 | Test method and system based on combined function coverage rate |
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Application publication date: 20100714 |