CN101777011B - Method of firmware address space application - Google Patents
Method of firmware address space application Download PDFInfo
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- CN101777011B CN101777011B CN 201010112038 CN201010112038A CN101777011B CN 101777011 B CN101777011 B CN 101777011B CN 201010112038 CN201010112038 CN 201010112038 CN 201010112038 A CN201010112038 A CN 201010112038A CN 101777011 B CN101777011 B CN 101777011B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000013507 mapping Methods 0.000 claims description 8
- 238000012986 modification Methods 0.000 claims description 2
- 230000004048 modification Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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Abstract
The invention provides a method of a firmware address space application, which comprises the following steps: when the system is initialized, the firmware address space which is mapped to a CPU is divided into a BIOS mirror image storage space and a private space. The method can enlarge the functions of the system, can improve the reliability and the usability of the system, and has promising application prospect.
Description
Technical field
The present invention relates to the high-performance computer field, be specifically related to the method for a kind of design firmware (Firmware) address space and the reliability of the high-performance computer realized based on this method, availability and towards the application of different field.
Background technology
High-performance computer is the important basis for IT application facility of the class in crucial application, especially can satisfy the demand in finance, telecommunications etc. field, propose very high requirement in these fields for the processing power to high-performance computer, but meanwhile high reliability, the high availability of high-performance computer also proposed very high requirement.
Therefore, reliability, the availability of raising high-performance computer become the most urgent demand.
Summary of the invention
The technical problem to be solved in the present invention is, proposes the method that a kind of firmware (Firmware) address space is used, and function that can extension system can improve reliability, the availability of system, has boundless application prospect.
In order to solve the problems of the technologies described above, the present invention proposes a kind of method that firmware address space is used, it is characterized in that, comprising:
System is divided into a BIOS mirrored storage space and a private room with firmware (Firmware) address space that is mapped to CPU when initialization.
Further, said method also can have following characteristics:
Described BIOS mirrored storage space is greater than or equal to the size of the BIOS mirror image that needs storage.
Further, said method also can have following characteristics:
System is in the operation BIOS stage, by modification source address code translator, the Firmware address space that is mapped to CPU is divided.
Further, said method also can have following characteristics:
To the described BIOS mirrored storage of major general spatial mappings to CPU.
Further, said method also can have following characteristics:
The mapping relations of described private room can be revised in the operation BIOS stage by system by revising the source address code translator, described private room is mapped on CPU and/or other equipment.
Further, said method also can have following characteristics:
Under operating system, described private room is managed.
Further, said method also can have following characteristics:
Described system comprises several CPU, and each CPU connects a BIOS mirror image.
Further, said method also can have following characteristics:
System when initialization, described several CPU of parallel initialization.
Further, said method also can have following characteristics:
Under the Anthem framework, system is that CPU distributes the Firmware address space of 16MB when initialization, and wherein 8MB address space is divided into described BIOS mirrored storage space, and remaining 8MB address space is divided into described private room.
The method that a kind of firmware address space that the present invention proposes is used, by planning dexterously the Firmware address space, thereby function that can extension system improves reliability, the availability of system, especially for the large scale system successful, has boundless application prospect.
Description of drawings
Fig. 1 is a kind of firmware address space application process of embodiment of the present invention process flow diagram;
Fig. 2 is the application process schematic diagram of traditional 16MB Firmware address space;
Fig. 3 is the example schematic that the present invention uses 16MB Firmware address space.
Embodiment
Below in conjunction with drawings and Examples, technical scheme of the present invention is described in detail.
Need to prove, if do not conflict, each feature in the embodiment of the present invention and embodiment can mutually combine, all within protection scope of the present invention.In addition, can carry out in the computer system such as one group of computer executable instructions in the step shown in the process flow diagram of accompanying drawing, and, although there is shown logical order in flow process, but in some cases, can carry out step shown or that describe with the order that is different from herein.
Referring to Fig. 1, the figure shows the method that the embodiment of the present invention is used the Firmware address space, comprise step:
Step S101: system begins initialization after powering on, and is its mapping Firmware address space by the CPU internal code;
After the Standby power supply electrifying finished, system namely began initial work, and this stage, configuration Firmware address space was to CPU, as shown in Figure 2 mainly by its Firmware address space of CPU internal code initialization.
In this system, the BIOS mirror image is direct-connected to CPU by spi bus.
When having a plurality of CPU in system, each CPU directly connects a BIOS mirror image, and described a plurality of CPU can parallel initialization.
Step S102: system by revising the source address code translator, is divided into a BIOS mirrored storage space and a private room with the Firmware address space that is mapped to CPU in the operation BIOS stage;
When the Firmware address space that is mapped to CPU is divided, need to consider the size of BIOS mirror image, the BIOS mirrored storage space of guaranteeing to mark off is greater than or equals BIOS mirror image size.Can also revise as required the mapping relations of described private room by revising the source address code translator, for example, described private room can be mapped on other equipment, that is, and with the private room of described private room as described other equipment; Perhaps with described private room part mapping to CPU, part mapping is to other equipment, that is, with the private room of described private room part as CPU, part is as the private room of described other equipment.For example, under the Anthem framework, the Firmware address space is 16MB, and BIOS mirror image size is 8MB, and the low 8MB that can configure 16MB Firmware address space is the private address space, as shown in Figure 3.
Described private room can be used according to specific needs, for example, and can storage system mistake Site Survey Table.
Step S103:BIOS collects whole system Address space mappinD table (comprising the Firmware address space) in operational process, thereby completes distribution and the topology of whole system resource;
Step S104:BIOS continues to complete the initialization action of whole system, and the Boot Loader that control is given operating system (OS) is to complete final start-up course;
Step S 105: can use the private address space in the Firmware address space under OS.
Described Firmware address space can be mapped completely on CPU, as depositing the BIOS mirror image, also can shine upon part Firmware address space to CPU, as depositing the BIOS mirror image, remainder Firmware address space can be mapped to CPU and upward and/or on other equipment use as private room.
Certainly; the present invention also can have other various embodiments; in the situation that do not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (8)
1. the method that firmware address space is used, is characterized in that, comprising:
System is divided into a BIOS mirrored storage space and a private room with the firmware Firmware address space that is mapped to CPU when initialization; Wherein, system is in the operation BIOS stage, by modification source address code translator, the Firmware address space that is mapped to CPU is divided;
BIOS collects whole system Address space mappinD table in operational process, comprise the Firmware address space, thereby complete distribution and the topology of whole system resource;
BIOS continues to complete the initialization action of whole system, and the Boot Loader that control is given operating system OS is to complete final start-up course;
Use the private room in the Firmware address space under OS.
2. the method for claim 1 is characterized in that:
Described BIOS mirrored storage space is greater than or equal to the size of the BIOS mirror image that needs storage.
3. the method for claim 1 is characterized in that:
To the described BIOS mirrored storage of major general spatial mappings to CPU.
4. method as claimed in claim 3 is characterized in that:
The mapping relations of described private room can be revised in the operation BIOS stage by system by revising the source address code translator, described private room is mapped on CPU and/or other equipment.
5. method as described in any one in claim 1-4 is characterized in that:
Under operating system, described private room is managed.
6. the method for claim 1 is characterized in that:
Described system comprises several CPU, and each CPU connects a BIOS mirror image.
7. method as claimed in claim 6 is characterized in that:
System when initialization, described several CPU of parallel initialization.
8. method as claimed in claim 2 is characterized in that:
Under the Anthem framework, system is that CPU distributes the Firmware address space of 16MB when initialization, and wherein 8MB address space is divided into described BIOS mirrored storage space, and remaining 8MB address space is divided into described private room.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010112038 CN101777011B (en) | 2010-02-11 | 2010-02-11 | Method of firmware address space application |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010112038 CN101777011B (en) | 2010-02-11 | 2010-02-11 | Method of firmware address space application |
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| CN101777011A CN101777011A (en) | 2010-07-14 |
| CN101777011B true CN101777011B (en) | 2013-06-19 |
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| CN 201010112038 Active CN101777011B (en) | 2010-02-11 | 2010-02-11 | Method of firmware address space application |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201054133Y (en) * | 2007-01-31 | 2008-04-30 | 孙武源 | Main board with hard disk data protection and recovery function |
| CN101609406A (en) * | 2009-07-17 | 2009-12-23 | 浪潮电子信息产业股份有限公司 | A kind of method of multi-BIOS mapping parallel initialization |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7032108B2 (en) * | 2003-05-02 | 2006-04-18 | Egenera, Inc. | System and method for virtualizing basic input/output system (BIOS) including BIOS run time services |
| US7392172B2 (en) * | 2005-04-28 | 2008-06-24 | Hewlett-Packard Development Company, L.P. | Providing virtual device access via firmware |
-
2010
- 2010-02-11 CN CN 201010112038 patent/CN101777011B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201054133Y (en) * | 2007-01-31 | 2008-04-30 | 孙武源 | Main board with hard disk data protection and recovery function |
| CN101609406A (en) * | 2009-07-17 | 2009-12-23 | 浪潮电子信息产业股份有限公司 | A kind of method of multi-BIOS mapping parallel initialization |
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| CN101777011A (en) | 2010-07-14 |
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Effective date of registration: 20201111 Address after: 215100 No. 1 Guanpu Road, Guoxiang Street, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province Patentee after: SUZHOU LANGCHAO INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: 100085 Beijing, Haidian District on the road to information on the ground floor, building 2-1, No. 1, C Patentee before: Inspur (Beijing) Electronic Information Industry Co.,Ltd. |