CN101771420A - Method for designing ROM in decoder and decoder - Google Patents
Method for designing ROM in decoder and decoder Download PDFInfo
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- CN101771420A CN101771420A CN200810246879A CN200810246879A CN101771420A CN 101771420 A CN101771420 A CN 101771420A CN 200810246879 A CN200810246879 A CN 200810246879A CN 200810246879 A CN200810246879 A CN 200810246879A CN 101771420 A CN101771420 A CN 101771420A
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Abstract
The invention provides a method for designing a read only memory (ROM) in a decoder, which includes the following steps: the address data to be saved in the ROM is classified into regular address data and irregular address data according to preset series rule; attribute lists are set up for the regular address data and irregular address data; the attribute lists and the irregular address data are stored in the ROM, in the decoding process, a ROM controller of the decoder acquires the corresponding address output data according to the preset series rule and the attribute lists and the irregular address data which are saved in the ROM. Through the method, the regular address data and the irregular address data are classified, so only the attribute lists and the irregular address data are saved in the ROM, thereby the area of the chip, which is occupied by the ROM, is effectively reduced, and the manufacturing cost is reduced.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, method for designing and the decoder of ROM in particularly a kind of decoder (Read-only Memory, read-only memory).
Background technology
Usually need a ROM be set at this decoder in the design of decoder cooperates decoder to decode, understand in order to have clearly the present invention, to be that example is simply introduced below with LDPC (Low DensityParity Check Code, low density parity check code) decoder.
The LDPC sign indicating number is to have sparse parity check matrix by the class that Robert doctor G.Gallager proposed in 1963, the superperformance of approaching the Shannon limit is not only arranged, and decoding complexity is lower, and structure is flexible, is the research focus of field of channel coding in recent years.Through research and development for over ten years, the researcher has obtained breakthrough progress in every respect, and the correlation technique of LDPC sign indicating number also reaches its maturity, and has been widely used in fields such as deep space communication, optical fiber communication, satellite digital video and audio broadcasting.At present, the LDPC sign indicating number has become the 4th strong competitor of generation communication system (4G), is adopted by satellite digital video broadcast standard DVB-S2 of future generation based on the encoding scheme of LDPC sign indicating number.
The LDPC sign indicating number is the class linear code by the check matrix definition, for making decoding feasible, when code length is longer, need check matrix to satisfy " sparse property ", be that 1 density is lower in the check matrix, just require in the check matrix 1 the number number much smaller than 0, and code length is long more, and density will be low more.In the process of LDPC decoder decode, the LDPC decoder can solve the data of some, need from the decoded data of its some that solves, select a part of data as decoded result output (being not that decoded data is all exported), so just need a ROM to deposit and select the address accordingly.Wherein, the number of the different corresponding dateouts of code check (rate) can be inequality.
The shortcoming that prior art exists is: ROM is bigger in the current decoder device, has increased area of chip and manufacturing cost.Be example also for example with above-mentioned LDPC decoder, the LDPC decoder solves 9612 decoded datas, and need the decoded result bit number N of output is 4608 bits (rate=1/2) or 6912 bits (rate=3/4), so this LDPC decoder just needs the ROM of (4608+6912) x14bit to preserve the address.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, particularly solves ROM in the prior art decoder and takies technological deficiency than the large chip area.
For achieving the above object, one aspect of the present invention proposes the method for designing of read only memory ROM in a kind of decoder, may further comprise the steps: according to predetermined ordered series of numbers rule the address date that will preserve in described ROM is classified, described address date is divided into regular address data and irregular address data; For described regular address data and irregular address data are set up attribute list; Described attribute list and described irregular address data are deposited among the described ROM, when decoding, the ROM controller of described decoder obtains the corresponding address dateout according to described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data.
An embodiment as said method of the present invention, the ROM controller of described decoder obtains the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises: described ROM controller judges that according to described attribute list its address date that will obtain is regular address data, still irregular address data; If judging its address date that will obtain is regular address data, then described ROM controller calculates corresponding address dateout and output according to described predetermined ordered series of numbers rule; If judging its address date that will obtain is irregular address data, then described ROM controller reads described irregular address data from described ROM, and exports as the address dateout.
As an embodiment of said method of the present invention, described ROM is single port ROM or twoport ROM.
An embodiment as said method of the present invention, when described ROM is single port ROM, the ROM controller of described decoder obtains the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises: described ROM controller reads described attribute list from described ROM, and described ROM controller calculates the corresponding address dateout according to described predetermined ordered series of numbers rule simultaneously; Described ROM control judges that according to the described attribute list that reads its address date that will obtain is regular address data, still irregular address data; If judging its address date that will obtain is regular address data, then described ROM controller is directly with the address dateout output of calculating; If judging its address date that will obtain is irregular address data, then described ROM controller reads described irregular address data again from described ROM, and exports as the address dateout.
An embodiment as said method of the present invention, when described ROM is single port ROM, the ROM controller of described decoder obtains the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises: described ROM controller reads irregular address data from described ROM, and described ROM controller calculates the corresponding address dateout according to described predetermined ordered series of numbers rule simultaneously; Described ROM controller reads described attribute list from described ROM, and judges that according to described attribute list its address date that will obtain is regular address data, still irregular address data; If judging its address date that will obtain is regular address data, then described ROM controller is directly with the address dateout output of calculating; If judging its address date that will obtain is irregular address data, the described irregular address data that then described ROM controller directly will read are exported as the address dateout.
As an embodiment of said method of the present invention, described ROM controller reads described attribute list with ping-pong operation.
An embodiment as said method of the present invention, when described ROM is twoport ROM, the ROM controller of described decoder obtains the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises: described ROM controller reads the described attribute list of preserving the described ROM from an address mouth, described ROM controller reads irregular address data corresponding the described ROM from another address mouth, and calculates the corresponding address dateout according to described predetermined ordered series of numbers rule simultaneously; Described ROM controller judges that according to described attribute list its address date that will obtain is regular address data, still irregular address data; If judging its address date that will obtain is regular address data, then described ROM controller is directly with the address dateout output of calculating; If judging its address date that will obtain is irregular address data, the described irregular address data that then described ROM controller directly will read are exported as the address dateout.
As an embodiment of said method of the present invention, described decoder is a low density parity check code LDPC decoder.
The present invention has also proposed a kind of decoder on the other hand, comprise ROM, ROM controller and processor, described processor, being used to decode obtains decoded data, and selects corresponding decoded result output according to the address dateout that described ROM controller obtains from described decoded data; Described ROM, be used to preserve attribute list and irregular address data, it is regular address data or irregular address data that described attribute list is used to identify the address date that described ROM controller will obtain, and wherein said regular address data and described irregular address data are divided according to predetermined ordered series of numbers rule; Described ROM controller is used for when described decoder decode, and according to described predetermined ordered series of numbers rule, described attribute list of preserving among the described ROM and described irregular address data are obtained the corresponding address dateout.
An embodiment as the above-mentioned decoder of the present invention, described ROM controller at first judges that according to described attribute list its address date that will obtain is regular address data or irregular address data, if judging its address date that will obtain is regular address data, then calculate the corresponding address dateout and export to described processor according to described predetermined ordered series of numbers rule, otherwise, if judging its address date that will obtain is irregular address data, then from described ROM, read described irregular address data, and export to described processor as the address dateout.
As an embodiment of the above-mentioned decoder of the present invention, described ROM is single port ROM or twoport ROM.
An embodiment as the above-mentioned decoder of the present invention, when described ROM is single port ROM, described ROM controller is when reading described attribute list from described ROM, also calculate the corresponding address dateout according to described predetermined ordered series of numbers rule, afterwards, described ROM controller judges that according to the described attribute list that reads its address date that will obtain is regular address data or irregular address data, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, then from described ROM, read described irregular address data again, and export as the address dateout.
An embodiment as the above-mentioned decoder of the present invention, when described ROM is single port ROM, described ROM controller reads irregular address data from described ROM when, also calculate the corresponding address dateout according to described predetermined ordered series of numbers rule, afterwards, from described ROM, read described attribute list, and judge that according to described attribute list its address date that will obtain is regular address data or irregular address data, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, the described irregular address data that then directly will read are exported as the address dateout.
As an embodiment of the above-mentioned decoder of the present invention, described ROM controller reads described attribute list with ping-pong operation.
An embodiment as the above-mentioned decoder of the present invention, when described ROM is twoport ROM, described ROM controller reads the described attribute list preserved the described ROM and corresponding irregular address data respectively from two address mouths when, also calculate the corresponding address dateout according to described predetermined ordered series of numbers rule, judge that according to described attribute list its address date that will obtain is regular address data or irregular address data afterwards, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, the described irregular address data that then directly will read are exported as the address dateout.
As an embodiment of the above-mentioned decoder of the present invention, described decoder is the LDPC decoder.
Further aspect of the present invention has also proposed a kind of ROM of decoder, described ROM comprises first memory block and second memory block, described first memory block, be used to preserve attribute list, it is regular address data or irregular address data that described attribute list is used to identify the address date that described ROM controller will obtain, and wherein said regular address data and described irregular address data are divided according to predetermined ordered series of numbers rule; Described second memory block is used to preserve irregular address data.
As the embodiment of the above-mentioned decoder ROM of the present invention, described decoder is the LDPC decoder.
The present invention is by the division to regular address data and irregular address data, make and only preserve attribute list among the ROM and irregular address data get final product, regular address data can be calculated according to predetermined ordered series of numbers rule by the ROM controller, thereby can effectively reduce the shared chip area of ROM, reduce manufacturing cost.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the method for designing flow chart of ROM in the embodiment of the invention decoder;
Fig. 2 is that ROM home address Data Matching is optimized schematic diagram in the LDPC decoder;
The decoder schematic diagram that Fig. 3 designs for the method according to this invention with single port ROM;
The decoder schematic diagram that Fig. 4 designs for the method according to this invention with twoport ROM;
Fig. 5 is a kind of address dateout method flow diagram that obtains in the embodiment of the invention;
Fig. 6 obtains address dateout method flow diagram during for a kind of single port ROM in the embodiment of the invention;
Fig. 7 obtains address dateout method flow diagram during for the another kind of single port ROM in the embodiment of the invention;
Fig. 8 obtains address dateout method flow diagram during for a kind of twoport ROM in the embodiment of the invention;
Fig. 9 is the decoder architecture figure of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
The present invention is that mainly the address of will preserve among the prior art ROM is divided into regular address data and irregular address data, regular address data can be calculated according to predetermined ordered series of numbers rule by the ROM controller, therefore ROM only need preserve attribute list and irregular address data get final product in the present invention, thereby can reduce the area of ROM greatly.As one embodiment of the present of invention, can divide regular address data and irregular address data according to predetermined ordered series of numbers rule, certainly the predetermined ordered series of numbers rule of its selection for different decoders may be different, following examples will be that example is described with the LDPC decoder, the predetermined ordered series of numbers rule of other decoder correspondences can be provided with reference to following embodiment, below just introduce no longer in detail.But need to prove, below be that example is introduced with the LDPC decoder be in order to make the present invention clearer, is not that the present invention can only be applied to the LDPC decoder.
As shown in Figure 1, be the method for designing flow chart of ROM in the embodiment of the invention decoder, this embodiment is that example is described with the LDPC decoder, may further comprise the steps:
Step S101 classifies to the address date that will preserve in ROM according to predetermined ordered series of numbers rule, and address date is divided into regular address data and irregular address data.With the LDPC decoder is example, and the address date of preserving among its ROM is clocklike, can distinguish according to certain ordered series of numbers rule.Wherein, the present invention's ordered series of numbers rule described herein can adopt a variety of modes, for example can compare by address date and a certain ascending series that will preserve among the ROM, find their corresponding relation, if address numerical value of preserving among the ROM and a certain ascending series coupling, illustrate that then this address numerical value is regular address data, otherwise unmatched words are irregular address data just.The address date of for example preserving in ROM is 201,202,500,204,205,206,555,208 etc., and the ascending series of selecting is 1,2,3,4,5,6,7,8 since 201, we as can be seen among the ROM the 3rd address date and the 7th address date be irregular address data, remaining is regular address data.What need once more to stress is; the different technical staff in this area may select different ordered series of numbers rules; different decoders may also can be to there being different ordered series of numbers rules; can't discuss one by one at this; but main thought of the present invention is the division by regular and irregular address data; thereby reduce the shared area of ROM; how a variety of modes have been divided by the ordered series of numbers rule; can only describe by way of example at this, but other dividing mode also all should be included within protection scope of the present invention.
Be that example is described with the LDPC decoder below, specifically can be simultaneously referring to accompanying drawing 2, Fig. 2 is that ROM home address Data Matching is optimized schematic diagram in the LDPC decoder.With code check is 1/2 to be example, meet this ordered series of numbers that increases progressively since 4609: 4609,4610.....4019 in this ordered series of numbers the inside, wherein some number is the progressive law that does not meet this ordered series of numbers, belongs to irregular number.4608 address dates of needs output are divided into data that meet the ordered series of numbers progressive law and the data that do not meet the ordered series of numbers progressive law.Need to prove that what select in this embodiment is ascending series, and the step-length that at every turn increases progressively is 1, also can selects decreasing sequence of numbers certainly, perhaps variation is made in the compensation of each increasing or decreasing.It is the same when code check is 3/4.But meet this ordered series of numbers clocklike that increases progressively since 2305,2305,2306,2307...... is in this ordered series of numbers the inside, and wherein some number is the progressive law that does not meet this ordered series of numbers, belongs to irregular address date (specifically can referring to Fig. 2).
Step S102 is for regular address data and irregular address data are set up attribute list.As one embodiment of the present of invention, simultaneously with reference to figure 2, the present invention can ordered series of numbers increases progressively and this attribute that do not meet the ordered series of numbers progressive law is encoded to meeting, as the regular address data that meet the ordered series of numbers progressive law being represented that with 1 irregular address data are represented with 0.Regular address data can be represented with 0 that equally also irregular address data are represented with 1, perhaps set up this attribute list with other modes.
Step S103 deposits attribute list and irregular address data among the ROM in.As shown in Figure 3 and Figure 4, decoder schematic diagram for said method design according to the present invention, wherein, Fig. 3 is the decoder schematic diagram with single port ROM of the said method design according to the present invention, and Fig. 4 is the decoder schematic diagram with twoport ROM of the said method design according to the present invention.ROM among Fig. 3 and Fig. 4 comprises first memory block and second memory block.First memory block is used to preserve attribute list, and it is regular address data or irregular address data that this attribute list is used to identify the address date that the ROM controller will obtain.Second memory block is used to preserve irregular address data.
The above-mentioned ROM of design the invention allows for the multiple method of obtaining the address dateout according to the present invention, below will be described in the mode of specific embodiment.
As shown in Figure 5, a kind of address dateout method flow diagram that obtains in the embodiment of the invention may further comprise the steps:
Step S501, the ROM controller reads the attribute list of its preservation from ROM.
Step S502, ROM control judges that according to attribute list its address date that will obtain is regular address data, still irregular address data.
Step S503, if judge that the address date that ROM control will be obtained is regular address data, then the ROM controller calculates corresponding address dateout and output according to predetermined ordered series of numbers rule.For example among Fig. 2, the ROM controller can obtain 4612 (code check is) at 1/2 o'clock according to 1412 through certain calculation, wherein above-mentioned operation method is also very many, and for example direct difference addition that ascending series and both of correspondence are preset also can realize by other modes certainly.
Step S504 is irregular address data if judge its address date that will obtain, and then the ROM controller reads irregular address data from ROM, and exports as the address dateout.
In order to improve processing speed, the invention allows for several parallel processing method, see following examples, can be in different ways for single port ROM and twoport ROM the present invention.But what also need to illustrate once more is that these embodiment only are preferred embodiment, are not that the present invention only can realize by following embodiment.
As shown in Figure 6, obtain address dateout method flow diagram during for a kind of single port ROM in the embodiment of the invention, may further comprise the steps:
Step S601, the ROM controller reads described attribute list from ROM, and the ROM controller calculates the corresponding address dateout according to predetermined ordered series of numbers rule simultaneously.
Step S602, ROM control judges that according to the attribute list that reads its address date that will obtain is regular address data, still irregular address data.
Step S603 is regular address data if judge its address date that will obtain, and then the ROM controller is directly with the address dateout output of calculating.
Step S604 is irregular address data if judge its address date that will obtain, and then the ROM controller reads irregular address data again from ROM, and exports as the address dateout.
As shown in Figure 7, obtain address dateout method flow diagram during for the another kind of single port ROM in the embodiment of the invention, may further comprise the steps:
Step S701, ROM controller read irregular address data from ROM, the ROM controller calculates the corresponding address dateout according to predetermined ordered series of numbers rule simultaneously.
Step S702, the ROM controller reads attribute list from ROM.
Step S703, the ROM controller judges that according to attribute list its address date that will obtain is regular address data, still irregular address data.
Step S704 is regular address data if judge its address date that will obtain, and then the ROM controller is directly with the address dateout output of calculating.
Step S705 is irregular address data if judge its address date that will obtain, and then the ROM controller irregular address data that directly will read are exported as the address dateout.
Wherein, preferably, for above-mentioned single port ROM, the ROM controller can ping-pong operation reads the attribute list among the ROM.
As shown in Figure 8, obtain address dateout method flow diagram during for a kind of twoport ROM in the embodiment of the invention, may further comprise the steps:
Step S801, the ROM controller reads the described attribute list of preserving the ROM from an address mouth, and described ROM controller reads irregular address data corresponding the ROM from another address mouth, and calculates the corresponding address dateout according to predetermined ordered series of numbers rule simultaneously.
Step S802, the ROM controller judges that according to attribute list its address date that will obtain is regular address data, still irregular address data.
Step S803 is regular address data if judge its address date that will obtain, and then the ROM controller is directly with the address dateout output of calculating.
Step S804 is irregular address data if judge its address date that will obtain, and then the ROM controller irregular address data that directly will read are exported as the address dateout.
As shown in Figure 9, be the decoder architecture figure of the embodiment of the invention, this decoder 100 comprises ROM110, ROM controller 120 and processor 130.Processor 130 is used to decode and obtains decoded data, and selects corresponding decoded result output according to the address dateout that ROM controller 120 obtains from decoded data.ROM 100 is used to preserve attribute list and irregular address data, wherein, it is regular address data or irregular address data that attribute list is used to identify the address date that ROM controller 200 will obtain, and regular address data and irregular address data are divided according to predetermined ordered series of numbers rule.ROM controller 120 is used for when decoder 100 decodings, and according to predetermined ordered series of numbers rule, the attribute list and the irregular address data of preserving among the ROM 100 are obtained the corresponding address dateout.
As one embodiment of the present of invention, ROM controller 120 at first judges that according to attribute list its address date that will obtain is regular address data or irregular address data, if judging its address date that will obtain is regular address data, then calculate the corresponding address dateout and export to processor 130 according to predetermined ordered series of numbers rule, otherwise, if judging its address date that will obtain is irregular address data, then from ROM 100, read irregular address data, and export to described processor as the address dateout.
Wherein, ROM 100 can be single port ROM or twoport ROM.
As the preferred embodiments of the present invention, when ROM 100 was single port ROM, ROM controller 120 also calculated the corresponding address dateout according to predetermined ordered series of numbers rule reading attribute list from ROM 100 when.Afterwards, ROM controller 120 judges that according to the attribute list that reads its address date that will obtain is regular address data or irregular address data, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, then from ROM 100, read irregular address data again, and export as the address dateout.
As another preferred embodiment of the present invention, when ROM 100 is single port ROM, ROM controller 120 reads irregular address data from ROM 100 when, also calculate the corresponding address dateout according to predetermined ordered series of numbers rule.Afterwards, from ROM 100, read attribute list, and judge that according to attribute list its address date that will obtain is regular address data or irregular address data, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, the irregular address data that then directly will read are exported as the address dateout.
Wherein, more preferably, when ROM 100 was single port ROM, ROM controller 120 can also read attribute list by ping-pong operation, further improves decoding speed.
As another preferred embodiment of the present invention, when ROM 100 is twoport ROM, ROM controller 120 reads the ROM 100 attribute list preserved and corresponding irregular address data respectively from two address mouths when, also calculate the corresponding address dateout according to predetermined ordered series of numbers rule.Judge that according to attribute list its address date that will obtain is regular address data or irregular address data afterwards, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, the irregular address data that then directly will read are exported as the address dateout.
Need to prove; in the above embodiment of the present invention, be that example is described in the LDPC decoder with ROM; but ROM also may be in LDPC decoder outside, and its effect is identical with ROM in the LDPC decoder of the present invention, is also contained within protection scope of the present invention equally.
The present invention is by the division to regular address data and irregular address data, only make among the ROM, regular address data can be calculated according to predetermined ordered series of numbers rule by the ROM controller, thereby can effectively reduce the shared chip area of ROM, reduce manufacturing cost.Be example for example with the LDPC decoder, the capacity of ROM can be reduced to 4653x 14bit from existing 11520x14bit by embodiments of the invention, thereby the present invention can significantly reduce the area of ROM as can be seen, certainly regular address data may be more in other decoders, and the ROM area of its corresponding minimizing is bigger.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (18)
1. the method for designing of read only memory ROM in the decoder is characterized in that, may further comprise the steps:
According to predetermined ordered series of numbers rule the address date that will preserve in described ROM is classified, described address date is divided into regular address data and irregular address data;
For described regular address data and irregular address data are set up attribute list;
Described attribute list and described irregular address data are deposited among the described ROM, when decoding, the ROM controller of described decoder obtains the corresponding address dateout according to described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data.
2. the method for designing of ROM in the decoder as claimed in claim 1, it is characterized in that the ROM controller of described decoder obtains the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises:
Described ROM controller judges that according to described attribute list its address date that will obtain is regular address data, still irregular address data;
If judging its address date that will obtain is regular address data, then described ROM controller calculates corresponding address dateout and output according to described predetermined ordered series of numbers rule;
If judging its address date that will obtain is irregular address data, then described ROM controller reads described irregular address data from described ROM, and exports as the address dateout.
3. the method for designing of ROM is characterized in that in the decoder as claimed in claim 1, and described ROM is single port ROM or twoport ROM.
4. the method for designing of ROM in the decoder as claimed in claim 3, it is characterized in that, when described ROM was single port ROM, the ROM controller of described decoder obtained the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises:
Described ROM controller reads described attribute list from described ROM, described ROM controller calculates the corresponding address dateout according to described predetermined ordered series of numbers rule simultaneously;
Described ROM control judges that according to the described attribute list that reads its address date that will obtain is regular address data, still irregular address data;
If judging its address date that will obtain is regular address data, then described ROM controller is directly with the address dateout output of calculating;
If judging its address date that will obtain is irregular address data, then described ROM controller reads described irregular address data again from described ROM, and exports as the address dateout.
5. the method for designing of ROM in the decoder as claimed in claim 3, it is characterized in that, when described ROM was single port ROM, the ROM controller of described decoder obtained the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises:
Described ROM controller reads irregular address data from described ROM, described ROM controller calculates the corresponding address dateout according to described predetermined ordered series of numbers rule simultaneously;
Described ROM controller reads described attribute list from described ROM, and judges that according to described attribute list its address date that will obtain is regular address data, still irregular address data;
If judging its address date that will obtain is regular address data, then described ROM controller is directly with the address dateout output of calculating;
If judging its address date that will obtain is irregular address data, the described irregular address data that then described ROM controller directly will read are exported as the address dateout.
6. as the method for designing of ROM in claim 4 or the 5 described decoders, it is characterized in that described ROM controller reads described attribute list with ping-pong operation.
7. the method for designing of ROM in the decoder as claimed in claim 3, it is characterized in that, when described ROM was twoport ROM, the ROM controller of described decoder obtained the corresponding address dateout according to the described attribute list of preserving among described predetermined ordered series of numbers rule, the described ROM and described irregular address data and specifically comprises:
Described ROM controller reads the described attribute list of preserving the described ROM from an address mouth, described ROM controller reads irregular address data corresponding the described ROM from another address mouth, and calculates the corresponding address dateout according to described predetermined ordered series of numbers rule simultaneously;
Described ROM controller judges that according to described attribute list its address date that will obtain is regular address data, still irregular address data;
If judging its address date that will obtain is regular address data, then described ROM controller is directly with the address dateout output of calculating;
If judging its address date that will obtain is irregular address data, the described irregular address data that then described ROM controller directly will read are exported as the address dateout.
8. the method for designing of ROM is characterized in that in the decoder as claimed in claim 1, and described decoder is a low density parity check code LDPC decoder.
9. a decoder is characterized in that, comprises ROM, ROM controller and processor,
Described processor, being used to decode obtains decoded data, and selects corresponding decoded result output according to the address dateout that described ROM controller obtains from described decoded data;
Described ROM, be used to preserve attribute list and irregular address data, it is regular address data or irregular address data that described attribute list is used to identify the address date that described ROM controller will obtain, and wherein said regular address data and described irregular address data are divided according to predetermined ordered series of numbers rule;
Described ROM controller is used for when described decoder decode, and according to described predetermined ordered series of numbers rule, described attribute list of preserving among the described ROM and described irregular address data are obtained the corresponding address dateout.
10. decoder as claimed in claim 9, it is characterized in that, described ROM controller at first judges that according to described attribute list its address date that will obtain is regular address data or irregular address data, if judging its address date that will obtain is regular address data, then calculate the corresponding address dateout and export to described processor according to described predetermined ordered series of numbers rule, otherwise, if judging its address date that will obtain is irregular address data, then from described ROM, read described irregular address data, and export to described processor as the address dateout.
11. decoder as claimed in claim 9 is characterized in that, described ROM is single port ROM or twoport ROM.
12. decoder as claimed in claim 11, it is characterized in that, when described ROM is single port ROM, described ROM controller is when reading described attribute list from described ROM, also calculate the corresponding address dateout according to described predetermined ordered series of numbers rule, afterwards, described ROM controller judges that according to the described attribute list that reads its address date that will obtain is regular address data or irregular address data, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, then from described ROM, read described irregular address data again, and export as the address dateout.
13. decoder as claimed in claim 11, it is characterized in that, when described ROM is single port ROM, described ROM controller reads irregular address data from described ROM when, also calculate the corresponding address dateout according to described predetermined ordered series of numbers rule, afterwards, from described ROM, read described attribute list, and judge that according to described attribute list its address date that will obtain is regular address data or irregular address data, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, the described irregular address data that then directly will read are exported as the address dateout.
14., it is characterized in that described ROM controller reads described attribute list with ping-pong operation as claim 12 or 13 described decoders.
15. decoder as claimed in claim 11, it is characterized in that, when described ROM is twoport ROM, described ROM controller reads the described attribute list preserved the described ROM and corresponding irregular address data respectively from two address mouths when, also calculate the corresponding address dateout according to described predetermined ordered series of numbers rule, judge that according to described attribute list its address date that will obtain is regular address data or irregular address data afterwards, if judge it is regular address data, then directly with the address dateout output of calculating, if judge it is irregular address data, the described irregular address data that then directly will read are exported as the address dateout.
16. decoder as claimed in claim 9 is characterized in that, described decoder is the LDPC decoder.
17. the ROM of a decoder is characterized in that, described ROM comprises first memory block and second memory block,
Described first memory block, be used to preserve attribute list, it is regular address data or irregular address data that described attribute list is used to identify the address date that described ROM controller will obtain, and wherein said regular address data and described irregular address data are divided according to predetermined ordered series of numbers rule;
Described second memory block is used to preserve irregular address data.
18. the ROM of decoder as claimed in claim 17 is characterized in that, described decoder is the LDPC decoder.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105262493A (en) * | 2015-11-17 | 2016-01-20 | 中国人民解放军92728部队 | Decoding method of low-density parity check codes |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105262493A (en) * | 2015-11-17 | 2016-01-20 | 中国人民解放军92728部队 | Decoding method of low-density parity check codes |
| CN105262493B (en) * | 2015-11-17 | 2018-08-24 | 中国人民解放军92728部队 | The interpretation method of low density parity check code |
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