CN101753130A - Bit conversion point extract circuit and lock phase clock recovery circuit of non-return-to-zero (NRZ) recovery signal and method for controlling circuits - Google Patents
Bit conversion point extract circuit and lock phase clock recovery circuit of non-return-to-zero (NRZ) recovery signal and method for controlling circuits Download PDFInfo
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- CN101753130A CN101753130A CN200810188109A CN200810188109A CN101753130A CN 101753130 A CN101753130 A CN 101753130A CN 200810188109 A CN200810188109 A CN 200810188109A CN 200810188109 A CN200810188109 A CN 200810188109A CN 101753130 A CN101753130 A CN 101753130A
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Abstract
The invention provides a bit conversion point extract circuit device, which comprises a preset current source transistor; a transistor pair which is connected with a source electrode, wherein the source electrode is inclined to the current source transistor and applies a difference non-return-to-zero (NRZ) recovery signal from the outside; and a capacitor which is connected with the transistor and the current source transistor to lead the voltage of the output node of the current source transistor to be constant.
Description
Technical field
The present invention relates to the bits switch point extraction circuit (bit-transition point extraction circuit) that a kind of non-return-to-zero recovers (NRZ-recovery) signal, a kind of phase-locked clock restore circuit that uses this circuit, and a kind of method that is used to control this circuit, and more specifically, relate to a kind of circuit (described circuit can move at a relatively high speed) that is used for recovering from non-return-to-zero input signal extraction bits switch point by the bits switch point extraction element that simple structure is provided, a kind of phase-locked clock restore circuit that uses this circuit, and a kind of method that is used to control this circuit.
Background technology
Input be modulated to the suchlike devices such as serial link receiving machine of signal that non-return-to-zero recovers sign indicating number before modulation based on the synchronous clock of the clock generating that is produced and input signal and recover Bit String (bit string).The device that plays above-mentioned effect is known as clock recovery circuitry.
As typical clock recovery circuitry, the clock recovery circuitry (after this, being called " injection locking clock recovery circuitry ") of the oscillator of the clock recovery circuitry of use phase-locked loop, over-sampling clock recovery circuitry, use injection locking (injection locked) etc. is all using.
In the described in the above clock recovery circuitry, the injection locking clock recovery circuitry generally includes bits switch point and extracts circuit and injection locked oscillator.
Known bits switch is extracted circuit and is made of delay circuit and XOR circuit.Input signal is to be modulated to the signal that non-return-to-zero recovers sign indicating number.This signal is used as the input of XOR circuit with the signal by delay circuit.
At this moment,, then export 1 if two inputs differ from one another, and if two inputs are mutually the same, then export 0.Therefore, the pulse that has the time width that signal is delayed in the position output that the bit of input signal is converted in delay circuit.
The delay circuit of bits switch point extraction circuit is usually designed to has certain length of delay, and this length of delay approximates half of a bit time width.For this reason, the ring oscillator that disposes by the positive feedback of using in the delay circuit produces clock and is widely used by the method for using the delay circuit identical with the ring oscillator that is used for bits switch point extraction circuit to obtain length of delay necessarily.
Yet, because this ring oscillator is not suitable for quick operation, can produce than ring oscillator more the LC voltage-controlled oscillator of high frequency clock generally be used for the injection locking clock recovery circuitry of operation fast.In this case, owing to need control to the length of delay of delay circuit (it is used for bits switch point extraction circuit to obtain half of a bit time width), and XOR circuit should be exported the pulse with short period width, becomes the bottleneck of prevention in the operation of high speed injection locking clock recovery circuitry high speed so known bits switch point extracts circuit.
Summary of the invention
Technical problem
Design the present invention is to solve the problems referred to above in association area.An object of the present invention is to provide a kind of CMOS bits switch point and extract circuit with quick operating structure.
Another object of the present invention provides a kind of ratio characteristics with simple structure and extracts circuit.
Another purpose of the present invention provides a kind of injection locking clock recovery circuitry, and it can extract circuit and recover to be in precision clock at a high speed by the bits switch point that the structure with high-speed cruising is provided.
Technical scheme
To achieve these goals and solve the problems referred to above in the association area, extracting circuit arrangement according to the bits switch point of exemplary embodiment of the present invention comprises: the predetermined current source transistor; And the transistor that is connected with the source is right, and it recovers input signal to current source transistor biasing and the difference non-return-to-zero that is applied with from the outside.
Bits switch point extraction circuit arrangement according to another illustrative examples of the present invention comprises: the scheduled current source transistor; The transistor that is connected with the source is right, and it recovers input signal to current source transistor biasing and the difference non-return-to-zero that is applied with from the outside; And with the capacitor of transistor to being connected with current source transistor, make the voltage constant of output node of current source transistor.
At this moment, capacitor allows the right V of transistor
GSAnd I
DSCurve has the electric capacity of working range in nonlinear area.
Use comprises according to the clock recovery device of the bits switch point extraction circuit of exemplary embodiment of the present invention: the scheduled current source transistor; The transistor that is connected with the source is right, and it recovers input signal to current source transistor biasing and the difference non-return-to-zero that is applied with from the outside; With the capacitor of transistor, make the voltage constant of output node of current source transistor to being connected with current source transistor; And the LC voltage-controlled oscillator, be used for and will the current impulse that produce be exported to predetermined difference output end by transistor.
Use comprises according to the clock recovery circuitry device of the bits switch point extraction circuit of second exemplary embodiment of the present invention: predetermined first current source transistor; The first transistor that is connected with the source is right, and it recovers input signal to first current source transistor biasing and the difference non-return-to-zero that is applied with from the outside; With first capacitor of the first transistor, make the voltage constant of the output node of the current source transistor of winning to being connected with first current source transistor; Predetermined second current source transistor; To second current source transistor biasing and to have a transistor seconds of a grid that is connected to supply voltage and another gate terminal that is connected to ground voltage right, and, make the voltage of output node of second current source transistor with second capacitor of transistor seconds to being connected; And the LC voltage-controlled oscillator, it receives according to the right output of differential signal form yoke transistor seconds.
Use comprises according to the clock recovery circuitry device of the bits switch point extraction circuit of another exemplary embodiment of the present invention: the scheduled current source transistor; The transistor that is connected with the source is right, and it recovers input signal to current source transistor biasing and the difference non-return-to-zero that is applied with from the outside; With the capacitor of transistor, make the voltage constant of output node of current source transistor to being connected with current source transistor; And the LC voltage-controlled oscillator, be used for receiving according to by using faradic form that coupling inductance produces at inductance by the current impulse of transistor to producing.
At this moment, the LC voltage-controlled oscillator comprises variable capacitor, is used to control the frequency of predetermined oscillation signal.
The method of extracting circuit according to the control bit transfer point of exemplary embodiment of the present invention may further comprise the steps: the preset transistor by having the source terminal that is connected with the scheduled current source transistor is to receiving the difference non-return-to-zero recovery input signal from the outside; The voltage that keeps the right node of connection current source transistor and transistor; And the predetermined bias electric current of the constant voltage of output node and predetermined gate voltages.
Beneficial effect
According to the present invention, may provide the CMOS bits switch point of structure to extract circuit with high speed operation.
According to the present invention, may provide a kind of bits switch point to extract circuit with simple structure.
According to the present invention, a kind of injection locking clock recovery circuitry may be provided, it extracts circuit by the bits switch point that the structure with high speed operation is provided can be in precision clock at a high speed.
Description of drawings
Fig. 1 shows the block diagram that extracts the configuration of circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.
Fig. 2 is the block diagram that extracts circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.
Fig. 3 shows the diagrammatic sketch that extracts the transistorized voltage-current characteristic curve of circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.
Fig. 4 shows the block diagram that extracts the configuration of circuit according to the bits switch point of exemplary embodiment of the present invention.
Fig. 5 shows the curve chart that extracts the predetermined data value of circuit according to the bits switch point of exemplary embodiment of the present invention.
The bits switch point that Fig. 6 shows according to another embodiment of the present invention extracts the block diagram of the configuration of circuit arrangement.
Fig. 7 shows the block diagram that extracts the configuration of circuit according to the bits switch point of another exemplary embodiment of the present invention.
Fig. 8 shows the curve chart that extracts the predetermined data value of circuit according to the bits switch point of another exemplary embodiment of the present invention.
Fig. 9 shows the block diagram of use according to the configuration of the clock recovery circuitry device of the bits switch point extraction circuit of exemplary embodiment of the present invention.
Figure 10 shows the diagrammatic sketch of use according to the configuration of the clock recovery circuitry of the bits switch point extraction circuit of exemplary embodiment of the present invention.
Figure 11 shows the curve chart according to the predetermined data value of the clock recovery circuitry of exemplary embodiment of the present invention.
Figure 12 shows the block diagram of use according to the configuration of the clock recovery circuitry device of the bits switch point extraction circuit of another exemplary embodiment of the present invention.
Figure 13 shows the diagrammatic sketch of use according to the configuration of the clock recovery circuitry of the bits switch point extraction circuit of another exemplary embodiment of the present invention.
Figure 14 shows the circuit diagram of use according to the configuration of the clock recovery circuitry device of the bits switch point extraction circuit of another exemplary embodiment of the present invention.
Figure 15 shows the circuit diagram of use according to the configuration of the clock recovery circuitry device of the bits switch point extraction circuit of another exemplary embodiment of the present invention.
Figure 16 shows and is used to control the flow chart that extracts the method for circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.
Embodiment
After this, although hereinafter will be with reference to the accompanying drawings and described in the accompanying drawings content describe the preferred embodiments of the present invention in detail, the present invention is not limited to or is defined in the preferred embodiment.
Fig. 1 shows the block diagram that extracts the configuration of circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.Fig. 2 is the transistorized block diagram that extracts circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.Fig. 3 shows the diagrammatic sketch that extracts the transistorized voltage-current characteristic curve of circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.
The present invention is based on bits switch point and extract circuit arrangement, it can extract in order to recover the bits switch point of initial clock signal by using transistor to receive from difference non-return-to-zero recovery (NRZ-recovery) input signal that the outside applied.
Shown in Fig. 2 and 3, bits switch point of the present invention extracts the drive principle that circuit arrangement uses general nmos pass transistor.As shown in the curve of Fig. 3, nmos pass transistor makes with square proportional IDS of VGS mobile.
Based on transistorized above-mentioned characteristic, the each several part that bits switch point extracts circuit arrangement 100 is sequentially described according to the job order of these parts.
At first, the difference non-return-to-zero that applies to current source transistor 120 biasings recovers input signal.
Next, pair of transistor 110 is connected with source electrode, this source electrode recovers input signal to current source transistor 120 biasing and the difference non-return-to-zero that is applied with from the outside, so that the voltage of the node that is connected with current source transistor 120 changes according to the difference non-return-to-zero recovery input signal that applies from the outside.
At this moment, the difference non-return-to-zero recovers input signal and represents a pair of voltage, comprising: the voltage voltage that moves between two scheduled voltages 1 and 0, that be applied to the first transistor of transistor in to 110; And and be applied on the relative direction of voltage of the first transistor and move the voltage of transistor seconds that move, that be applied to pair of transistors between these two voltages simultaneously.
As mentioned above, in the present invention, mainly use nmos pass transistor as transistor to 110, but be not limited to nmos pass transistor.
Fig. 4 shows the block diagram that extracts the configuration of circuit according to the bits switch point of exemplary embodiment of the present invention.Fig. 5 shows the curve chart that extracts the predetermined data value of circuit according to the bits switch point of exemplary embodiment of the present invention.
That is, as transistor to the leakage current IDS+ of 110 nmos pass transistor and IDS-according to the difference non-return-to-zero recover input signal Vin+ and Vin-(its with 0 be converted to 1 or be converted to 0 with 1) change.Ideally, two leakage currents and should be constant.Yet nmos pass transistor is carried out and the source follower identical operations, thereby the voltage of VX node changes according to the high voltage between Vin+ and the Vin-, modulates bias current IBIAS with the limited output impedance according to current source transistor 120.
At this moment, bits switch point extraction circuit arrangement 100 is to carry out the circuit that synchronous point produces pulse signal to the clock that produces from input signal.
Promptly, transistor is to bias current IBIAS 100 leakage current and that equal current source transistor 120, therefore, bits switch point extract circuit arrangement 100 can by obtain electric current and detect as the difference non-return-to-zero restoring signal of input and become 1 or become 0 point by 1 by 0.
The bits switch point that Fig. 6 shows according to another embodiment of the present invention extracts the block diagram of the configuration of circuit arrangement.
Extract in the circuit arrangement 100 (it is shown in Figure 1) at bits switch point according to exemplary embodiment of the present invention, two nmos pass transistors are worked in the mode identical with source follower, make this electric current of mobile voltage modulated of VX node, but in this case, two nmos pass transistors are worked in the linear zone of Fig. 3 curve, therefore, the total amount of modulated electric current can be very little.
Therefore, in the present invention, can be only by using bits switch point to extract the point that circuit arrangement 100 detects bits switch, but also can make voltage steady, and make modulated amounts of bias current maximization by transistor is worked in the inelastic region of the curve chart of Fig. 3 to 610 by adding capacitor at VX node place.
Based on foregoing description, will according to another embodiment of the present invention bits switch point extraction circuit sequentially be described according to being used to drive method that the bit transfer point extracts the each several part of circuit arrangement.
At first, transistor has source terminal to 610, and source terminal is connected with current source transistor 630 publicly, and the difference non-return-to-zero that is applied with from the outside recovers input signal.
At this moment, the difference non-return-to-zero recovers input signal and represents to be applied to the positive voltage of transistor to the predetermined value of the first transistor in 610, and the negative voltage of predetermined value that is applied to the transistor seconds of pair of transistors.
As mentioned above, in the present invention, mainly use nmos pass transistor as transistor to 610, but be not limited to nmos pass transistor.
Fig. 7 shows the block diagram that extracts the configuration of circuit according to the bits switch point of another exemplary embodiment of the present invention.Fig. 8 shows the curve chart that extracts the predetermined data value of circuit according to the bits switch point of another exemplary embodiment of the present invention.
Next, capacitor 620 is connected to transistor to 610 and current source transistor 630, connects current source transistor 630 and the transistor voltage constant to 610 node to be used in.
At this moment, capacitor 620 is mainly used in the capacitance that makes transistor have working range in the inelastic region to 610 VGS and IDS curve.
Next, current source transistor 620 is exported the bias current of modulating according to the constant voltage and the predetermined output impedance of node.
At this moment, bits switch point extraction circuit arrangement 100 is to carry out the circuit that synchronous point produces pulse signal to the clock that produces from output signal.
Therefore, the present invention can be by capacitor 620 is added into the VX node but not is come the bias current of modulated current source transistor 630 stablize the voltage of VX node by the voltage that uses the VX node, so the present invention can maximize the modulated total amount of bias current by transistor is worked in the inelastic region of the curve chart of Fig. 3 to 610.
Therefore, the magnitude of current of the curve chart of the modulated magnitude of current of the curve chart of Fig. 3 and Fig. 8 differs about twice or more.
That is, the bits switch of the input signal in the circuit of the present invention can produce current impulse.At last, the width of the current impulse that is produced equals the change-over time of input signal.
Under the situation that circuit runs at high speed, the bits switch time takies half corresponding to the time of one or more bits usually.Because this characteristic, not additional delay element and with circuit arrangement for being suitable for injection locking (injection locking).
Fig. 9 shows and uses the block diagram of the configuration of the clock recovery circuitry device of bits switch point extraction circuit according to an exemplary embodiment of the present invention.
Above-mentioned bits switch point can be extracted circuit 600 and LC voltage-controlled oscillator connects and disposes clock recovery circuitry of the present invention.
Figure 10 shows and uses the diagrammatic sketch of the configuration of the clock recovery circuitry of bits switch point extraction circuit according to an exemplary embodiment of the present invention.
The present invention is based on bits switch point and extract circuit arrangement, described circuit arrangement can use transistor to recover input signal by the difference non-return-to-zero that receives from the outside, extracts the bits switch point of the signal that is provided for recovering initial clock.
Subsequently the relation between the parts of reference bits transfer point extraction circuit arrangement 600 and LC voltage-controlled oscillator 900 is described by clock recovery circuitry.
Can drive clock recovery circuitry of the present invention by using bits switch point to extract circuit arrangement 600.The detailed configuration that bits switch point extracts circuit arrangement 600 will briefly be described below.
Extracting circuit arrangement 600 according to the bits switch point of exemplary embodiment of the present invention comprises: current source transistor 630, the transistor that is connected with source electrode to 610 (described source electrode is setovered and is applied with difference non-return-to-zero recovery input signal from the outside to current source transistor 630) and with transistor to 610 capacitors that are connected with current source transistor 620, make the voltage constant of output node of current source transistor 630.
Dispose clock recovery circuitry device of the present invention by being connected with LC voltage-controlled oscillator 900, the pulse of described LC voltage-controlled oscillator input current, wherein, by transfer point extract circuit arrangement 600 and transistor to 610 with a bits switch to predetermined difference output ends.
Here, LC voltage-controlled oscillator 900 comprises variable capacitor 910, the frequency of its control oscillator signal.
That is, LC voltage-controlled oscillator 900 can be controlled the frequency of oscillator signal by control variable capacitor 910.When oscillator 900 has clock that frequency approaches the bit rate of input signal when vibrating by 910 pairs in variable capacitor of control, LC voltage-controlled oscillator 900 produces and the synchronous clocks of input signal, and meanwhile is injected into locking in current impulse.
Figure 11 shows the curve chart according to the predetermined data value of the clock recovery circuitry of exemplary embodiment of the present invention.
This principle can be described by the clock recovery circuitry through injection locking.Clock recovery circuitry of the present invention also is used for respectively recovering sign indicating number with 0 and 1 corresponding to low-voltage and high-tension non-return-to-zero by use and modulates and transmit 0 and 1.This signal is as the input signal of clock recovery circuitry.
As shown in figure 11, bits switch point extract circuit 600 the point that from by synchronous input signal, produces clock (that is, bit with 0 be converted into 1 or be converted into 0 point with 1) locate to produce pulse.
At this moment, LC voltage-controlled oscillator 900 (it is the oscillator through injection locking) is the oscillator that produces clock.LC voltage-controlled oscillator 900 has and has the signal that frequency approaches the clock frequency that produced by reception and make clock and the synchronous function of input signal that is produced.
Using in the clock recovery circuitry of the oscillator of injection locking, extract spike train (train) that circuit extracted from bits switch and be input to oscillator through injection locking, described oscillator vibrates with the frequency of the bit rate that approaches input signal, thereby, produced the clock synchronous with the Bit String of input signal.
That is, applying under the situation of input signal that being used for except that the non-return-to-zero input signal periodically produce clock, using clock recovery circuitry can be used for frequency multiplier through the oscillator of injection locking.
In the present invention, bits switch point extracts the side that circuit arrangement 600 can only be connected to the difference output of LC voltage-controlled oscillator 900, and bits switch point extracts each side in the both sides that difference that circuit arrangement 600 is connected to LC voltage-controlled oscillator 900 exports.In this case, therefore opposite side can configure more stable clock restore circuit as biasing circuit to any side in the both sides as bits switch point extracts circuit arrangement.
Figure 12 shows the block diagram of use according to the configuration of the clock recovery circuitry device of the bits switch point extraction circuit of another exemplary embodiment of the present invention.
As shown in FIG., the clock recovery circuitry of circuit is extracted in use according to the bits switch point of another exemplary embodiment of the present invention configuration will be described now.
Clock recovery circuitry comprises that the first bits switch point extracts circuit arrangement 1210, and it comprises: the first predetermined current source transistor; The transistor that is connected with source electrode is right, and described source electrode recovers input signal to first current source transistor biasing and the difference non-return-to-zero that is applied with from the outside; And first capacitor, with the first transistor to being connected, so that the voltage constant of the output node of first current source transistor with first current source transistor.Clock recovery circuitry comprises that also the second bits switch point extracts circuit arrangement 1230, and it comprises: the second predetermined current source transistor; Transistor seconds is right, to the biasing of second current source transistor, and has a gate terminal that is connected to supply voltage and another gate terminal that is connected to ground voltage; And second capacitor, be connected to second current source transistor, so that the voltage constant of the output node of second current source transistor.Clock recovery circuitry also comprises LC voltage-controlled oscillator 1220, according to the right output of form reception transistor seconds of differential signal.
The clock recovery circuitry device comprises that also bits switch point extracts circuit 600 and LC voltage-controlled oscillator 1220.Therefore, the detailed description of each composed component will be omitted.
Figure 13 shows the diagrammatic sketch of configuration that use bits switch point according to another embodiment of the present invention extracts the clock recovery circuitry of circuit.
Promptly, as shown in figure 13, the first bits switch point extracts circuit arrangement 1210 and produces current impulse at the some place that comes switch bit by input difference non-return-to-zero restoring signal, current impulse is inputed to arbitrary difference output of LC voltage-controlled oscillator 1220, and the second bits switch point extracts another difference output that circuit 1230 is connected to LC voltage-controlled oscillator 1220, to be used as the constant current biasing circuit.
At this moment, LC voltage-controlled oscillator 1220 can come the frequency of control signal vibration by control capacitor 1221.When the clock that approaches the bit rate of input signal when 1220 pairs of frequencies of LC voltage-controlled oscillator vibrated, LC voltage-controlled oscillator 1220 can produce the clock synchronous with input signal by injection locking in current impulse.
Figure 14 shows the circuit diagram of configuration that use bits switch point according to another embodiment of the present invention extracts the clock recovery circuitry device of circuit.
As shown in FIG., the clock recovery circuitry device 1400 that uses bits switch point of the present invention to extract circuit can be configured to the clock recovery circuitry that the constant bias voltage by a side place of LC voltage-controlled oscillator keeps.Now this configuration will be described.
The clock recovery circuitry device 1400 that uses bits switch point to extract circuit comprises: the predetermined current source transistor; Transistor is right, is connected with source electrode, and described source electrode recovers input signal to current source transistor biasing and the difference non-return-to-zero that is applied with from the outside; Capacitor pair links to each other transistor, so that the voltage constant of current source transistor output node with current source transistor; And the LC voltage-controlled oscillator, described LC voltage-controlled oscillator receives by the current impulse of transistor to producing at the output of current source transistor.
Figure 15 shows the circuit diagram of use according to the configuration of the clock recovery circuitry device of the bits switch point extraction circuit of another exemplary embodiment of the present invention.
As shown in Figure 15, can dispose the clock recovery circuitry device 1400 that uses bits switch point of the present invention to extract circuit by coupling inductor (coupled inductor) being added into the LC voltage-controlled oscillator.Now this configuration will be described.
The clock recovery circuitry device 1500 that uses bits switch point to extract circuit comprises: the predetermined current source transistor; Transistor is right, is connected with source electrode, and described source electrode recovers input signal to current source transistor biasing and the difference non-return-to-zero that is applied with from the outside; Capacitor pair links to each other transistor, so that the voltage constant of current source transistor output node with current source transistor; And the LC voltage-controlled oscillator, receive by the current impulse of transistor according to the faradic form that in inductor, is produced by using coupling inductor producing.
Figure 16 shows and is used to control the flow chart that extracts the method for circuit arrangement according to the bits switch point of exemplary embodiment of the present invention.
Can carry out the method that is used to control bits switch point extraction circuit arrangement of the present invention by using bits switch point to extract circuit arrangement 600.Extract the driving method of circuit arrangement 600 sequentially describes according to bits switch point.
At first, current source transistor 630 receives the difference non-return-to-zero recovery input signal (S1610) from the outside.
Next, transistor is connected with source electrode 610, described source electrode recovers input signal to current source transistor 630 biasing and the difference non-return-to-zero that is applied with from the outside, thereby described transistor is to being applied with this input signal (S1620).
At this moment, the difference non-return-to-zero recovers input signal and represents to be applied to the positive voltage of transistor to the predetermined value of 610 the first transistor, and the negative voltage that is applied to the predetermined value of the right transistor seconds of transistor.
As mentioned above, in the present invention, mainly use nmos pass transistor as transistor to 610, but be not limited to nmos pass transistor.
Next, capacitor 620 is connected to transistor to 610 and current source transistor 630, makes the voltage constant (S1630) of output node of current source transistor 630.
At this moment, bits switch point extraction circuit arrangement 600 can be represented to be used for to carrying out the circuit that synchronous point produces pulse signal at the clock that produces from input signal.
Form according to program command (it can carry out and can be recorded in the computer-readable medium by multiple computer module) is implemented exemplary embodiment of the present invention.Computer-readable medium can comprise program command, data file data structure of absolute version or combining form etc.The program command that is recorded in the medium is used for the present invention by specific design or configuration, but the known technology that can be used as the those of ordinary skill of computer software fields uses.Computer readable recording medium storing program for performing comprises magnetizing mediums (such as hard disk, floppy disk and tape), optical record medium (such as CD-ROM and DVD), magneto-optic (magneto-optical) medium (but reading disk such as light) and the hardware unit (such as ROM, RAM, flash memory) etc. of for example storage and executive program order.Program command is handled and is comprised for example by the high-level language sign indicating number by using interpretive program to be carried out by computer outside the machine language of compiler preparation.In order to carry out operation of the present invention, can operate hardware unit by one or more softwares.Vice versa.
As mentioned above, although described the present invention with reference to limited embodiment and accompanying drawing, the present invention is not limited to these embodiment and can makes multiple conversion and modification by those skilled in the art.Therefore, scope of the present invention should not be limited to the foregoing description and should be defined by claims and equivalents thereof.
Label list
600: bits switch point extracts circuit
610: transistor pair
620: capacitor
630: current source transistor
The 900:LC voltage-controlled oscillator
Claims (18)
1. a bits switch point extracts circuit arrangement, comprising:
The predetermined current source transistor; And
Transistor is right, is connected with source electrode, and described source electrode recovers input signal to biasing of described current source transistor and the difference non-return-to-zero that is applied with from the outside.
2. a bits switch point extracts circuit arrangement, comprising:
The predetermined current source transistor;
Transistor is right, is connected with source electrode, and described source electrode recovers input signal to biasing of described current source transistor and the difference non-return-to-zero that is applied with from the outside; And
Capacitor, with described transistor to being connected, so that the voltage constant of the output node of described current source transistor with described current source transistor.
3. bits switch point according to claim 2 extracts circuit arrangement,
Wherein, described capacitor makes right VGS of described transistor and IDS curve have the ability of working in the inelastic region scope.
4. clock recovery device that uses bits switch point to extract circuit comprises:
The predetermined current source transistor;
Transistor is right, is connected with source electrode, and described source electrode recovers input signal to biasing of described current source transistor and the difference non-return-to-zero that is applied with from the outside;
Capacitor, with described transistor to being connected, so that the voltage constant of the output node of described current source transistor with described current source transistor; And
The LC voltage-controlled oscillator, described LC voltage-controlled oscillator is imported by the current impulse of described transistor to producing to predetermined difference output end.
5. clock recovery circuitry device that uses bits switch point to extract circuit comprises:
The first predetermined current source transistor;
The first transistor is right, and to the biasing of described first current source transistor and be applied with the source electrode that difference non-return-to-zero from the outside recovers input signal and be connected;
First capacitor, with described the first transistor to being connected, so that the voltage constant of the output node of described first current source transistor with described first current source transistor;
The second predetermined current source transistor;
Transistor seconds is right, and to the biasing of described second current source transistor and be applied with the source electrode that difference non-return-to-zero from the outside recovers input signal and be connected;
Transistor seconds to described current source transistor biasing is right, and it has a gate terminal that is connected to supply voltage and another gate terminal that is connected to ground voltage; And second capacitor, be connected to described second current source transistor, so that the voltage constant of the output node of described second current source transistor; And
The LC voltage-controlled oscillator receives the right output of described transistor seconds according to the form of differential signal.
6. clock recovery circuitry device that uses bits switch point to extract circuit comprises:
The predetermined current source transistor;
Transistor is right, is connected with source electrode, and described source electrode recovers input signal to biasing of described current source transistor and the difference non-return-to-zero that is applied with from the outside;
Capacitor, with described transistor to being connected, so that the voltage constant of the output node of described current source transistor with described current source transistor; And
The LC voltage-controlled oscillator, described LC voltage-controlled oscillator receives by the current impulse of described transistor to producing at the output of described current source transistor.
7. clock recovery circuitry device that uses bits switch point to extract circuit comprises:
The predetermined current source transistor;
Transistor is right, is connected with source electrode, and described source electrode recovers input signal to biasing of described current source transistor and the difference non-return-to-zero that is applied with from the outside;
Capacitor, with described transistor to being connected, so that the voltage constant of the output node of described current source transistor with described current source transistor; And
The LC voltage-controlled oscillator receives by the current impulse of described transistor to producing according to the faradic form that produces in described inductor by using coupling inductor.
8. extract circuit arrangement according to each described bits switch point in the claim 4 to 7,
Wherein, described capacitor makes right VGS of described transistor and IDS curve have the ability of working in the inelastic region scope.
9. extract the clock recovery circuitry device of circuit according to each described use bits switch point in the claim 4 to 7,
Wherein, described LC voltage-controlled oscillator comprises variable capacitor, the frequency of the oscillator signal that described variable capacitor control is predetermined.
10. extract circuit arrangement according to each described bits switch point in the claim 1 to 2 or in the claim 4 to 7,
Wherein, described difference non-return-to-zero recovers input signal and represents to be applied to the positive voltage of predetermined value of the right the first transistor of described transistor and the negative voltage that is applied to the predetermined value of the right transistor seconds of described transistor.
11. extract circuit arrangement according to each described bits switch point in the claim 1 to 2 or in the claim 4 to 7,
Wherein, described transistor is to comprising nmos pass transistor.
12. extract circuit arrangement according to each described bits switch point in the claim 1 to 2 or in the claim 4 to 7,
Wherein, described bits switch point extraction circuit arrangement is at the circuit that need carry out synchronous some generation pulse signal to the clock that produces from described input signal.
13. a control bit transfer point extracts the method for circuit arrangement, may further comprise the steps:
Recover input signal by preset transistor to receive the difference non-return-to-zero from the outside with the source terminal that is connected with the predetermined current source transistor;
Be kept for described current source transistor and described transistor voltage the node that is connected; And
Constant voltage and predetermined grid voltage by described node are exported predetermined bias current.
14. control bit transfer point according to claim 13 extracts the method for circuit arrangement,
Wherein, described difference non-return-to-zero recovers input signal and represents to be applied to the positive voltage of predetermined value of the right the first transistor of described transistor and the negative voltage that is applied to the predetermined value of the right transistor seconds of described transistor.
15. control bit transfer point according to claim 13 extracts the method for circuit, wherein, described transistor is to comprising nmos pass transistor.
16. control bit transfer point according to claim 13 extracts the method for circuit,
Wherein, described bits switch point extraction circuit arrangement is at the circuit that need carry out synchronous some generation pulse signal to the clock that produces from described input signal.
17. control bit transfer point according to claim 13 extracts the method for circuit,
Wherein, be kept for described current source transistor and the described transistor step to the voltage of the node that is connected described, described capacitor makes right VGS of described transistor and IDS curve have the ability of working in the inelastic region scope.
18. a computer readable recording medium storing program for performing, wherein, record is used for carrying out the program according to any one method of claim 13 to 17.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810188109 CN101753130B (en) | 2008-12-12 | 2008-12-12 | Bit conversion point extract circuit and lock phase clock recovery circuit of non-return-to-zero (NRZ) recovery signal and method for controlling circuits |
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| CN 200810188109 CN101753130B (en) | 2008-12-12 | 2008-12-12 | Bit conversion point extract circuit and lock phase clock recovery circuit of non-return-to-zero (NRZ) recovery signal and method for controlling circuits |
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| CN101753130A true CN101753130A (en) | 2010-06-23 |
| CN101753130B CN101753130B (en) | 2013-02-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109818605A (en) * | 2017-11-21 | 2019-05-28 | 德州仪器公司 | Generate the level shifter circuit of bipolar clock signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2445123C3 (en) * | 1973-09-26 | 1980-03-06 | Hitachi, Ltd. | Analog signal processing circuit |
| US6249192B1 (en) * | 1998-01-26 | 2001-06-19 | Agere Systems Guardian Corp. | Clock injection system |
| CN1167199C (en) * | 2000-06-08 | 2004-09-15 | 华为技术有限公司 | Injection-type synchronous narrow-band regenerative phase-locked loop |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109818605A (en) * | 2017-11-21 | 2019-05-28 | 德州仪器公司 | Generate the level shifter circuit of bipolar clock signal |
| CN109818605B (en) * | 2017-11-21 | 2023-10-03 | 德州仪器公司 | Level shifter circuit for generating bipolar clock signal |
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| CN101753130B (en) | 2013-02-27 |
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