CN101751995B - Storage device with flash memory and storage method of flash memory - Google Patents
Storage device with flash memory and storage method of flash memory Download PDFInfo
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Abstract
The invention relates to a storage device with flash memory and a storage method of flash memory; the storage device with flash memory comprises a flash memory and a control unit which is electrically connected with the flash memory; the flash memory comprises a plurality of first transistors and a plurality of second transistors; the control unit receives a data write instruction, if the write instruction is stored in the first transistors, the control unit stores the data into the first transistors by a first dynamic leveling read-write calculating method, if the write instruction is stored in the second transistors, the control unit stores the data into the second transistors by a second dynamic leveling read-write calculating method; the control unit manages the data in the first transistors by a first static leveling read-write calculating method and manages the data in the second transistors by a second static leveling read-write calculating method; in the invention, aiming at different flash memories, different management measures are adopted, so as to prolong the life of the flash memory.
Description
Technical field
The present invention relates to a kind of storage device and storage method, particularly relate to a kind of the have storage device of flash memory and the storage method of flash memory.
Background technology
Flash memory (Flash ROM, i.e. fast flash memory bank) can be divided into single stage unit (Single LevelCell is called for short SLC) and multi-level unit (Multi Level Cell is called for short MLC).Using in the mode of internal storage location, SLC flash memory device and EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read-Only Memory, EEPROM) identical, but thinner with the oxide film in source electrode (Source) at floating grid (Floating gate, the gate of floating).Writing of data is the electric charge making alive by floating grid, then can stored electric charge be eliminated by source electrode, store information bit (bit is bit, is all called bit herein) one by one by this, programming can be provided fast and read.But SLC is limited to the problem of low silicon efficiency (Siliconefficiency), have only by advanced flow process reinforcement technique (Processenhancements), could promote the range of application of SLC device.
MLC uses electric charge in various degree in floating grid, therefore can in one-transistor (transistor), store data more than two bits, and by remembering somatic writing and the control of responding to, in one-transistor (transistor is electric crystal, is all called transistor herein), produce 4 layers of unit.The data reading-writing speed of this kind of mode is medium, and needs optimized sensor circuit (sensingcircuitry).
In addition, due to semi-conductive physical characteristics, adopt each memory region of flash memory (block) of MLC to be about 10,000 times serviceable life and delete/write, each memory region of the flash memory of SLC its serviceable life is to delete/write for 100,000 times.
In order to extend the life-span of flash memory, static state average read-write algorithm (StaticWear Leveling) and consecutive mean read-write algorithm (Dynamic Wear Leveling) are developed at present, this two calculus of classes method is all for fear of the specific memory region of excessive use, and while causing most of memory region to still have very long serviceable life, there is the bad block of excessively being deleted/writing in internal memory, no matter be therefore static state average read-write algorithm or consecutive mean read-write algorithm, can contribute on average to use each memory region, to extend the life-span of flash memory entirety.
In order to take into account the advantage that SLC is quick and the life-span is long, and MLC low price and jumbo advantage, each factory proposes a plan one after another, and wherein, the Combined type storage device Shou Ge factory of SLC design mixed with MLC payes attention to.But existing flash memory management method, for example TaiWan, China is invented I293729 patent " the management algorithm of flash memory ", and the disclosed administrative skill of No. 94125951 application case " adjustable flash memory management system and method ", do not consider in storage device, whether there is different types of flash memory.But in fact SLC is different from MCL characteristic, while using the storage device of two or more flash memorys with, how effectively work is read and is write in management, to allow user really enjoy that read or write speed is fast, the life-span long, at a low price and jumbo benefit, is an important topic.
Summary of the invention
The object of the invention is can have different ladder of management to extend the storage device with flash memory in flash memory life-span for different flash memorys providing a kind of.
The object of the invention to solve the technical problems realizes by the following technical solutions.The storage device with flash memory proposing according to the present invention, comprises: a flash memory and a control module being electrically connected with this flash memory; This flash memory comprises most the first transistors and most transistor secondses; This control module is in order to judge, a document to be stored in those the first transistors or in those transistor secondses, if be stored in those the first transistors, according to one first consecutive mean read-write algorithm, this document is stored in those the first transistors, if be stored in those transistor secondses, according to one second consecutive mean read-write algorithm, this document is stored in those transistor secondses; This control module is also managed the data in those the first transistors according to one first static state average read-write algorithm, and manages the data in those transistor secondses according to one second static state average read-write algorithm.
Preferably, the aforesaid storage device with flash memory, those the first transistors can be written into respectively data and reach one first upper limit number of times, those transistor secondses can be written into respectively data and reach one second upper limit number of times, this control module is one first setup parameter that determines this first static state average read-write algorithm according to this first upper limit number of times, to manage the data in those the first transistors, this control module also determines one second setup parameter of this second static state average read-write algorithm according to this second upper limit number of times, to manage the data in those transistor secondses.
Control module of the present invention is that the range that respectively this first transistor is written into the number of times of data is more than or equal to this first setup parameter, the mobile data that is stored in this first transistor that writes least number of times; And the range that respectively this transistor seconds is written into the number of times of data is more than or equal to this second setup parameter, this control module is the mobile data that is stored in this transistor seconds that writes least number of times.
Preferably, those the first transistors of flash memory of the present invention and those transistor secondses, be respectively can be in order to store the single stage unit of data of a bit, and can be in order to store the multi-level unit of data of most bits.
Another object of the present invention, being to provide a kind of has the storage method of different ladder of management with the flash memory in prolongation flash memory life-span for different flash memorys.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The storage method of the flash memory proposing according to the present invention comprises: judge a document is stored in most the first transistors or in most transistor secondses, if be stored in those the first transistors, store this document in those the first transistors according to one first consecutive mean read-write algorithm, if be stored in those transistor secondses, store this document in those transistor secondses according to one second consecutive mean read-write algorithm, in addition, also respectively according to one first static state average read-write algorithm and one second static state average read-write algorithm manage be stored in those the first transistors with those transistor secondses in data.
Preferably, aforesaid storage method, those the first transistors can be written into respectively data and reach one first upper limit number of times, and those transistor secondses can be written into respectively data and reach one second upper limit number of times; Can determine one first setup parameter of this first static state average read-write algorithm according to this first upper limit number of times, to manage the data in those the first transistors, and can determine one second setup parameter of this second static state average read-write algorithm according to this second upper limit number of times, to manage the data in those transistor secondses.
More preferably, aforesaid storage method, the range that is written into the number of times of data when each this first transistor is more than or equal to this first setup parameter, the mobile data that is stored in this first transistor that writes least number of times, and the range that respectively this transistor seconds is written into the number of times of data is more than or equal to this second setup parameter, the mobile data that is stored in this transistor seconds that writes least number of times.
By technique scheme, the present invention has the storage device of flash memory and the storage method of flash memory at least has following advantages and beneficial effect: different in response to the physical characteristics of the first transistor and transistor seconds, adopt different the first static state average read-write algorithm and the second static state average read-write algorithm to manage respectively the data being stored in the first transistor and transistor seconds, more to extend the life-span of flash memory.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of instructions, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Brief description of the drawings
Fig. 1 is the block schematic diagram that the present invention has the preferred embodiment of the storage device of flash memory.
Fig. 2 is the process flow diagram that preferred embodiment that the present invention has a storage device of flash memory stores a document.
Fig. 3 is that the process flow diagram of the data in the first memory region and the second memory region that is stored in is managed in the preferred embodiment of inventing the storage device with flash memory.
Embodiment
Technological means and effect of taking for reaching predetermined goal of the invention for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to the storage device with flash memory proposing according to the present invention and its embodiment of storage method, structure, step, feature and effect thereof of flash memory, be elaborated.
Referring to shown in Fig. 1, is the block schematic diagram that the present invention has the preferred embodiment of the storage device of flash memory.The storage device with flash memory 10 of preferred embodiment of the present invention comprises a flash memory 1 (Flash memory) and a control module 2 being electrically connected with this flash memory 1.
Above-mentioned flash memory 1 comprises multiple first memory regions 11 (block) with most the first transistors 111, and multiple second memory region 12 with most transistor secondses 121.In the present embodiment, those the first transistors 111 are respectively can be in order to store the single stage unit (Single Level Cell, be called for short SLC) of data of a bit; And those transistor secondses 121 are respectively can be in order to store multi-level unit (the Multi Level Cell of data of most bits, be called for short MLC), 1 of the flash memory of the present embodiment is the solid magnetic disc of a kind of SLC of mixing and MLC hybrid (hybrid) (Solid State Disk).
It is worth mentioning that, each first memory region 11 can only be written into data and reach one first upper limit number of times, and also can only being written into data, each second memory region 12 reaches one second upper limit number of times, because those the first transistors 111 in the first memory region 11 are SLC, therefore the first upper limit number of times is about 100,000 times in the present embodiment, and because those transistor secondses 121 in the second memory region 12 are MLC, therefore the second upper limit number of times is approximately 10,000 times in the present embodiment.
Shown in Fig. 2, it is the process flow diagram that storage device 10 stores a document.When this control module 2 will be stored in a document in flash memory 1, first control module 2 can carry out step 84, the data that receives writes instruction, this data writes its content of instruction and has comprised a FAT (File Allocation Table, be called for short FAT) information such as the Material Name of this document of noting down, position, size, then carry out step 81, control module 2 is understood this command content, and judgement needs this document be stored in the first memory region 11 or be stored in the second memory region 12.If this command content is for to be stored in this document in those first memory regions 11,2 execution steps 82 of control module, store this document in those first memory regions 11 according to one first consecutive mean read-write algorithm, in the present embodiment, the first consecutive mean read-write algorithm meaning, be written into the number of times of data by adding up each first memory region 11, and in the time will storing data, utilize this algorithm to select to be written into one of data least number of times or several the first memory region 11 and store this document.If this command content is for to be stored in this document in those second memory regions 11, 2 execution steps 83 of control module, store this document in those second memory regions 12 according to one second consecutive mean read-write algorithm, the second consecutive mean read-write algorithm in the present embodiment, meaning is with the first consecutive mean read-write algorithm, be written into the number of times of data by adding up each second memory region 12, and in the time will storing data, utilize the second consecutive mean read-write algorithm to select to be written into one of data least number of times or several the second memory region 12 and store this document.In one embodiment of the invention, the second consecutive mean read-write algorithm and the first consecutive mean read-write algorithm are independent different algorithm.
Refer to shown in Fig. 1 and Fig. 3, Fig. 3 is the process flow diagram that storage device 10 management are stored in the data in the first memory region 11 and the second memory region 12.Due to some data, it is the data of seldom being write such as the set data of pdf document and operating system, therefore store the number of times that the memory region 11,12 of these data is written into also few, have longer serviceable life compared to 11,12 of other memory regions, occur for fear of this class situation, control module 2 can be on suitable opportunity, and the mobile data that these are seldom write is relatively to other memory regions 11,12, and this is static state average read-write algorithm.In the present embodiment, this control module 2 is obtained those the first memory regions 11 and 12 points of other first upper limit number of times of those second memory regions and the second upper limit number of times in step 91, and arrange in pairs or groups in step 92, monitor and add up those first memory regions 11 and else write number of times with 12 points of those second memory regions, and in step 93, obtain one first initial setup parameter and one second setup parameter.
Generally, in the time that flash memory 1 whole service life is still normal, control module 2 can carry out step 98, selects to maintain the first setup parameter, the second setup parameter that in step 93, obtain, and then enters step 94 or step 95, in step 94, control module 2 is by the access times of each the first memory region 11 of statistics in step 92, obtain the sample set of those access times, whether the range that is judged again this sample set is more than or equal to the first setup parameter in step 98, if be judged as YES, control module 2 performs step 96, the mobile data that is stored in several the first memory regions 11 that write least number of times, to writing in several the first memory regions 11 that indegree is maximum, originally being stored in the data of writing the first memory region 11 that indegree is maximum is moved in several the first memory regions 11 that write least number of times, if the judged result of step 94 is no, get back to step 92, control module 2 continue to monitor and add up those first, the second memory region 11, 12 access times, step 95 item is similar to step 94, the access times sample set of each the second memory region 12 that control module 2 gets by statistics, whether the range that is judged again this sample set is more than or equal to the second setup parameter, if be judged as YES, control module 2 performs step 97, will be stored in the data of several the second memory regions 12 that write least number of times, and is stored in the data interchange of writing the second memory region 12 that indegree is maximum, if the judged result of step 95 is no, get back to step 92.
Flash memory 1 has used a very long time, now may there is part memory region 11, see the bottom soon for 12 serviceable life, therefore must moderately adjust first, the second setup parameter, avoid allowing memory bad block occur ahead of time, control module 2 can carry out determining step 99, judge respectively in the first memory region 11 and the second memory region 12, write the memory region 11 that indegree is maximum, whether 12 lower than 1000 times, if NO, perform step 98 and maintain first, two setup parameters, if be judged as YES, perform step 910, by first, under the second setup parameter, repair, then control module 2 is carried out and similarly step 94 of step 94 again ' or with the similar step 95 of step 95 ', step 94 ', 95 ' with step 94, 95 different places are, it is first years old, the second setup parameter is to repair through under step 910.Thus, control module 2 is in the time that exhaust the serviceable life of flash memory 1 soon, can more continually the data of seldom being write be replaced to stored memory region 11,12, make the whole service life of flash memory 1 average, avoid part memory region 11,12 to form bad block, but other memory regions 11,12 still also have serviceable life many times.
It is worth mentioning that, the present embodiment is the sample range of utilizing the access times of memory region 11,12, judge whether to want mobile data, but can also adopt sample standard deviation, mean absolute deviation or interquartile range etc. can sense the computing of the variation of sample numerical value, judge whether to want mobile data, be not limited to the present embodiment; In addition, the step 99 that the present embodiment control module 2 is performed, described is only for 1000 times for example, can comply with different demands shift, is not limited with the present embodiment.
The first transistor 111 and the transistor seconds 112 of the flash memory 1 of the present embodiment, be respectively SLC and MLC, in fact, hybrid-type flash memory 1 may be also the transistor that has mixed the transistor AND gate that can store dibit data and can store three bit data, or or even other can expect with prior art or not expected flash memory mixed species, and be not only limited with the present embodiment.
In sum, effect of the present invention is, different in response to the physical characteristics of the first transistor and transistor seconds, adopt different the first consecutive mean read-write algorithm and the second consecutive mean read-write algorithm to manage respectively the data being stored in the first transistor and transistor seconds, also adopt different the first static state average read-write algorithm and the second static state average read-write algorithm to manage respectively the data being stored in the first transistor and transistor seconds, more to extend the life-span of flash memory, therefore really can reach object of the present invention.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the method for above-mentioned announcement and technology contents to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (12)
1. there is a storage device for flash memory, it is characterized in that this storage device comprises:
One flash memory, comprises most the first transistors and most transistor secondses; And
One control module, is electrically connected with this flash memory, and this control module is managed the data in those the first transistors according to one first static state average read-write algorithm, and manages the data in those transistor secondses according to one second static state average read-write algorithm;
Wherein, those the first transistors have respectively the serviceable life that can only be written into data and reach one first upper limit number of times, those transistor secondses have respectively the serviceable life that can only be written into data and reach one second upper limit number of times, this control module is one first setup parameter that determines this first static state average read-write algorithm according to this first upper limit number of times, to manage the data in those the first transistors, this control module also determines one second setup parameter of this second static state average read-write algorithm according to this second upper limit number of times, to manage the data in those transistor secondses; And this control module also according to each this first transistor be written into the number of times of data and this first upper limit number of times and respectively this transistor seconds be written into number of times and this second upper limit number of times of data, judge whether to repair down this first setup parameter, this second setup parameter, judge should repair down this first setup parameter, this second setup parameter time when this control module, will under this first setup parameter, this second setup parameter, repair.
2. the storage device with flash memory as claimed in claim 1, it is characterized in that: the sample standard deviation that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, this control module is the mobile data that is stored in this first transistor that writes least number of times; The sample standard deviation that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, and this control module is the mobile data that is stored in this transistor seconds that writes least number of times.
3. the storage device with flash memory as claimed in claim 1, it is characterized in that: the mean absolute deviation that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, this control module is the mobile data that is stored in this first transistor that writes least number of times; The mean absolute deviation that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, and this control module is the mobile data that is stored in this transistor seconds that writes least number of times.
4. the storage device with flash memory as claimed in claim 1, it is characterized in that: the interquartile range that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, this control module is the mobile data that is stored in this first transistor that writes least number of times; The interquartile range that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, and this control module is the mobile data that is stored in this transistor seconds that writes least number of times.
5. the storage device with flash memory as claimed in claim 1, it is characterized in that: the range that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, this control module is the mobile data that is stored in this first transistor that writes least number of times; The range that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, and this control module is the mobile data that is stored in this transistor seconds that writes least number of times.
6. the storage device with flash memory as described in claim as arbitrary in claim 1 to 5, is characterized in that: those the first transistors are respectively in order to store the data of a bit, and those transistor secondses are respectively in order to store the data of most bits.
7. a storage method for flash memory, is characterized in that this storage method comprises:
(A) obtain most the first transistors and most transistor secondses divide other one first upper limit number of times and one second upper limit number of times, respectively this first transistor be written into the number of times of data and respectively this transistor seconds be written into the number of times of data, wherein, those the first transistors have respectively the serviceable life that can only be written into data and reach this first upper limit number of times, and those transistor secondses have respectively the serviceable life that can only be written into data and reach this second upper limit number of times;
(B) determine one first setup parameter of one first static state average read-write algorithm according to this first upper limit number of times, and determine one second setup parameter of one second static state average read-write algorithm according to this second upper limit number of times;
(C) according to this first upper limit number of times, this second upper limit number of times, respectively this first transistor be written into the number of times of data and respectively this transistor seconds be written into the number of times of data, judge whether to repair down this first setup parameter, this second setup parameter;
(D) judge should repair down this first setup parameter, this second setup parameter time when step (C), will under this first setup parameter, this second setup parameter, repair; And
(E) according to this first static state average read-write algorithm and this first setup parameter, to manage the data in those the first transistors, and according to this second static state average read-write algorithm and this second setup parameter, to manage the data in those transistor secondses.
8. the storage method of flash memory as claimed in claim 7, it is characterized in that: the sample standard deviation that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, the mobile data that is stored in this first transistor that writes least number of times, and the sample standard deviation that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, the mobile data that is stored in this transistor seconds that writes least number of times.
9. the storage method of flash memory as claimed in claim 7, it is characterized in that: the mean absolute deviation that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, the mobile data that is stored in this first transistor that writes least number of times, and the mean absolute deviation that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, the mobile data that is stored in this transistor seconds that writes least number of times.
10. the storage method of flash memory as claimed in claim 7, it is characterized in that: the interquartile range that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, the mobile data that is stored in this first transistor that writes least number of times, and the interquartile range that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, the mobile data that is stored in this transistor seconds that writes least number of times.
The storage method of 11. flash memorys as claimed in claim 7, it is characterized in that: the range that is written into the number of times of data when each those the first transistor is more than or equal to this first setup parameter, the mobile data that is stored in this first transistor that writes least number of times, and the range that is written into the number of times of data when each those transistor seconds is more than or equal to this second setup parameter, the mobile data that is stored in this transistor seconds that writes least number of times.
The storage method of the flash memory as described in 12. claims as arbitrary in claim 7 to 11, is characterized in that: those the first transistors are respectively in order to store the data of a bit, and those transistor secondses are respectively in order to store the data of most bits.
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