CN101742489B - Apparatus for performing a downlink or uplink processing in a wireless communication system and a data processing method - Google Patents
Apparatus for performing a downlink or uplink processing in a wireless communication system and a data processing method Download PDFInfo
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- CN101742489B CN101742489B CN2009100088543A CN200910008854A CN101742489B CN 101742489 B CN101742489 B CN 101742489B CN 2009100088543 A CN2009100088543 A CN 2009100088543A CN 200910008854 A CN200910008854 A CN 200910008854A CN 101742489 B CN101742489 B CN 101742489B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
An apparatus for performing downlink or uplink processing in a wireless communication system and a data processing method. An apparatus for performing downlink processing in a wireless communication system to maintain efficiency of system bandwidth includes a sharing-ring buffer, a MAC-PHY interface, a security engine, and a DMA processor. The sharing-ring buffer is for storing multi-format data. The MAC-PHY interface is for receiving input data and storing the input data into the sharing-ring buffer to form stored data, the security engine is for retrieving stored data from the sharing-ring buffer, decrypting the retrieved data to form decrypted data and storing the decrypted data in the sharing-ring buffer, and the DMA processor is for accessing the sharing-ring buffer to obtain the decrypted data. The method and apparatus of the present invention is capable of improving the whole operating rate of the a wireless communication system and remarkably reducing the scale of the wireless communication system.
Description
Technical field
The present invention is relevant for radio communication, more specifically, relevant in wireless communication system, implement down link (downlink, DL) or up link (uplink, device and the data processing method UL) handled.
Background technology
Fig. 1 is according to prior art applied a kind of typical frame (ftame) structural representation in wireless communication system; Wherein, Wireless communication system is for example global intercommunication microwave access (Worldwide InteroperabilityMicrowave Access, WiMAX) communication system.The WiMAX communication system can utilize downlink burst (burst) and uplink burst to communicate according to the sketch map of the frame structure shown in Fig. 1.In Fig. 1, (Orthogonal Frequency Division Multiple Access is an example OFDMA), has provided the information and the burst content that contain in the OFDMA symbol among the figure with the orthogonal frequency division multiple access.With OFDMA symbol k to k+33 symbol be example, wherein, in k symbol, comprise preamble (preamble); And comprise downlink map table (DL-MAP) in k+1 symbol, i.e. DL-mapping table, and frame control header (frame control header; FCH), comprise the DL burst in k+3 the symbol, and uplink map table (UL-MAP); Be the UL-mapping table, comprise a plurality of DL bursts in k+3 to the k+15 symbol, and comprise a plurality of UL bursts in k+17 to the k+26 symbol; In like manner, from the k+29 symbol, above-mentioned distribution circulates.The leftmost side part of Fig. 1 has for example shown subchannel logical number (subchannel logical number), from s to s+N.Should be noted that between k+15 symbol and k+17 symbol, to be transmission/reception conversion time slot (TTG), and between k+26 symbol and the k+29 symbol, be reception/transmission conversion time slot (RTG).Fig. 2 is used for medium access control (the Medium Access Control that frame structure shown in Figure 1 typically uses the downlink burst form; MAC) protocol Data Unit (Protocol Data Unit; The embodiment of MAC header (header) PDU); Wherein, the MAC header length among Fig. 1 is 68 system positions (6octets), and said MAC header typically is used for frame structure as shown in Figure 1 with the downlink burst form.Medium access control header among Fig. 2 is by the MAC header, load (payload), CRC (CyclicRedundancy Check, CRC) three parts are formed, wherein load, CRC is an option.And among Fig. 2, the MAC header is launched in detail, visible, its containing type, parameters such as EKS, LEN MSB, LEN LSB, CIDMSB, HCS and CID LSB.
According to prior art, typical WiMAX MAC circuit comprises receptions (receiving Rx) path, i.e. a plurality of levels (stage) on the Rx path, and more comprise transmission (transmitting, Tx) path, i.e. a plurality of grades on the Tx path.And a plurality of levels on each Rx path and Tx path all are continuous distribution, because consider the discrete cell of data, a plurality of levels on each path need the serial running, so be difficult to further improve the overall operation speed of WiMAX MAC circuit.In addition, consider the Rx path, for a plurality of levels, need a plurality of buffers, for example first in first out (First In First Out, FIFO) memory.So in order to obtain more performance on the Rx path, the storage volume of each of a plurality of buffers all can not be too little, so it is less to have caused reducing the possibility of scale of WiMAX MAC circuit.
Summary of the invention
In view of this, the present invention is provided at device and the data processing method that wireless communication system is implemented down link or uplink processing.
One of the object of the invention provides a kind of device that down link is handled of in wireless communication system, implementing, and wherein, this device is used to keep the efficient of system's frequency range, and this device comprises: share the ring buffer, be used to store multi-form data; The medium access control physical layer interface is used for receiving the input data, and wherein, these input data comprise at least one data burst, and this medium access control physical layer interface should be imported data storing and share in the ring buffer at this, to form storage data; Security engine is used for sharing this storage data of ring buffer acquisition from this, forming acquisition data, and deciphers this acquisition data, forming data decryption, and this data decryption is stored in this shares in ring buffer; And the direct memory access (DMA) processor, be used for access and should share the ring buffer to obtain this data decryption.
Another object of the present invention provides a kind of device of in wireless communication system, implementing uplink processing, and wherein, this device is used to keep the efficient of system's frequency range, and this device comprises: share the ring buffer, be used to store multi-form data; The direct memory access (DMA) processor is used for receiving the input data, and should import data storing and share the ring buffer to form storage data in this; Security engine is used for sharing this storage data of ring buffer acquisition from this, with the formation acquisition data, and encrypts this acquisition data to form enciphered data, and wherein, this enciphered data is stored in this and shares the ring buffer; And the medium access control physical layer interface, be used for sharing the ring buffer and receive this enciphered data from this.
A further object of the present invention provide a kind of in wireless communication system data processing method, comprise: provide and share the ring buffer, be used to store multi-form data; Receive the input data, wherein these input data comprise at least one data burst, and should import data storing and share in the ring buffer to form storage data in this; Share this storage data of ring buffer acquisition from this, to form acquisition data; Decipher this acquisition data with the formation data decryption, and this data decryption is stored in this shared ring buffer; And access should be shared the ring buffer to obtain this data decryption.
The present invention provide in addition a kind of in wireless communication system data processing method, this method comprises: provide one to share the ring buffer and be used to store at least one type of data; Receive the input data, wherein, the form of these input data is protocol data unit form, and should the input data storing share in the ring buffer to form storage data in this; Share this storage data of ring buffer acquisition from this, to form acquisition data; Encrypt this acquisition data, forming enciphered data, and this enciphered data is stored in this shares in ring buffer, wherein the form of this enciphered data is the data burst form; And this shared ring buffer of access is used for giving baseband circuit with this encrypted data transmission to obtain this enciphered data.
Different with prior art, the device in the embodiments of the invention can improve the operation rate of the integral body of wireless communication system with and related methods, so has more performance than prior art.Device in the embodiments of the invention with another beneficial effect of and related methods is; Do not hinder logic level (the logically successive stage) running separately continuously on the transmission/RX path in the wireless communication system, just can significantly reduce the scale of wireless communication system.
Description of drawings
Fig. 1 is according to prior art applied a kind of typical frame structure sketch map in wireless communication system.
Fig. 2 is used for the embodiment of MAC header that frame structure shown in Figure 1 typically uses the MAC PDU of downlink burst form.
Fig. 3 is according to the first embodiment of the present invention, in wireless communication system, is used to keep the efficient of system's frequency range and the sketch map of implementing the device 100 of down link or uplink processing.
Fig. 4 is the flow chart of the method 910 of the deal with data at wireless communication system according to an embodiment of the invention.
Fig. 5 is the flow chart of the method 920 of the deal with data in the wireless communication system according to another embodiment of the invention.
Fig. 6 is the actual system architecture sketch map of device 100 according to an embodiment of the invention, as shown in Figure 3.
Fig. 7 is according to a specific embodiment among Fig. 6, the sketch map the processing stage of the individual program of Rx burst control device 110 as shown in Figure 6 partly overlapping.
Fig. 8 is the sketch map that is used for the buffer structure of Rx burst control device 110 shown in Figure 6.
Fig. 9 is for another specific embodiment of providing according to Fig. 6, the sketch map the processing stage of other scheme of Tx burst control device 120 as shown in Figure 6 partly overlapping.
Figure 10 is the buffer structure sketch map that is used for Tx burst control device 120 shown in Fig. 6.
Embodiment
In the middle of specification and follow-up claim, used some vocabulary to censure specific components.One of ordinary skill in the art can understand, and same assembly may be called with different nouns by manufacturer.This specification and follow-up claim are not used as distinguishing the mode of assembly with the difference of title, but are used as distinguishing criterion with the difference of assembly on function.Be to be open language mentioned " comprising " in the middle of specification and the follow-up request terms in the whole text, so should be construed to " comprise but be not limited to ".In addition, " coupling " speech is to comprise any indirect means that are electrically connected that directly reach at this.By the narration of following specific embodiment and cooperate Fig. 1 to Figure 10 of full text that the present invention is described, but the device in the following narration, assembly and method, step are in order to explanation the present invention, and should not be used for limiting the present invention.
Describe below and realize specific embodiment of the present invention.Following description is for rule of the present invention is described, unintelligible is restriction to the present invention.Therefore protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Please refer to Fig. 3; Fig. 3 is according to the first embodiment of the present invention; The sketch map that in wireless communication system, is used to keep the efficient of system's frequency range and implements the device 100 of down link or uplink processing, wherein, wireless communication system can be for example WiMAX communication system; Device 100 among this embodiment comprises a control module 100M, and a baseband circuit 108.In this embodiment, at least a portion (for example, control module 100M and/or baseband circuit 108) can be an integrated circuit (Integrated Circuit, IC) the middle realization in the device 100.
Realize selecting for one according to the first embodiment of the present invention, device 100 can be represented wireless system, but the present invention is not as limit.Another realization according to first embodiment is selected, and device 100 can comprise wireless communication system.For instance, device 100 can be a multi-function device, comprises the function of mobile phone, personal digital assistant (Personal DigitalAssistant, function PDA), and WiMAX communication function.In another embodiment of the present invention, device 100 can be represented a part in the wireless communication system (for example, as shown in Figure 3 control module 100M).
According to the first embodiment of the present invention, control module 100M can comprise one group of PDU resolver, for example PDU resolver (parser) 112 and PDU resolver 122; At least one is shared ring buffer (sharing-ring buffer) and (for example, in an embodiment of the present invention, shares the ring buffer and can be embodied as the pool of buffer device; Be buffer 114 and buffer 124), a plurality of treatment circuits, for example treatment circuit 130; 140 and 150; And one connect identifier (Connection Identification, CID) table search engine (search engine) 160, and this CID table search engine 160 comprises CID table 162.As shown in Figure 3, PDU resolver 122 and buffer 124 all can be incorporated in the burst control device 120.
With reference to the first half of the control module 100M shown in the figure 3, buffer 114 comprises a plurality of buffer area 114R, and a plurality of buffer area 114R are used for the interim data of the continuous level of logic in corresponding wireless communication system Rx path respectively that store.As shown in Figure 3, the Rx path among this embodiment comprises data path R0, R1; ...; And R7, and above-mentioned a plurality of data path is corresponding with the order of the continuous level of logic in Rx path, wherein; And the treatment circuit 150 of this control module 100M can be couple to external memory storage through for example data path R7/T0, and baseband circuit 108 can be couple to the RF module through data path R0/T7.Along the Rx path, PDU resolver 112 is resolved one or more sub-cell (sub-unit) of the data that receive in the buffer area to a plurality of buffer area 114R of buffer 114, to form a plurality of PDU.For example, one or more bytes are stored temporarily in each buffer area among corresponding a plurality of buffer area 114R.
In addition, with reference to the latter half of the control module 100M among the figure 3, buffer 124 comprises a plurality of buffer area 124R, is respectively applied in the interim storage wireless communication system corresponding to the data of level continuously of the logic on the Tx path.As shown in Figure 3, the Tx path of this embodiment comprises a plurality of data path T0, T1 ..., and T7, wherein, above-mentioned a plurality of paths are corresponding with the order of continuous grade of the logic on the Tx path.Along the Tx path, PDU resolver 122 will be resolved one or more sub-cell from the data of a buffer area among a plurality of buffer area 124R of buffer 124, to form a plurality of PDU.For example, one or more bytes are stored temporarily in each buffer area of 124R in corresponding a plurality of buffer area, and these one or more bytes will be resolved by PDU resolver 122.In this embodiment, the data after PDU resolver 122 is resolved along data path T5 transmission, promptly a plurality of PDU are to treatment circuit 130.
According to first embodiment, realize the continuous level of logic on the Rx/Tx path that a plurality of treatment circuits 130,140 and 150 can be respectively applied in wireless communication system.The treatment circuit 130,140 and 150 of this embodiment is through the cyclic access buffer; Be a plurality of buffer area 114R of buffer 114; The continuous level of logic that can emulation Rx path, and treatment circuit 130,140 and 150 is simultaneously through the cyclic access buffer; It is the continuous level of a plurality of buffer area 124R and the logic in emulation Tx path of buffer 124; Buffer 1114 and buffer 124 comprise buffer 114 and buffer 124 owing to share the ring buffer, and the big I of buffer 114 and buffer 124 distribute as required, so can be considered access buffer capable of circulation.
In this embodiment more specifically, buffer 114 can be called the rx buffering device, and buffer 124 can be referred to as the Tx buffer.In addition, treatment circuit 130,140 and 150 can be through difference access rx buffering device; The a plurality of buffer area 114R that are buffer 114 are with the continuous level of the logic in emulation Rx path; Simultaneously also can be through difference access Tx buffer, promptly a plurality of buffer area 124R of buffer 124 are with the continuous level of the logic in emulation Tx path, wherein; Treatment circuit 130,140 and 150 does not need the serial running.
Illustrate; With reference to the Rx path, begun at treatment circuit 130 after the running of discrete cell (for example, PDU) data; The first of the discrete cell of the data in the buffer area among a plurality of buffer area 114R of treatment circuit 140 beginning accesses; In order to begin the running to the discrete cell of data as early as possible, and need not wait for the completion of running, treatment circuit 130 can be implemented running to the discrete cell of data.
Similar; Still with reference to the Rx path, after treatment circuit 140 began the running to the discrete cell of data, treatment circuit 150 can begin access from the first of the discrete cell of one data among a plurality of buffer area 114R (more specifically; A buffer area among the 114R of buffer area); For the running of the discrete cell that begins data as early as possible, and need not wait for the completion of running, treatment circuit 140 can be implemented running to the discrete cell of said data.
Corresponding to the data path T7 in Tx path, T6 ..., and the running of T0 respectively with data path R0 corresponding to the Rx path, R1 ..., and the running of R7 is opposite, is described in this for Tx path similar and repeats no more.This scheme is compared the overall operation speed of the wireless communication system that can provide higher with prior art, therefore, the performance higher than prior art can be provided.
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the flow chart of the method 910 of the deal with data at wireless communication system according to an embodiment of the invention, and wherein, the running in the Rx path in method 910 flow charts and the wireless communication system is corresponding.Fig. 5 is the flow chart of the method 920 of the deal with data in the wireless communication system according to another embodiment of the invention, and wherein the flow chart of method 920 is corresponding to the running in the Tx path in the wireless communication system.Method 910 can be applied in the first embodiment of the present invention with method 920, and all available device shown in Figure 3 100 is realized.
Should be noted that, in method 910, at first in step 912; The rx buffering that comprises a plurality of buffer areas device is provided, and then, step 914-1 and step 914-2 be corresponding header check sequence (HeaderCheck Sequence respectively; HCS) detection running (is step 914-1; Effective HCS?) and CID detects running, and (be step 914-2, CID matees?), and above-mentioned running can be implemented in device 100.At step 914-1, PDU resolver 112 detects from the data that data path R2 receives, whether have effective HCS.If there is effective HCS really in 112 decisions of PDU resolver, controlling path C0 and C1 so will be activated, and get into step 914-2 then; Otherwise, will get into step 914-1 again, detect running to realize HCS.
At step 914-2, whether the CID of CID table search engine 160 decisions each from a plurality of PDU that control path C0 receives shows a CID coupling in the CID table 162 in the search engine 160 with CID.CID shows search engine 160, and path C1 sends to PDU resolver 112 with testing result through control.When any CID in the CID of each in receiving a plurality of PDU and the CID table 162 does not match, PDU resolver 112 will abandon a plurality of PDU that receive.If the CID of each among a plurality of PDU that receive all with CID table 162 in CID coupling; So among a plurality of buffer area 114R of data parsing to the buffer 114 of PDU resolver 112 a plurality of PDU that will receive; Get into step 916 then; That is a buffer area in a plurality of buffer areas of resolution data to rx buffering device; Otherwise, get into step 914-1 again.After execution of step 916, get into step 918, utilize a plurality of buffer areas of rx buffering device to correspond respectively to the logic data of level continuously in the Rx path of wireless communication system with interim storage.
Similar with the step in the method 910; Step in the method 920 (comprising step 922,924 and 926) all discloses in first embodiment; For succinctly, Fig. 5 is similar with the embodiment among Fig. 4 is described in this and repeats no more, and is the data processing method that is used on the Rx path but the difference of the method among Fig. 4 and among Fig. 5 is Fig. 4; And Fig. 5 is the data processing method that is used on the Tx path, thus with Fig. 4 in the step of the corresponding Fig. 5 of step be the running on the Tx path.
Fig. 6 is the actual system architecture sketch map of device 100 according to an embodiment of the invention, as shown in Figure 3, and wherein, this embodiment is a concrete embodiment of device 100 as shown in Figure 3.Control module 100M in this specific embodiment and install 100 can be called WiMAX MAC module 100M ' respectively and install 100 '.At this; Because burst control device 110 and burst control device 120 operate respectively on Rx path and Tx path; So burst control device 110 and burst control device 120 can be called Rx burst and Tx burst control device respectively, Rx burst control device and the Tx burst control device hereinafter mentioned among this embodiment then are referred to as Rx burst control device 110 and Tx burst control device 120, in addition; Buffer 114 among this embodiment and buffer 124 can use the FIFO memory to realize; So buffer 114 can be referred to as FIFO 114 again, and buffer 124 can be referred to as FIFO 124.Special, can comprise finite state machine (FiniteState Machine, the module that FSM) realizes in this embodiment in the PDU resolver 112 or 122.
In this embodiment, baseband circuit 108 can be implemented as WiMAX PHY circuit 108 ', WiMAX PHY circuit 108 ' can comprise the Rx analog-digital converter 108R and the Tx digital analog converter 108T that are respectively applied for data path R0 and T7 wherein.In addition; Above-mentioned treatment circuit 130,140 and 150 can be embodied as a medium access control physical layer interface respectively, promptly MAC-PHY interface 130 '; Security engine 140 ' and dma processor; For example line up administrative unit (Queue Management Unit, QMU)/DMA engine 150 ', hereinafter be referred to as QMU/DMA engine 150 '.QMU/DMA engine 150 among this embodiment ' (Advanced High-performance Bus AHB) is couple to external memory storage to see through senior high performance bus.
According to this embodiment of the invention, MAC-PHY interface 130 ' can be used at wireless communication system PDU resolver 112 and 122 being couple to baseband circuit, for example, and WiMAX PHY circuit 108 '.Security engine 140 ' can be used for the data encryption in Tx path, also can be used for the data decryption in Rx path.QMU/DMA engine 150 ' can be used for the data in relevant Rx path are written to the external memory storage of wireless communication system, also can be used for the data about the Tx path are read from the external memory storage of wireless communication system.In addition, the MAC-PHY interface 130 ' in the embodiment of the invention can synchronous operation or asynchronous running, and the security engine 140 in the embodiment of the invention ' can handle in real time, and perhaps processed offline, perhaps even can handle in real time simultaneously and processed offline.
In this embodiment; Above-mentioned shared ring buffer can be implemented as FIFO 114 and the FIFO 124 (FIFO 114 and FIFO 124 can be respectively applied for rx buffering device and Tx buffer in this embodiment) that mentions in the preceding text; And above-mentioned shared ring buffer can be used for storing multi-form data or at least one class of data; Wherein, share the ring buffer and comprise as shown in Figure 3 a plurality of buffer area 114R and a plurality of buffer area 124R.Consider that down link is handled and uplink processing can be by device 100 ' implement, detailed running will be explained below.
Under the situation that device 100 ' the enforcement down link is handled, MAC-PHY interface 130 ' can be used for reception input data, and the input data comprise at least one data burst, and be somebody's turn to do the input data storing in this shared ring buffer, to form storage data.More specifically, in the case, the input data storing is in FIFO114, to form storage data.In addition, security engine 140 ' capture this storage data from sharing ring buffer (for example, in the case FIFO 114); To form acquisition data; Decipher this acquisition data then, to form data decryption, wherein; The form of data decryption is the PDU form, and is stored in and shares ring buffer (for example in the case FIFO114).Special, the part of this storage data of ring buffer is shared in security engine 140 ' acquisition, to form acquisition data, deciphers acquisition data then, to form data decryption.These input data, this acquisition data and this data decryption in single burst is stored in (for example shares the ring buffer; FIFO114 in the case), and in this shared ring buffer can dynamically adjust for the space system that stores input data, acquisition data and data decryption distribution.In addition, dma processor, for example ring buffer (for example, FIFO114 in the case) is shared in QMU/DMA engine 150 ' can be used for access, to obtain data decryption and to be used for handling.
It is a plurality of PDU that PDU resolver 112 will be imported data parsing, then each PDU is stored among a plurality of buffer area 114R at least one.Special, PDU resolver 112 usefulness will import data and data decryption is resolved among a plurality of buffer area 114R that share in the ring buffer (for example, FIFO 114 in the case), to form a plurality of PDU.CID table search engine 160 can be used for determining a plurality of PDU each CID whether with CID table search engine 160 in a CID coupling.When any one CID in each CID and the CID table among a plurality of PDU does not match, PDU resolver 112 will abandon said a plurality of PDU.For instance, the CID table can use above-mentioned CID table 162 to realize.CID table search engine 160 is used to determine the input data of oneself, the CID of each among promptly a plurality of PDU whether with CID table 162 in a coupling.When CID and any one CID in the CID table 162 of input data do not match, the PDU resolver will abandon the input data, and promptly a plurality of PDU encircle in the buffer and it is not stored into to share.
Note that; The CID of each of a plurality of PDU of CID search engine 160 decision whether with CID table search engine 160 in the CID table in the running of CID coupling after; The running of ring buffer (for example, in the case FIFO 114) is shared in 160 accesses of CID search engine.Whether PDU resolver 112 further detects HCS, effective with a plurality of PDU that decision receives.Typically; Whether PDU resolver 112 detects correct HCS and is present in each among a plurality of PDU; Detect each the CRC designator (indicator) among a plurality of PDU simultaneously, then, when only each among a plurality of PDU comprises the CID of HCS correctly and coupling; A plurality of PDU are stored into share ring buffer (for example, in the case FIFO 114).
Note that, MAC-PHY interface 130 ', security engine 140 ' and dma processor, the for example continuous level of logic on the Rx path of QMU/DMA engine 150 ' can be wireless communication system above-mentioned.According to this embodiment; Above-mentioned treatment circuit 130,140 and 150 can be implemented as the continuous level of these logics on the Rx path of wireless communication system respectively, wherein; Treatment circuit 130; 140 and 150 can be according to relevant Rx path partly overlapping the processing stage (phase), shares a plurality of buffer areas and the continuous level of the logic in emulation Rx path of ring buffer (for example, in the case FIFO 114) through access.
At device 100 ' implement under the situation of uplink processing, dma processor, QMU/DMA engine 150 ' can be used for receiving input data for example; And can be used for the input data storing to sharing the ring buffer; To form storage data, wherein, the form of input data is the PDU form.More specifically, dma processor, for example QMU/DMA engine 150 ' in the case can be with the input data storing in FIFO 124.In addition, security engine 140 ' can be used for capturing this storage data from sharing ring buffer (for example, FIFO 124 in the case) to form acquisition data, is encrypted acquisition data, to form enciphered data then.Wherein enciphered data can be stored into and share ring buffer (for example, FIFO 124 in the case), and enciphered data can convert the data burst form into before being stored into shared ring buffer.Special, security engine 140 ' from sharing the part of ring buffer acquisition storage data.Input data, acquisition data in a single burst; And enciphered data (for example can be stored in shared ring buffer; FIFO124 in the case) in, and the space system that in this shares the ring buffer, distributes for storage input data, acquisition data and enciphered data can dynamically adjust.
In addition, MAC-PHY interface 130 ' can be used for receives enciphered data from sharing ring buffer (for example, in the case FIFO124).Typically; MAC-PHY interface 130 ' (for example can be used for the shared ring of access buffer; FIFO124 in the case) obtaining enciphered data, being used for giving baseband circuit with encrypted data transmission, and baseband circuit may be embodied as in this embodiment WiMAX PHY circuit 108 '.Furtherly, PDU resolver 122 can be resolved and is stored in the data of sharing in the ring buffer, forming a plurality of PDU, and a plurality of PDU is stored at least one of a plurality of buffer areas of sharing ring buffer (for example, in the case FIFO124).
Note that dma processor, for example QMU/DMA engine 150 ', security engine 140 ' and MAC-PHY interface 130 ' can be the continuous level of logic on the Tx path in the wireless communication system above-mentioned.Routine in real time according to this; The continuous level of logic on the Tx path that above-mentioned treatment circuit 150,140 and 130 can be embodied as respectively in the wireless communication system; Wherein, treatment circuit 150,140 and 130 can be according to the pointer corresponding to partly overlapping processing stage the in relevant Tx path; Share ring buffer (for example, in the case FIFO 124) and the continuous level of logic on the emulation Tx path through access.
Fig. 7 is according to a specific embodiment among Fig. 6, other scheme S of Rx burst control device 110 as shown in Figure 6
Rx(j
Rx) partly overlapping the processing stage P
Rx(i
Rx) sketch map, wherein, in this special case, i
Rx=0,1,2,3 ..., or the like, j
Rx=0,1 ..., and N_j
RxWith N_j
RxEqual 2.In this embodiment, each scheme S
Rx(j
Rx) each the processing stage P
Rx(i
Rx), a plurality of buffer areas among the FIFO 114 in a plurality of frame representative graphs 7 of the dotted lines in the use FIFO.Wherein, The parameter of the buffer accesses of relevant a plurality of buffer areas; PHY WR represent MAC-PHY interface 130 ' write command; SEC_RD represent security engine 140 ' reading order, SEC_WR represent security engine 140 ' write command, DMA_RD represent QMU/DMA engine 150 ' reading order.In this embodiment; One or more sub-cell of the data of the PDU that receives (for example one or more byte); Be stored temporarily in each in corresponding a plurality of buffer area, through this operation, the transmission time the processing stage of from one to another processing stage can be very short.That is to say, MAC-PHY interface 130 ', security engine 140 ', and QMU/DMA engine 150 ' running respectively, can implement simultaneously, and need not to wait for the completion of whole processing of the PDU that comes from transmission each other.Therefore, the overall operation speed of wireless communication system can be higher than prior art.
Fig. 8 is the sketch map that is used for the buffer structure of Rx burst control device 110 shown in Figure 6, and wherein, buffer is FIFO 114.In this figure, the state that PDU state parameter PDU_Status1 in buffer 114 structures and PDU_Status0 represent PDU.It should be noted that PDU state parameter PDU_Status1 and PDU_Status0 comprise can (for example, the PDU resolver 112 by one or more assembly among the WiMAX MAC module 100M '; MAC-PHY interface 130 '; Security engine 140 ', with and/or QMU/DMA engine 150 ') change or updated information, so; Whether one of them assembly just can determine according to the PDU state parameter, the data among this PDU of beginning access.In addition, parameter GMH (Byte5), GMH (Byte4) ...; And GMH (Byte0) can be used to describe the versatile MAC header (Generic MAC Header, GMH), and above-mentioned parameter also can be used for storing HCS temporarily and detects the result of running and/or the result that CID detects running; Wherein, if original PDU does not detect running and/or CID detection running, parameter GMH (Byte5) through HCS; GMH (Byte4) ..., the content among the andGMH (Byte0); Then can use the GMH of another PDU directly to cover, wherein, Byte0-5 is a byte; And in various embodiment, the number of the byte of use can be different, and it depends on the needs of actual conditions.Therefore, their own accesses of PDU resolver 112 and/or security engine 140 ' can determine whether to begin to follow-up data.In addition, parameter K ey_idx can describe key indication (key index) of security engine 140 ' employed key (key), through this operation, and a plurality of schemes shown in Fig. 7 for example, execution that can be appropriate.And other parameter among Fig. 8, for example, Control representes control word, and PAYLOAD0-13 representes load data.
Fig. 9 is for another specific embodiment of providing according to Fig. 6, other scheme S of Tx burst control device 120 as shown in Figure 6
Tx(j
Tx) partly overlapping the processing stage P
Tx(i
Tx) sketch map, in this special case, i
Tx=0,1,2,3 ..., or the like, j
Tx=0,1,2 ..., and N_j
TxWith N_j
TxEqual 2.In this embodiment, each scheme
Tx(j
Tx) each the processing stage P
Tx(i
Tx), in FIFO (FIFO 124 for example shown in Figure 6), use a plurality of frames of dotted lines to represent a plurality of buffer areas among the FIFO 124 in Fig. 6.Wherein, The parameter of the buffer accesses of relevant a plurality of buffer areas; DMA_WR represent QMU/DMA engine 150 ' write command; SEC_RD represent security engine 140 ' reading order, SEC_WR represent security engine 140 ' write command, and PHY_RD represent MAC-PHY interface 130 ' reading order.In this embodiment, one or more sub-cell of PDU (for example, one or more byte) data is temporarily stored in relevant a plurality of buffer areas in each, will be very short between the transmission the processing stage of to another processing stage.That is to say, QMU/DMA engine 150 ', security engine 140 ', and MAC-PHY interface 130 ' running respectively almost can implement simultaneously, and need not wait for from each other the whole of PDU and finishing dealing with.Therefore, the operation rate of the integral body of wireless communication system is just higher than prior art.
Figure 10 is the buffer structure sketch map that is used for Tx burst control device 120 shown in Fig. 6, and wherein, buffer is FIFO 124.Because corresponding to the Tx path data path T7, T6 ..., and the running of T0; With the data path R0 corresponding to the Rx path, R1 ..., and the running of R7 is similar; So repeat no more for the similar description in Rx path here, special, the parameters R sv among Figure 10 representes subsequent use.
Should be noted that in first embodiment, though a buffer has been used in each path of wireless communication system (for example Rx path, perhaps Tx path), the present invention is not exceeded with the foregoing description.According to the distortion of first embodiment, can use more than a buffer in each path (for example Rx path, perhaps Tx path).According to another distortion of first embodiment, can share a buffer for Rx path and Tx path.
According to the other distortion of first embodiment, the size of each buffer area can change as required, to reach the use for the optimum of each buffer.
Different with prior art, the device in the embodiments of the invention can improve the operation rate of the integral body of wireless communication system with and related methods, and therefore, the device in the embodiments of the invention has more performance with and related methods than prior art.
Device in the embodiments of the invention with another beneficial effect of and related methods is, do not hinder the logic level running separately continuously on the Rx/Tx path in the wireless communication system, just can significantly reduce the scale of wireless communication system.
Though the present invention discloses as above with embodiment; Right its is not that any those skilled in the art are in spirit that does not break away from the present invention and scope in order to qualification the present invention; When can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (19)
1. in wireless communication system, implement the device that down link is handled for one kind, be used to keep the efficient of system's frequency range, it is characterized in that this device comprises:
Share the ring buffer, be used to store multi-form data;
The medium access control physical layer interface is used for receiving the input data, and wherein, these input data comprise at least one data burst, and this medium access control physical layer interface should be imported data storing and share in the ring buffer at this, to form storage data;
Security engine is used for sharing this storage data of ring buffer acquisition from this, forming acquisition data, and deciphers this acquisition data, forming data decryption, and this data decryption is stored in this shares in ring buffer; And
The direct memory access (DMA) processor is used for access and should shares the ring buffer to obtain this data decryption.
2. the device of in wireless communication system, implementing the down link processing according to claim 1 is characterized in that, this is shared ring buffer and comprises a plurality of buffer areas.
3. the device of in wireless communication system, implementing the down link processing according to claim 2 is characterized in that this device also comprises:
The protocol Data Unit resolver is couple to this and shares the ring buffer, and being used for this input data parsing is a plurality of protocol Data Units, and will these a plurality of protocol Data Units be stored at least one of this a plurality of buffer areas.
4. the device of in wireless communication system, implementing the down link processing according to claim 3 is characterized in that this device also comprises:
Connect the identifier list search engine, be couple to this a plurality of protocol Data Units, the connection identifier that is used for determining each connection identifier of these a plurality of protocol Data Units whether to be connected with this in connection identifier list of identifier list search engine is mated;
Wherein, when each this connection identifier in these a plurality of protocol Data Units was connected with this that any connection identifier does not all match in identifier list, then this protocol Data Unit resolver abandoned this a plurality of protocol Data Units.
5. the device of in wireless communication system, implementing the down link processing according to claim 4; It is characterized in that; This connect each connection identifier in these a plurality of protocol Data Units of identifier list search engine decision whether is connected in the identifier list with this should connections identifier coupling after, this connects the access of identifier list search engine and is somebody's turn to do the shared buffer that encircles.
6. the device of in wireless communication system, implementing the down link processing according to claim 5; It is characterized in that; This protocol Data Unit resolver detects whether correct header check sequence is present in each in these a plurality of protocol Data Units; And detect each the cyclic redundancy detection indicator in these a plurality of protocol Data Units; And only when in these a plurality of protocol Data Units each comprises the connection identifier of this correct header check sequence and this coupling, should a plurality of protocol Data Units be stored to this and share the ring buffer.
7. according to claim 1ly in wireless communication system, implement the device that down link is handled, it is characterized in that this security engine is shared the part of this storage data of ring buffer acquisition from this, forming this acquisition data, and decipher this acquisition data.
8. the device of in wireless communication system, implementing the down link processing according to claim 1; It is characterized in that; This storage data, this acquisition data and this data decryption are in single burst, and in this shares ring buffer, can dynamically adjust for storing the space that this storage data, this acquisition data and this data decryption distribute.
9. the device of in wireless communication system, implementing the down link processing according to claim 1; It is characterized in that; This medium access control physical layer interface, this security engine and this direct memory access (DMA) processor are the continuous levels of the logic on the RX path in this wireless communication system, and this device comprises:
A plurality of treatment circuits; Be couple to this and share the ring buffer; Be used for realizing the continuous level of this logic on this RX path of this wireless communication system, wherein, according to overlap the processing stage; A plurality of buffer areas that these a plurality of treatment circuits should be shared the ring buffer through access are with the continuous level of the logic of this RX path of emulation.
10. device of in wireless communication system, implementing uplink processing, this device is used to keep the efficient of system's frequency range, it is characterized in that this device comprises:
Share the ring buffer, be used to store multi-form data;
The direct memory access (DMA) processor is used for receiving the input data, and should import data storing and share the ring buffer to form storage data in this;
Security engine is used for sharing this storage data of ring buffer acquisition from this, with the formation acquisition data, and encrypts this acquisition data to form enciphered data, and wherein, this enciphered data is stored in this and shares the ring buffer; And
The medium access control physical layer interface is used for sharing the ring buffer from this and receives this enciphered data.
11. the device of in wireless communication system, implementing uplink processing according to claim 10 is characterized in that, this security engine is from the part that should share this storage data of ring buffer acquisition, forming this acquisition data, and encrypts this acquisition data.
12. the device of in wireless communication system, implementing uplink processing according to claim 11 is characterized in that, this is shared the ring buffer and comprises a plurality of buffer areas.
13. the device of in wireless communication system, implementing uplink processing according to claim 12 is characterized in that this device comprises:
The protocol Data Unit resolver is couple to this and shares the ring buffer, is used to resolve this storage data forming a plurality of protocol Data Units, and should be stored in this a plurality of buffer areas by a plurality of protocol Data Units.
14. the device of in wireless communication system, implementing uplink processing according to claim 10; It is characterized in that; This storage data, this acquisition data and this enciphered data are stored in this single burst of sharing the ring buffer, and in this shares ring buffer, can dynamically adjust for storing the space that this storage data, this acquisition data and this enciphered data distribute.
15. the device of in wireless communication system, implementing uplink processing according to claim 10; It is characterized in that; This direct memory access (DMA) processor, this security engine, and the continuous level of logic on this medium access control physical layer interface transmit path that is wireless communication system; It is characterized in that this device comprises:
A plurality of treatment circuits; Be couple to this and share the ring buffer; Be used to realize the continuous level of logic on this transmit path of this wireless communication system, these a plurality of treatment circuits wherein, according to counterpart overlapping the processing stage pointer; Through a plurality of buffer areas that access should be shared the ring buffer, the continuous level of the logic of this transmit path of emulation.
16. a data processing method in wireless communication system is characterized in that, this method comprises:
Provide and share the ring buffer, be used to store multi-form data;
Receive the input data, wherein these input data comprise at least one data burst, and should import data storing and share in the ring buffer to form storage data in this;
Share this storage data of ring buffer acquisition from this, to form acquisition data;
Decipher this acquisition data with the formation data decryption, and this data decryption is stored in this shared ring buffer; And
Access should be shared the ring buffer to obtain this data decryption.
17. according to claim 16 in wireless communication system data processing method, it is characterized in that this is shared ring buffer and comprises a plurality of buffer areas, and this method also comprises:
These input data and this data decryption are resolved to these a plurality of buffer areas that should share the ring buffer.
18. according to claim 17 in wireless communication system data processing method, it is characterized in that this method also comprises:
Whether detect header check sequence effective with these input data of confirming to receive;
Provide and connect identifier list and whether is connected in the identifier list connection identifier with the connection identifier of confirming these input data and matees with this; And
When this connection identifiers of this input data is connected with this that any connection identifier does not all match in identifier list, abandon this input data, share the ring buffer and should not import data storing in this.
19. a data processing method in wireless communication system is characterized in that, this method comprises:
Provide shared ring buffer to be used to store at least one type of data;
Receive the input data, wherein, the form of these input data is protocol data unit form, and should the input data storing share in the ring buffer to form storage data in this;
Share this storage data of ring buffer acquisition from this, to form acquisition data;
Encrypt this acquisition data, forming enciphered data, and this enciphered data is stored in this shares in ring buffer, wherein the form of this enciphered data is the data burst form; And
Access should be shared the ring buffer to obtain this enciphered data, was used for giving baseband circuit with this encrypted data transmission.
Applications Claiming Priority (2)
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|---|---|---|---|
| US12/276,420 | 2008-11-24 | ||
| US12/276,420 US20100131679A1 (en) | 2008-11-24 | 2008-11-24 | Apparatus for performing a downlink or uplink processing in a wireless communication system to maintain the efficiency of system bandwidth, and associated methods |
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| CN101742489A CN101742489A (en) | 2010-06-16 |
| CN101742489B true CN101742489B (en) | 2012-09-05 |
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| US (1) | US20100131679A1 (en) |
| CN (1) | CN101742489B (en) |
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| CN112685197B (en) * | 2020-12-28 | 2022-08-23 | 浪潮软件科技有限公司 | Interface data interactive system |
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| JP2985524B2 (en) * | 1992-08-18 | 1999-12-06 | 富士通株式会社 | Method for searching address recognition table of inter-LAN relay device |
| CN1402480A (en) * | 2001-08-07 | 2003-03-12 | 株式会社藤仓 | Method for managing address of medium access control bridge, and said bridge |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE10007602A1 (en) * | 2000-02-18 | 2001-08-30 | Siemens Ag | Transferring packet data information in radio communications system - involves transmitting identification information separated from associated data packet over same or specially dedicated channel |
| US7826466B2 (en) * | 2002-06-26 | 2010-11-02 | Atheros Communications, Inc. | Communication buffer scheme optimized for VoIP, QoS and data networking over a power line |
| CN101019405B (en) * | 2005-01-28 | 2011-09-28 | 美国博通公司 | Method and system for mitigating denial of service in a communication network |
| RU2491737C2 (en) * | 2006-03-31 | 2013-08-27 | Квэлкомм Инкорпорейтед | Memory management for high-speed medium access control |
| US20090252070A1 (en) * | 2007-01-12 | 2009-10-08 | Connors Dennis P | Airlink management in a wireless broadcast system |
| US20090323584A1 (en) * | 2008-05-27 | 2009-12-31 | Fujitsu Limited | Method and Apparatus for Parallel Processing Protocol Data Units |
-
2008
- 2008-11-24 US US12/276,420 patent/US20100131679A1/en not_active Abandoned
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- 2009-02-05 TW TW098103660A patent/TW201021492A/en unknown
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2985524B2 (en) * | 1992-08-18 | 1999-12-06 | 富士通株式会社 | Method for searching address recognition table of inter-LAN relay device |
| CN1402480A (en) * | 2001-08-07 | 2003-03-12 | 株式会社藤仓 | Method for managing address of medium access control bridge, and said bridge |
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| Title |
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| JP特开2000-253041A 2000.09.14 |
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| TW201021492A (en) | 2010-06-01 |
| CN101742489A (en) | 2010-06-16 |
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