CN101742281B - Demodulator device and demodulation method for reducing program clock reference jitter - Google Patents
Demodulator device and demodulation method for reducing program clock reference jitter Download PDFInfo
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Abstract
一种用于一数字电视接收器的解调制器装置，包括：一符号解交错器，以实施以符号为基础的解交错；一比特解交错器，以实施以比特为基础的解交错；一解映射器，以实施解映射；以及一维特比解码器，以实施维特比解码，其中该符号解交错器、该比特解交错器，以及该解映射器当中的一个包含一存储器以存储历经符号解交错的数据，以及该符号解交错器、该比特解交错器，以及该解映射器当中的另一个或该维特比解码器利用一经自适应最佳化的输送率来读取该历经符号解交错的数据。
A demodulator device for a digital television receiver comprises: a symbol deinterleaver for performing symbol-based deinterleaving; a bit deinterleaver for performing bit-based deinterleaving; a demapper for performing demapping; and a Viterbi decoder for performing Viterbi decoding, wherein one of the symbol deinterleaver, the bit deinterleaver, and the demapper comprises a memory for storing data subjected to symbol deinterleaving, and the other of the symbol deinterleaver, the bit deinterleaver, and the demapper or the Viterbi decoder reads the data subjected to symbol deinterleaving using an adaptively optimized transmission rate.
Description
Technical field
The present invention relates to a kind of rectification device, relate in particular to a kind of rectification device and a kind of rectification method that is used for a DTV receiver that is used for a DTV receiver (DIGITAL TV RECEIVER).
Background technology
Digital video broadcast-terrestrial (Digital Video Broadcasting-Terrestrial; DVB-T) standard is a kind of DVB Europe association criterion that is used for the broadcast transmitted (Broadcast Transmission of DigitalTerrestrial Television) of terrestrial DTV.The OFDM modulation (being COFDOM) that the utilization of this system has serial connection channel coding (Concatenated Channel Coding) transmits a compressed digital video/audio stream.And the source coding method that it adopted for example, is (the Moving Picture Experts Group of Motion Picture Experts Group; MPEG) standard, code name 2 (being commonly referred to as " MEPG-2 "), this standard is defined by the ISO/IEC 13818-1:1996 standard that ISO/IEC issued.
One mpeg 2 transport stream involves the video/audio message transmission in length is the transmission stream packets of 188 bits.Each grouping comprises a header (Head), and it comprises control information, and comprises a payload (Payload), and this payload comprises image or acoustic information.This mpeg 2 transport stream can carry a plurality of different programs simultaneously.Each grouping in the transport stream is by a packet identification sign indicating number (Packet Identifier who is contained in this header; PID) be associated with a program.Whether the variable-length of this header comprises an adaptation hurdle (Adaptation Field) according to it and decides.This adapts to the hurdle and comprises control information, and this control information might not appear in each transmission stream packets.
Yet this mpeg 2 transport stream may manifest high PCR shake (PCR Jitter) situation because of different communication conditions, so influence the operation in mpeg decoder or the processor.The conventional art that is used for reducing the PCR shake be utilize an extra PCR buffer with storage through demodulation symbol and exported with the rule order then.Yet required PCR buffer capacity may be quite big.For example, equal at 64 QAM and encoding rate under 7/8 the most abominable situation, the capacity of PCR buffer may be up to the 20*199*8*2=60160 bit.This causes the sky high cost in the VLSI practice.Therefore, the low-cost countermeasure that is used for reducing the PCR shake in a demodulator is subjected to height requirement.
Summary of the invention
At this a kind of demodulator device and rectification method are described, in order to reduce the PCR shake.
On the one hand, the invention provides a kind of demodulator device that is used for a DTV receiver comprises: a symbolic solution interleaver, in order to implement release of an interleave based on symbol, one bit deinterlacer, in order to implement release of an interleave based on bit, one de-mapping device, in order to implement to separate mapping, an and Viterbi decoder, in order to implement Veterbi decoding, this symbolic solution interleaver wherein, this bit deinterlacer, and in the middle of this de-mapping device one comprises a memory and goes through the staggered data of symbolic solution with storage, and this symbolic solution interleaver, this bit deinterlacer, and this is separated another or this Viterbi decoder in the middle of the mapping and utilizes and read this once the optimized transfer rate of self adaptation and go through the staggered data of symbolic solution.
On the other hand, the invention provides a kind of rectification method that is used for a DTV receiver, comprise: implement release of an interleave based on symbol, enforcement is based on the release of an interleave of bit, mapping is separated in enforcement, and enforcement Veterbi decoding, the staggered step of this symbolic solution wherein, this bit release of an interleave step, and this is separated in the middle of the mapping step one and comprises that storage goes through the staggered data of symbolic solution, and the staggered step of this symbolic solution, this bit release of an interleave step, and this is separated another or this Veterbi decoding step in the middle of the mapping step and comprises utilizing and read this once the optimized transfer rate of self adaptation and go through the staggered data of symbolic solution.
Below will in " execution mode ", describe above-mentioned and other features, aspect, and embodiment.
Description of drawings
According to various characteristics of the present invention, function and embodiment, all can be from above-mentioned detailed description, and reach preferable understanding with reference to the accompanying drawings simultaneously, these accompanying drawings comprise:
Fig. 1 is the embodiment that the example of the PCR shake in the transport stream reduces the signal graph of situation;
Fig. 2 is an embodiment of one of one receiver/demodulator device block schematic diagram;
Fig. 3 is an embodiment of a demonstration look-up table;
Fig. 4 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device;
Fig. 5 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device;
Fig. 6 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device;
Fig. 7 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device;
Fig. 8 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device;
Fig. 9 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device; And
Figure 10 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device.
[main element symbol description]
200～receiver 200a～RF (radio frequency)/digital units
200b～demodulator 202～antenna
204～tuner, 206～digital to analog converter device
208～synchronizer, 210～automatic gain controller
212～ejector, 214～fast Fourier transform unit
216～equalizer, 218～carrier phase and time tracker
220～symbolic solution interleaver, 2202～symbolic solution interlace memory
222～de-mapping device, 224～bit deinterlacer
226～Viterbi decoder 228～grouping deinterlacer
230～gift moral Solomon decoder, 232～descrambler
234～TPS decoder, 400～receiver
400b～demodulator 422～de-mapping device
4222～de-mapping device memory, 424～bit deinterlacer
500～receiver 500b～demodulator
522～de-mapping device, 524～bit deinterlacer
5242～bit release of an interleave memory, 526～Viterbi decoder
500～receiver 500b～demodulator
624～bit deinterlacer, 622～de-mapping device
700～receiver 700b～demodulator
720～symbolic solution interleaver, 722～de-mapping device
724～bit deinterlacer, 7242～bit release of an interleave memory
800～receiver 800b～demodulator
822～de-mapping device, 8242～de-mapping device memory
824～bit deinterlacer, 826～Viterbi decoder
900～receiver 900b～demodulator
920～symbolic solution interleaver, 9202～symbolic solution interlace memory
924～bit deinterlacer, 1000～receiver
1000b～demodulator 1020～symbolic solution interleaver
1024～bit deinterlacer, 10242～bit release of an interleave memory
1026～Viterbi decoder P
11-P
38: grouping
P
11'-P
38': grouping S
1-S
3: symbol
S
1'-S
3': transport stream S
TPS～TPS signal
T
11-T
37: time interval T
11'-T
37': time interval
T
S1-T
S3: symbol lengths T
S1'-T
S3': symbol lengths
T
P1-T
P3: symbol period T
P1'-T
P3': symbol period
Ts: transport stream Ts ': transport stream
Embodiment
Fig. 1 is the embodiment that the demonstration of the PCR shake in the transport stream reduces the signal graph of situation.In Fig. 1, a transport stream TS, promptly a mpeg transport stream can not have the rectification program that the PCR shake reduces operation through one.For example, this transport stream TS can be formed by the symbol S1-Sn of a sequence, and wherein n is an integer, and S1-Sn then does more detailed demonstration in the drawings.Each symbol Si () in the middle of these symbols S1-Sn can be further formed by the grouping Pil-Pim of a sequence, wherein for example, and m=8.As shown in scheming to understand, the pulse train (Burts) in the symbol S1-Sn, it is represented by time interval Tij respectively, can cause bigger PCR shake.If time interval Tij is big more, and then the shake of the PCR in the transport stream TS is big more.
Reduced in Fig. 1, the transport stream TS ' have the rectification program that the PCR shake reduces operation through, wherein time interval Tb1 to Tb3 is in transport stream TS ', so symbol S1 '-Sn ' presents more uniform distribution.Thus, transport stream TS ' PCR shake compare transport stream TS and promptly reduced.In addition, transport stream TS ' symbol lengths TS1 '-TS3 ' greater than the symbol lengths TS1-TS3 of transport stream TS, yet the symbol period of two transport stream TS and TS ' all equals TP1 to TP3.Be used for reducing the demonstration rectification program that PCR shakes according to one, can reduce time interval Tb1 to Tb3 by the symbol of once accepting bit deinterleave processing (bit-deinterleaving) of storing a sequence and the mode of utilizing a transfer rate (Throughput Rate) that reduces to read this symbol sebolic addressing then simply, more details will be in following description.
Fig. 2 is an embodiment of a block schematic diagram of one receiver/demodulator device.In Fig. 2, one receiver 200 can comprise one radio frequency/digital units 200a, it is in order to amplify and to change an analog radio-frequency signal to Base Band, wherein this analog radio-frequency signal can receive via an antenna 202, and the analog signal conversion of this amplification is become a digital signal, and a demodulator 200b, it is in order to carry out the rectification program.For example, receiver 200 can comprise a DVB-T receiver, and demodulator 200b can comprise an OFDM demodulator to carry out OFDM rectification program.
In Fig. 2, this radio frequency/digital units 200a can be configured to comprise a tuner (Tuner) 204, a digital to analog converter (ADC) 206, a synchronizer 208, and an automatic gain controller (Automatic Gain Controller; AGC) 210.Tuner 204 can be used to amplify this analog radio frequency (RF) signal that is received by this antenna 202, should be converted to a fundamental frequency signal through amplified analog signal, and filters this fundamental frequency signal.This ADC 206 can be used to change this fundamental frequency signal to this digital signal.This synchronizer 208 can be used to the combine digital signal processing, is picture synchronizationization, sign synchronizationization for example ... or the like similar program.This automatic gain controller (AGC) 210 can be used for controlling a gain of a receiving terminal to be fit to above-mentioned Digital Signal Processing.
In Fig. 2, OFDM demodulator 200b can be configured to and comprises an ejector (Eliminator) 212, a fast Fourier transform (Fast Fourier Transform; FFT) unit 214, one equalizer, 216, one carrier phases and time tracker 218, a symbolic solution interleaver (SymbolDeinterleaver) 220, a de-mapping device (Demapper), a bit deinterlacer (SymbolDeinterleaver) 224, a Viterbi decoder (Viterbi decoder) 226, one grouping deinterlacer (Packet Deinterleaver) (or being called external solution interleaver (external deinterleaver)) 228, one gift moral Saloman (Reed-Solomon; RS) decoder 230, and a descrambler (Descrambler) 232.This ejector 212 can be used for eliminating a protection (Guard Interval at interval; GI) with Cyclic Prefix (Cyclic Prefix; CP) signal, and this FFT unit 214 can be a frequency-region signal with a time domain conversion of signals.In addition, these equalizers 216 can remedy and amplify or distortion that transmission course caused, and this carrier phase and time tracker 218 phase place and time of can be used to follow the trail of a carrier wave.This symbolic solution interleaver 220 can provide a kind of at block fundamentally and based on the operation of the release of an interleave of symbol, and this de-mapping device 222 can be used for above-mentioned staggered and be converted to a simple bit stream by the symbol that a plurality of vectors (such as OPSK, 16QAM or 64QAM) are constituted through symbolic solution.And, this bit deinterlacer 224 can be used to provide the release of an interleave operation based on bit, that is, a kind of bit is (Bit-Wise) release of an interleave program one by one, and this Verterbi decoder 226 can be used to reverse once by the coded program of the performed mistake of one inside/convolution coder (Internal/Convolutional Coder) of a conveyer.This grouping deinterlacer 228 can comprise a convolution deinterlacer (ConvolutionalDeinterleaver), and this convolution deinterlacer is to carry out with the release of an interleave that is grouped into the basis to operate, that is the release of an interleave operation one by one of the bit within each grouping.This RS decoder 230 coded program of the performed mistake of a RS encoder in this conveyer once that can reverse.More specifically, this RS decoder 230 grouping that can produce 188 bits from the grouping of 204 bits that received.This descrambler 232 can be used for above-mentioned data through decoding are carried out descrambling, disperses to remove once energy performed in this conveyer, thereby recovers original successive bits stream.Therefore, this descrambler 232 successive bits stream that can be used for being recovered is provided as the final output stream of this demodulator 200b.
Symbolic solution interleaver 220 can comprise a symbolic solution interlace memory 2202 is gone through bit release of an interleave program with storage symbol.At this, de-mapping device 222 can receive the symbol of going through the symbolic solution cross-program and then these gone through the staggered symbol of symbolic solution and separate map operation from symbolic solution interlace memory 2202.When symbolic solution interleaver 220 finishes symbolic solution cross-program to a symbol, it can be with this example among the symbol of symbolic solution cross-program be stored in symbolic solution interlace memory 2202, and notice de-mapping device 222 go to begin to read and separate mapping this through the staggered symbol of symbolic solution.In the 8K pattern, de-mapping device 222 can take out 48 blocks finishing an OFDM symbol from symbolic solution interlace memory 2202, and in the 2K pattern, 222 of de-mapping devices take out 12 blocks to finish an OFDM symbol.Because each OFDM symbol can comprise 6048 data characters and then can comprise 1512 data characters in the 2K pattern in the 8K pattern, therefore de-mapping device 222 can utilize one to equal the transfer rate of 1/ (N*6048) and can utilize a transfer rate that equals 1/ (N*1512) to read symbolic solution interlace memory 2202 in the 2K pattern in the 8K pattern, wherein this parameter N can be a fixed integer, and this fixed integer is to decide according to system configuration and clock design, for example, can be fixed as 9.Yet, can increase this parameter N, that is N 9, to reduce transfer rate.As the relevant discussion of Fig. 1, reduce the interests that transfer rate causes the PCR shake to reduce.Under preferable situation, can be in symbolic solution interlace memory 2202 arbitraryly can by the next one under the condition that the staggered symbol of symbolic solution is covered is set up, transfer rate be minimized before symbolic solution interlace memory 2202 outputs from then on through the staggered symbol of symbolic solution.
Under the preferable situation, de-mapping device 222 makes its reading rate (being transfer rate) optimization adaptively, so that above-mentioned output stream through demodulation is more even, promptly has lower PCR shake, and the side is can adapt to all different transmission conditions.In order to reach this point, de-mapping device 222 can come its reading rate of optimization adaptively according to the transmission parameter of transport stream at least, so that demodulating process can provide best PCR shake to reduce effect.For example; in a DVB-T system, described transmission parameter can comprise number of pictures, troop (Constellation) (for example for QPSK, 16-QAM or 64-OAM), hierarchical information (Hierarchy Information) (these data are to encode with an additional parameter α under a normal or Hierarchy Mode), encoding rate (being 1/2,2/3,3/4,5/6,7/8 for example), protection (being 1/32,1/16,1/8,1/4 for example), transmission mode (being 2K or 8K for example) and unit marks (Cell Identification) at interval.Therefore, de-mapping device 222 can come its reading rate of optimization adaptively according at least one parameter in the middle of these parameters.For example, de-mapping device 222 can come its reading rate of optimization adaptively at interval according to transmission mode and protection.
In Fig. 2, OFDM demodulator 200b can also comprise a TPS (TransmissionParameter Signal (parameter signals)) decoder 234.This TPS decoder 234 can be used for receiving a frequency content from FFT214, the entrained information of specific carriers of this signal that recovery is received, and provide one to represent the TPS signal STPS of institute's recovering information to this de-mapping device 222.This information can comprise the transmission parameter of this transport stream STS.This descrambler 222 can come its reading rate of optimization adaptively according to the transmission parameter that this TPS signal STPS is carried then.
In order to reach the optimization of reading rate according to transmission parameter, this de-mapping device 222 can be with reference to a look-up table, this look-up table record corresponds to the transfer rate of different transmission parameter combination or the optimum value of parameter N, and wherein this optimum value provides best PCR to reduce effect.For example, this optimum value can obtain by reality test and measurement.In addition, this look-up table has all different practice modes.For example, this look-up table can be put into practice becomes a multiplexer.This multiplexer is configurable to be received this TPS signal and provides a rate controlled signal to become this optimum value with the reading rate of controlling this descrambler 232.
Fig. 3 is an embodiment of a demonstration look-up table.In Fig. 3, this look-up table can be used as de-mapping device 222 comes its reading rate of optimization adaptively at interval according to transmission mode and protection place, place.As shown in the figure, represent that corresponding to all available integer A of numerical value, B, the C of the parameter N of the combination of all transmission parameters wherein A, B and C represent 10,11 and 12 respectively, and all parameter N values all surpass a set value, are 9 for example.
At this, the reduction of transfer rate or minimize not necessarily requires to implement between symbolic solution interleaver 220 and mapper 222.Can only require is for going through reading the reduction of implementing output rating or minimizing of the staggered data of symbolic solution.
Fig. 4 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device.In Fig. 4, one receiver 400 can be similar to receiver 200 (in Fig. 2), just can comprise a demodulator 400b, wherein can between a de-mapping device 400b and a bit deinterlacer 424, implement the reduction of transfer rate or minimize, but not, implement the reduction of transfer rate or minimize at symbolic solution interleaver 220 and de-mapping device 222 as Fig. 2.For example, de-mapping device 422 can comprise a de-mapping device memory 4222 and separate the bit stream of mapping with the storage process, and wherein this once went through the symbolic solution cross-program through the bit stream of separating mapping in symbolic solution interleaver 220.Bit deinterlacer 424 can utilize once reducing or minimized transfer rate, comes to separate mapping memory 4222 from this and reads these through separating the bit stream of mapping.For example, bit deinterlacer 424 is its reading rate of optimization (being transfer rate) adaptively, or by reference one look-up table.For brevity, be the description of omitting all the other similar in Fig. 4 elements at this to the counter element of Fig. 2.
Fig. 5 is another embodiment of the block schematic diagram of example receiver/demodulator device.In Fig. 5, one receiver 500 can be similar to receiver 200 (in Fig. 2), just can comprise a demodulator 500b, wherein can between a bit deinterlacer 524 and a Viterbi decoder 526, implement the reduction of transfer rate or minimize, but not, implement the reduction of transfer rate or minimize at symbolic solution interleaver 220 and de-mapping device 222 as Fig. 2.For example, bit deinterlacer 524 can comprise a bit release of an interleave memory 5242 with the bit stream of storage through the bit release of an interleave, and wherein this bit stream through the bit release of an interleave was once gone through the symbolic solution cross-program in symbolic solution interleaver 220.Viterbi decoder 526 can utilize once reducing or minimized transfer rate, and coming from then on, bit release of an interleave memory 5242 reads these bit streams through the bit release of an interleave.For example, Viterbi decoder 526 is its reading rate of optimization adaptively, or by reference one look-up table.For brevity, be the description of omitting all the other similar in Fig. 5 elements at this to the counter element of Fig. 2.
Fig. 6 is another embodiment of the block schematic diagram of a demonstration receiver/demodulator device.In Fig. 6, one receiver 600 can be similar to receiver 200 (in Fig. 2), just can comprise a demodulator 600b, wherein the bit deinterlacer can be cooperated with each other with symbolic solution interleaver 220 toward reach and be become a so-called interior deinterlacer (Inner-deinterleaver).Symbolic solution interleaver 220 can comprise the symbol that a symbolic solution interlace memory 2202 interlocks through symbolic solution with storage, and bit deinterlacer 624 can utilize once reducing or minimized transfer rate, and coming from then on, symbolic solution interlace memory 6202 reads these through the staggered symbol of symbolic solutions.For brevity, be the description of omitting all the other similar in Fig. 6 elements at this to the counter element of Fig. 2.
Fig. 7 and 8 is other embodiment of the block schematic diagram of all the other demonstration receiver/demodulator devices.In Fig. 7 and 8, receiver 700 can be similar to receiver 200 (in Fig. 2) to 800, just can be respectively between bit deinterlacer 724 and de-mapping device 722, and implement the reduction of transfer rate between de-mapping device 822 and the Viterbi decoder 826 or minimize.For brevity, be the description of omitting Fig. 9 all the other elements similar at this to 10 to the counter element of Fig. 2.
Fig. 9 and 10 is other embodiment of the block schematic diagram of all the other demonstration receiver/demodulator devices.In Fig. 9 and 10, receiver 900 can be similar to receiver 200 (in Fig. 2) to 1000, and just de-mapping device 222 can be moved to respectively before symbolic solution interleaver 920 and 1020.For brevity, be the description of omitting Fig. 9 all the other elements similar at this to 10 to the counter element of Fig. 2.
In Fig. 2 to 10, transfer rate can be adjusted to ideal value adaptively, and the adaptivity that provides for the improvement of different transmission parameter is provided, thereby the PCR shake of improvement is provided.
Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appended claims person of defining.
Claims (13)
1. demodulator device that is used for a DTV receiver comprises:
One symbolic solution interleaver is in order to implement the release of an interleave based on symbol;
One bit deinterlacer is in order to implement the release of an interleave based on bit;
One de-mapping device is in order to implement to separate mapping; And
One Viterbi decoder is in order to implement Veterbi decoding; Wherein
One in the middle of this symbolic solution interleaver, this bit deinterlacer and this de-mapping device comprises a memory and goes through the staggered data of symbolic solution with storage;
Another or this Viterbi decoder in the middle of this symbolic solution interleaver, this bit deinterlacer and this de-mapping device is to utilize to read this once the optimized transfer rate of self adaptation and go through the staggered data of symbolic solution, wherein utilizes to read this through the optimized transfer rate of self adaptation and go through the staggered data of symbolic solution and be meant to reduce adaptively or minimize reading rate and read this and go through the staggered data of symbolic solution.
2. the demodulator device that is used for a DTV receiver as claimed in claim 1 wherein should be through the optimized transfer rate of self adaptation by deciding with reference to a look-up table.
3. the demodulator device that is used for a DTV receiver as claimed in claim 2; wherein this look-up table decides this through the optimized transfer rate of self adaptation according to a combination of transmission parameter; this transmission parameter comprises number of pictures, troops, hierarchical information, encoding rate, protection at interval, transmission mode, and unit marks.
4. the demodulator device that is used for a DTV receiver as claimed in claim 3 also comprises a parameter signals decoder, and it is in order to produce these transmission parameters and in order to provide these transmission parameters to this another person or to this Viterbi decoder.
5. the demodulator device that is used for a DTV receiver as claimed in claim 1, wherein this symbolic solution interleaver comprises this memory, and this de-mapping device reads these through the staggered data of symbolic solution from this memory.
6. the demodulator device that is used for a DTV receiver as claimed in claim 1, wherein this de-mapping device comprises this memory, and this Viterbi decoder system is from this memory read staggered data of symbolic solution of learning from else's experience.
7. the demodulator device that is used for a DTV receiver as claimed in claim 1, wherein this de-mapping device comprises this memory, and this bit de-interleaver is from this memory read staggered data of symbolic solution of learning from else's experience.
8. the demodulator device that is used for a DTV receiver as claimed in claim 3, wherein this bit deinterlacer comprises this memory, and this Viterbi decoder is from this memory read staggered data of symbolic solution of learning from else's experience.
9. the demodulator device that is used for a DTV receiver as claimed in claim 3, wherein this symbolic solution interleaver comprises this memory, and this bit deinterlacer is from this memory read staggered data of symbolic solution of learning from else's experience.
10. the demodulator device that is used for a DTV receiver as claimed in claim 1, wherein this bit deinterlacer comprises this memory, and this de-mapping device system is from this memory read staggered data of symbolic solution of learning from else's experience.
11. a rectification method that is used for a DTV receiver comprises:
Enforcement is based on the release of an interleave of symbol;
Enforcement is based on the release of an interleave of bit;
Mapping is separated in enforcement; And
Implement Veterbi decoding,
The staggered step of this symbolic solution wherein, this bit release of an interleave step, and this is separated in the middle of the mapping step one and comprises that storage goes through the staggered data of symbolic solution, and the staggered step of this symbolic solution, this bit release of an interleave step, and this separates another or this Veterbi decoding step in the middle of the mapping step and comprises utilizing and read this once the optimized transfer rate of self adaptation and go through the staggered data of symbolic solution, wherein utilizes to read this through the optimized transfer rate of self adaptation and go through the staggered data of symbolic solution and be meant to reduce adaptively or minimize reading rate and read this and go through the staggered data of symbolic solution.
12. rectification method as claimed in claim 11, wherein this of this read step decides by reference one look-up table through the optimized transfer rate of self adaptation.
13. rectification method as claimed in claim 12; wherein this look-up table is provided to decide this through the optimized transfer rate of self adaptation according to a combination of transmission parameter; this transmission parameter comprises number of pictures, troops, hierarchical information, encoding rate, protection at interval, transmission mode, and unit marks.
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| CN1625839A (en) * | 2002-02-01 | 2005-06-08 | 皇家飞利浦电子股份有限公司 | Phase-locked-loop with reduced clock jitter |
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| CN1625839A (en) * | 2002-02-01 | 2005-06-08 | 皇家飞利浦电子股份有限公司 | Phase-locked-loop with reduced clock jitter |
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