CN101740460B - Forming method of shallow trench isolation area and manufacturing method of NMOS (N-Mental-Oxide-Semiconductor) transistor - Google Patents

Forming method of shallow trench isolation area and manufacturing method of NMOS (N-Mental-Oxide-Semiconductor) transistor Download PDF

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CN101740460B
CN101740460B CN2008102263862A CN200810226386A CN101740460B CN 101740460 B CN101740460 B CN 101740460B CN 2008102263862 A CN2008102263862 A CN 2008102263862A CN 200810226386 A CN200810226386 A CN 200810226386A CN 101740460 B CN101740460 B CN 101740460B
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semiconductor substrate
groove
grid
manufacturing approach
megohmite insulant
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CN101740460A (en
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居建华
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Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

The invention discloses a forming method of a shallow trench isolation area and a manufacturing method of an NMOS (N-Mental-Oxide-Semiconductor) transistor, wherein the forming method of the shallow trench isolation area comprises the following steps of: providing a semiconductor substrate; etching the semiconductor substrate to form a trench; filling an insulating material in the trench; annealing, wherein the annealing temperature is smaller than 1000 DEG C; and flattening and exposing the semiconductor substrate. In the invention, the annealing temperature is adjusted in the annealing step after the step of filling the insulating material in the trench, thereby reducing the pressure stress of the filled insulating material to the side walls of the trench, also reducing the pressure stresses of a drain electrode area and a conducting channel, and reducing the drain current of flowing to the semiconductor substrate from the drain electrode area of an MOS (Mental-Oxide-Semiconductor) device.

Description

The formation method of shallow channel isolation area and the manufacturing approach of nmos pass transistor
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of shallow channel isolation area and a kind of manufacturing approach of nmos pass transistor.
Background technology
In semiconductor fabrication,, between the different semiconductor device on the Semiconductor substrate, form shallow channel isolation area (STI) usually in order to make electric insulation between the different semiconductor device of making on the Semiconductor substrate.The formation method of STI generally includes: etching groove on Semiconductor substrate at first; In groove, fill dielectric; In groove, filling expires, and carries out rapid thermal treatment (RTP) then and makes insulating medium layer finer and close, and the stress in the dielectric in the groove is evenly distributed; Then carry out planarization, the dielectric on the removal Semiconductor substrate and the dielectric at groove top up to exposing Semiconductor substrate, make Semiconductor substrate and groove top be in same plane, thereby form STI.
For example on open be: on June 13rd, 2007, notification number is: CN1979798, name is called: in the one Chinese patent application of the process of realization STI, disclose the process of a kind of STI of realization.As shown in Figure 3, adopt existing STI technology, may further comprise the steps at least: shallow trench 10 etchings, 20 deposits of high-density plasma film, CMP grind; Wherein, after the deposit of high-density plasma film, append the rete 30 of growth one deck planarization, and then heat-treat, implement CMP after heat-treating again and grind.
Yet in semiconductor fabrication; Size of semiconductor device reduces gradually; The critical dimension of grid reduces gradually, the grid shorter and shorter more and more narrow that becomes, the shorter and shorter and more and more narrow that also becomes of the conducting channel between source area and the drain region in the Semiconductor substrate under the grid; Yet in to the test of the semiconductor device that utilizes the said method manufacturing, find dwindling along with device size; The leakage current that flows to Semiconductor substrate from the drain region of MOS device increases gradually, Fig. 1 and Fig. 2 experimental data for the nmos device that adopts the prior art manufacturing is tested, and abscissa is active area (AA) overall width of conducting channel length direction among Fig. 1; Ordinate is the leakage current that the drain region of nmos device flows to matrix, the nmos device that curve 720 is made for the method for utilizing prior art.Abscissa is active area (AA) overall width of conducting channel Width among Fig. 2, and ordinate is the leakage current that the drain region of nmos device flows to Semiconductor substrate, the nmos device that curve 820 is made for the method for utilizing prior art.The leakage current that flows to Semiconductor substrate through the drain region of testing the nmos device of finding the manufacturing of employing prior art is very big; Especially in conducting channel length less than 0.06um; The conducting channel width is less than more obvious in the nmos device of 0.5um, and said leakage current makes the degradation of MOS device.
Summary of the invention
In order to address the above problem, the invention provides a kind of formation method of shallow channel isolation area, reduced the leakage current that MOS device source polar region or drain region flow to Semiconductor substrate, improved the performance of semiconductor device.
The formation method of a kind of shallow channel isolation area of the present invention comprises step: Semiconductor substrate is provided; The Semiconductor substrate etching is formed groove; In groove, fill megohmite insulant; Anneal, annealing temperature is less than 1000 degree; Carry out planarization, expose Semiconductor substrate.
Optional, annealing temperature is that 0 degree is to 500 degree.
Optional, in groove, fill the megohmite insulant step and comprise: the trench liner oxide skin(coating) that forms covering groove sidewall and bottom surface; Deposit fill oxide layer is filled oxide skin(coating) up to groove and covers.
Optional, said deposit fill oxide layer utilizes low-pressure chemical vapor phase deposition.
Corresponding the present invention also provides a kind of manufacturing approach of nmos pass transistor, comprises step:
Semiconductor substrate is provided;
The Semiconductor substrate etching is formed groove;
In groove, fill megohmite insulant;
Below 1000 degree, anneal;
Carry out planarization, expose Semiconductor substrate,
On Semiconductor substrate, form grid, in the Semiconductor substrate of grid both sides, form source area and drain region.
Optional, the width of grid is less than or equal to 65nm.
Optional, annealing temperature is that 0 degree is to 500 degree.
Optional, in groove, fill the megohmite insulant step and comprise: the trench liner oxide skin(coating) that forms covering groove sidewall and bottom surface; Deposit fill oxide layer is filled oxide skin(coating) up to groove and covers.
Optional, said deposit fill oxide layer utilizes low-pressure chemical vapor phase deposition.
The advantage of technique scheme is:
An above-mentioned technical scheme is filled in groove in the annealing steps after the dielectric step; The temperature of adjustment annealing; Thereby reduce the compression of the interior dielectric of groove to trenched side-wall; Thereby reduced to flow to the leakage current of Semiconductor substrate, therefore improved the performance of semiconductor device from the drain region.
Description of drawings
Fig. 1 to Fig. 2 is the test data figure of the nmos pass transistor of the existing method manufacturing of utilization.
Fig. 3 is the formation method of a kind of STI in the prior art;
Fig. 4 is the flow chart of the formation method embodiment of shallow channel isolation area of the present invention;
Fig. 5 to Fig. 7 is the sketch map of the formation method embodiment of shallow channel isolation area of the present invention;
Fig. 8 is the flow chart of the manufacturing approach embodiment of nmos pass transistor of the present invention;
The nmos pass transistor structural representation that Fig. 9 forms for the present invention;
Figure 10 to Figure 11 is the test comparison diagram that utilizes formation the method nmos pass transistor of making and the nmos pass transistor that utilizes existing method to make of shallow channel isolation area of the present invention.
Embodiment
Usually in the forming process of STI, in groove, filled after the dielectric, can carry out annealing in process, made the dielectric in the groove finer and close, and reduce the uneven distribution of stress in dielectric dielectric.But,, think that dielectric has also increased the compression to trenched side-wall when becoming finer and close therefore through inventor's test because annealing can make dielectric finer and close.Because the zone between two adjacent trenches is an active area; Be used for making the MOS device; Therefore dielectric increases the compression of trenched side-wall; Just the compression to active area increases, thereby makes the compression between active area and the Semiconductor substrate increase, and the leakage current that the drain region of nmos device flows to Semiconductor substrate also increases.In large-sized MOS device, for example grid critical dimension is 90nm and above MOS device, because the conducting channel broad between source area and the drain region, longer; But along with size of semiconductor device reduces gradually, the critical dimension of grid reduces gradually, the grid shorter and shorter more and more narrow that becomes; The conducting channel shorter and shorter and more and more narrow that also becomes; Thereby find that through experiment the leakage current that the drain region of MOS device flows to Semiconductor substrate increases gradually, can find out from Fig. 1 and Fig. 2; To flow to the leakage current of Semiconductor substrate very big in the drain region of nmos device when grid critical dimension is less than or equal to 65nm, thereby make the MOS poor.
Therefore the invention provides a kind of formation method of shallow channel isolation area, comprise step: Semiconductor substrate is provided; The Semiconductor substrate etching is formed groove; In groove, fill megohmite insulant; Anneal, annealing temperature is less than 1000 degree; Carry out planarization, expose Semiconductor substrate.
Wherein, annealing temperature is that 0 degree is to 500 degree.
Wherein, in groove, filling the megohmite insulant step comprises:
Form the trench liner oxide skin(coating) of covering groove sidewall and bottom surface;
Deposit fill oxide layer is filled oxide skin(coating) up to groove and covers.
Wherein, said deposit fill oxide layer utilizes low-pressure chemical vapor phase deposition.
A kind of manufacturing approach of nmos pass transistor comprises step:
Semiconductor substrate is provided;
The Semiconductor substrate etching is formed groove;
In groove, fill megohmite insulant;
Below 1000 degree, anneal;
Carry out planarization, expose Semiconductor substrate,
On Semiconductor substrate, form grid, in the Semiconductor substrate of grid both sides, form source area and drain region.
Wherein, the width of grid is less than or equal to 65nm.
Wherein, annealing temperature is that 0 degree is to 500 degree.
Wherein, in groove, filling the megohmite insulant step comprises:
Form the trench liner oxide skin(coating) of covering groove sidewall and bottom surface;
Deposit fill oxide layer is filled oxide skin(coating) up to groove and covers.
Wherein, said deposit fill oxide layer utilizes low-pressure chemical vapor phase deposition.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.Owing to the present invention relates to the filling process of STI; Thereby in the following description; Processing step except that the STI filling step is only introduced in order to cooperate explanation method of the present invention, can not constitute the restriction to protection scope of the present invention, and; Below described processing step except that STI fills be not restricted to following description, also can adopt other technology of those skilled in the art institute convention.
Embodiment one
With reference to figure 4 to Fig. 7.
S110: Semiconductor substrate 100 is provided.
Semiconductor substrate 100 is provided, and said Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon; Said Semiconductor substrate 100 also can be silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate 100 can also have epitaxial loayer or insulating barrier silicon-on; Described Semiconductor substrate 100 can also be other semi-conducting material, enumerates no longer one by one here.
On Semiconductor substrate 100, have dielectric layer 101, this dielectric layer 101 is made up of silicon oxide liner bed course that on Semiconductor substrate 100, forms successively 102 and silicon nitride layer 103, and wherein silicon nitride layer 103 also can be the mixture of silicon nitride or silicon oxynitride.Silicon oxide liner bed course 102 is as the transition zone between Semiconductor substrate 100 and the silicon nitride layer 103, and its thickness can be 50 dusts-100 dust.Silicon nitride layer 103 has higher compactness extent, and the grinding that can be used as follow-up cmp (CMP) stops layer.The Semiconductor substrate 100 of the above-mentioned silicon nitride layer 103 of patterning to expose the respective grooves position.
S120: the Semiconductor substrate etching is formed groove 104.
Utilize silicon nitride layer 103 in substrate 100, to etch groove 104 as mask.Can be utilized in spin coating photoresist layer on the Semiconductor substrate 100, the patterning photoresist layer exposes the Semiconductor substrate 100 of the position of respective grooves 104 then, utilizes the photoresist layer of patterning in substrate 100, to etch groove 104 as mask.
Said etching can utilize method well known to those skilled in the art to carry out etching, for example utilizes dry plasma etch.
S130: in groove 104, fill megohmite insulant 108.
In this step, can also comprise; At first form the trench liner oxide skin(coating) 106 of covering groove 104 sidewalls and bottom surface; Can adopt following method: cleaning and removing is removed the oxide in the groove 104; Place then in the high-temperature oxydation equipment, in groove 104 sidewalls and bottom growth one deck cushion oxide layer 106, thickness is 50 dusts-150 dusts; This cushion oxide layer 106 can better connect thereby make between groove 104 and the megohmite insulant 108 as the transition zone between megohmite insulant 108 and groove 104 sidewalls and the bottom.
Deposit megohmite insulant 108 in semiconductor substrate surface and groove all is filled full up to groove 104.Utilize low-pressure chemical vapor phase deposition (LPCVD), plasma vapor deposition (PCVD) method among the present invention, megohmite insulant 108 can be silica.For example in one embodiment of the invention, adopt the method for LPCVD, technological parameter is: reaction chamber pressure is 1 * 10 2Pa, reaction temperature is 600 degree-800 degree.Thermal decomposition TEOS under above-mentioned technological parameter, thus silicon dioxide (SiO generated 2).Because megohmite insulant 108 density that LPCVD higher pressure chemical vapor deposition (HPCVD) generates are little, so the compression of 108 pairs of groove 104 sidewalls of megohmite insulant in the groove 104 is less.Because the zone between two adjacent trenches 104 is an active area, be used for making the MOS device, therefore reduced 104 pairs of trenched side-walls of groove, the just compression of active area.
S140: below 1000 degree, anneal.
Below 1000 degree, for example 800 degree, 500 degree, 300 degree, 200 degree, 100 degree, 50 degree, 30 degree are annealed, and can utilize short annealing, stove thermal annealing etc. after the deposit megohmite insulant 108.Utilize rapid thermal annealing in the present embodiment, technological parameter is: annealing temperature is 0 degree-100 degree, and the time is 0-10 minute.Annealing steps can be adjusted the distribution of the molecule of megohmite insulant 108; Make megohmite insulant 108 finer and close; Stress distribution is more even; Therefore but too high annealing temperature makes that the compactness extent of megohmite insulant 108 is excessive, makes that the compression of 108 pairs of groove 104 sidewalls of megohmite insulant in the groove 104 is also very big.Because the zone between two adjacent trenches 104 is an active area, be used for making the MOS device, therefore also just increased the compression of 104 pairs of active areas of groove.So adopted lower annealing temperature among the embodiment, thereby the compactness extent of megohmite insulant 108 reduced, thereby reduced the compression of 104 pairs of active areas of groove.
In general; For nmos pass transistor; Between drain region and Semiconductor substrate, have leakage current, and have the compression between drain region and the Semiconductor substrate can increase said leakage current, so the present invention is through reducing the compression of 104 pairs of active areas of groove; Thereby also just reduced the compression between drain region and the Semiconductor substrate, the leakage current that makes the drain region of nmos device flow in the Semiconductor substrate reduces.
S150: carry out planarization, expose Semiconductor substrate.
Semiconductor substrate 100 to having megohmite insulant 108 is carried out cmp (CMP); Remove megohmite insulant 108, silicon oxide liner bed course 102 and silicon nitride layer 103 on the Semiconductor substrate 100; Expose Semiconductor substrate 100, the top of groove 108 and Semiconductor substrate 100 are flushed.This step can adopt method well known to those skilled in the art to carry out.
In addition, the inventor also finds also can reduce the compression of the groove oppose side wall of STI, thereby reduce the leakage current of grid if cancel the step of annealing.
Embodiment two
With reference to figure 8 to Fig. 9.
The embodiment of the manufacturing approach of nmos pass transistor comprises the step of the formation STI of S110-S140, therefore repeats no more, and in addition also comprises step:
S160: on Semiconductor substrate 100, form grid 110, in the Semiconductor substrate of grid 110 both sides, form source area 112 and drain region 114.
The method that this step can adopt ability and technical staff to know, for example on Semiconductor substrate 100, the part between two adjacent S TI forms the grid layer on grid oxide layer and the grid oxide layer, grid layer and grid oxide layer is carried out etching, formation grid 110.The mode of utilizing ion to inject forms source area 112 and drain region 114.Thereby form nmos pass transistor shown in Figure 8.
Along with size of semiconductor device reduces gradually, the critical dimension of grid 110 reduces gradually, and for example for 65nm technology, the length of grid 110 is 65nm.Yet for the length of grid 110 is 65nm or less than the MOS device of 65nm, the length of the conducting channel 116 under the grid 110 has also narrowed down to and has been less than or equal to 0.06urm.Yet along with the shortening of conducting channel 116, especially for the nmos pass transistor of 65nm and following technology, STI makes the drain region of MOS device flow to the leakage current increase in the Semiconductor substrate to the stress of active area.
Figure 10 and Figure 11 experimental data for the nmos device that adopts prior art and manufacturing of the present invention is tested; Abscissa is active area (AA) overall width of conducting channel length direction among Fig. 9; Ordinate is the leakage current that the drain region of nmos device flows to Semiconductor substrate; The nmos device of curve 710 for utilizing method of the present invention to make, the nmos device that curve 720 is made for the method for utilizing prior art.Abscissa is active area (AA) overall width of conducting channel Width among Figure 10; Ordinate is the leakage current that the drain region of nmos device flows to Semiconductor substrate; The nmos device of curve 810 for utilizing method of the present invention to make, the nmos device that curve 820 is made for the method for utilizing prior art.Find to adopt the present invention to compare through test with prior art; The leakage current that the nmos device drain region of the nmos device of making flows to Semiconductor substrate descends greatly; Especially in conducting channel length less than 0.06um, this improvement is more obvious in the nmos device of conducting channel width less than 0.5um.
Therefore in the present embodiment; The length that the manufacturing approach of above-mentioned nmos pass transistor is applied to grid is less than or equal to 65nm; The width of grid is less than or equal in the manufacturing of nmos pass transistor of 650nm; Obtained improvement preferably for the nmos pass transistor of 65nm and following technology, the drain region that reduces nmos device greatly flows to the leakage current of Semiconductor substrate, has improved the characteristic of nmos pass transistor.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims (7)

1. the formation method of a shallow channel isolation area is characterized in that, comprises step:
Semiconductor substrate is provided;
The Semiconductor substrate etching is formed groove;
In groove, fill megohmite insulant;
Anneal, annealing temperature 0～100 degree, the time is 0～10 minute;
Carry out planarization, expose Semiconductor substrate.
2. manufacturing approach as claimed in claim 1 is characterized in that, in groove, fills the megohmite insulant step and comprises:
Form the trench liner oxide skin(coating) of covering groove sidewall and bottom surface;
Deposit fill oxide layer is filled oxide skin(coating) up to groove and covers.
3. manufacturing approach as claimed in claim 2 is characterized in that, said deposit fill oxide layer utilizes low-pressure chemical vapor phase deposition.
4. the manufacturing approach of a nmos pass transistor is characterized in that, comprises step:
Semiconductor substrate is provided;
The Semiconductor substrate etching is formed groove;
In groove, fill megohmite insulant;
Anneal at 0～100 degree, annealing time is 0～10 minute;
Carry out planarization, expose Semiconductor substrate,
On Semiconductor substrate, form grid, in the Semiconductor substrate of grid both sides, form source area and drain region.
5. manufacturing approach as claimed in claim 4 is characterized in that the width of grid is less than or equal to 65nm.
6. manufacturing approach as claimed in claim 4 is characterized in that, in groove, fills the megohmite insulant step and comprises:
Form the trench liner oxide skin(coating) of covering groove sidewall and bottom surface;
Deposit fill oxide layer is filled oxide skin(coating) up to groove and covers.
7. manufacturing approach as claimed in claim 6 is characterized in that, said deposit fill oxide layer utilizes low-pressure chemical vapor phase deposition.
CN2008102263862A 2008-11-14 2008-11-14 Forming method of shallow trench isolation area and manufacturing method of NMOS (N-Mental-Oxide-Semiconductor) transistor Expired - Fee Related CN101740460B (en)

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CN1649122A (en) * 2004-01-29 2005-08-03 台湾积体电路制造股份有限公司 Method for forming shallow trench isolation (STI) and its structure

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Publication number Priority date Publication date Assignee Title
CN1649122A (en) * 2004-01-29 2005-08-03 台湾积体电路制造股份有限公司 Method for forming shallow trench isolation (STI) and its structure

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