CN101739995B - Pin shared analog front end processing device and method for sharing pin - Google Patents
Pin shared analog front end processing device and method for sharing pin Download PDFInfo
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- CN101739995B CN101739995B CN2008101710676A CN200810171067A CN101739995B CN 101739995 B CN101739995 B CN 101739995B CN 2008101710676 A CN2008101710676 A CN 2008101710676A CN 200810171067 A CN200810171067 A CN 200810171067A CN 101739995 B CN101739995 B CN 101739995B
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Abstract
The invention relates to a pin shared analog front end processing device and a method for sharing a pin. The pin shared analog front end processing device comprises a plurality of positive terminal pins, a negative terminal pin, a plurality of positive terminal clamping circuits, a negative terminal clamping circuit, a plurality of sampling and holding circuits, and a plurality of alignment circuits. The positive terminal clamping circuits clamp each positive terminal signal to a corresponding target positive terminal voltage. The negative terminal clamping circuit clamps a negative terminal signal to a first reference voltage. Each sampling and holding circuit comprises a positive input terminal and a negative input terminal, and in a sampling period, the voltage difference between the two input terminals is that between the corresponding target positive terminal voltage and the first reference voltage; in a holding period, the voltage difference between the two input terminals is the voltage difference between the corresponding target negative terminal voltage and a second reference voltage.
Description
Technical field
The present invention relates to a kind of analog front end processing device and pin position method for sharing thereof of pin-sharing, relate in particular to a kind of DC potential of fixing all negative terminal signals in a reference voltage and the sampling of improvement inside and the analog front end processing device and the method for holding circuit.
Background technology
Display system chip such as TV, LCD Panel etc. comprise an analog front circuit usually, are used for converting analog signal (for example R, G, B) usefulness of digital signal for screen display to.On using; (single-ended) that signal is normally single-ended; And for the consideration of noise, the signal of display system chip is handled and can be adopted differential signal (differential signal), so must convert received single-ended signal to differential signal at chip internal.Because the DC potential of each signal is not quite similar, therefore can use the skill of AC coupling to let the alternating component of signal get into chip internal usually, and the DC potential of after coupling capacitance, rebuilding each signal again.
Common DC potential reconstruction mode is an example with the DC potential reconstruction mode of image signal; It is fixedly DC potential to the positive terminal voltage of pairing target of the anode signal of differential signal (for example R+, G+, B+) of elder generation; The DC potential of the negative terminal signal of each self trim differential signal (for example R-, G-, B-) so decides the DC potential of differential signal to pairing target negative terminal voltage again.Because the signal scope of the anode signal on each road is different; So the target negative terminal voltage of each road reference also can be different, therefore, the pin position of negative terminal signal can't be shared; There is several roads anode signal just to need the negative terminal pin position on several roads, also uneconomical in the consideration of cost.
Summary of the invention
One of the object of the invention is to provide a kind of pin position shared analog front end processing and pin position method for sharing thereof, to solve the problems of the prior art.
Embodiments of the invention have disclosed a kind of pin position shared analog front end processing, are used for receiving many to all anode signals in the differential signal and a negative terminal signal wherein.Analog front end processing device includes: a plurality of anode pins, a negative terminal pin, a plurality of anode clamp circuit, a negative terminal clamping circuit, a plurality of sampling and holding circuit and a plurality of adjustment circuit.A plurality of anode pins are used for receiving many a plurality of anode signals to differential signal respectively.The negative terminal pin is used for receiving that these are many to differential signal specific this negative terminal signal to differential signal wherein.A plurality of anode clamp circuits are respectively coupled to a plurality of anode pins, and the DC potential that is used for fixing a plurality of anode signals respectively is in the positive terminal voltage of a pairing target.Negative terminal clamping circuit is coupled to the negative terminal pin, and the DC potential that is used for fixing this negative terminal signal is in first reference voltage.Each sampling and holding circuit comprise a positive input terminal and a negative input end; Each sampling and holding circuit are in a sample period; Positive input terminal is the voltage difference of the positive terminal voltage of pairing target and first reference voltage with the pressure reduction of input negative terminal; And in a hold period, the pressure reduction of positive input terminal and negative input end is the voltage difference of the pairing target negative terminal voltage and second reference voltage.A plurality of adjustment circuit are respectively coupled to a plurality of samplings and holding circuit, are used for adjusting a plurality of samplings and holding circuit to pairing target negative terminal voltage respectively.Wherein, XOR is equal in fact mutually with this second reference voltage for first reference voltage.
Embodiments of the invention have disclosed a kind of method of pin position of common analog front end processing device, and this method includes: receive many to a plurality of anode signals in the differential signal; It is many to a differential signal specific negative terminal signal to differential signal wherein to receive this; The DC potential of fixing each anode signal is in the positive terminal voltage of pairing target respectively; The DC potential of fixing this negative terminal signal is in first reference voltage; A plurality of samplings and holding circuit are provided, and each sampling and holding circuit comprise a positive input terminal and a negative input end; In the sample period, the positive input terminal of each sampling and holding circuit is coupled to the positive terminal voltage of pairing target, and the negative input end of each sampling and holding circuit is coupled to first reference voltage; In a hold period, the positive input terminal of each sampling and holding circuit is coupled to pairing target negative terminal voltage, and this negative input end of each sampling and holding circuit is coupled to one second reference voltage; And these a plurality of samplings of adjustment and holding circuit to pairing target negative terminal voltage.
Description of drawings
Fig. 1 is the synoptic diagram of an embodiment of pin of the present invention position shared analog front end processing.
Fig. 2 (including Fig. 2 A and Fig. 2 B) for tradition sampling and holding circuit in the synoptic diagram of sample period and hold period.
Fig. 3 (including Fig. 3 A and Fig. 3 B) for sampling of the present invention and holding circuit in the synoptic diagram of sample period and hold period.
Fig. 4 is the process flow diagram of an example operation of the method for the pin position of common analog front end processing device of the present invention.
The reference numeral explanation
100 display system chips
105 printed circuit board (PCB)s
110 analog front end processing devices
R, G, the differential image signal of B
R+, G+, B+ anode signal
R-negative terminal signal
The C ac coupling capacitor
122,124,126 anode pins
128 negative terminal pins
132,134,136 anode clamp circuits
140 negative terminal clamping circuit
150 input buffers
152,212,222,232 positive input terminals
154,214,224,234 negative input ends
162,164,166 analog-digital converters
182,184,186 adjustment circuit
210,220,230 sampling and holding circuits
V
TG1+, V
TG2+, V
TG3+The anode target voltage
V
TG1-, V
TG2-, V
TG3-The negative terminal target voltage
V
REF1First reference voltage
V
REF2Second reference voltage
(V
Ip-V
In) input end pressure reduction
(V
Op-V
On) output terminal pressure reduction
402～440 steps
Embodiment
Please refer to Fig. 1, Fig. 1 is applied to the embodiment synoptic diagram of the analog front end processing device 110 of a display system for the present invention.DC potential reconstructing device wherein can be applicable to various differential signals, and the differential image signal that is applied to display system is merely the embodiment of one of them.Analog front end processing device 110 is arranged in the display system chip 100; Display system chip 100 receives many to differential image signal R, G, B; And utilize ac coupling capacitor C to let the alternating component of signal get into display system chips 100 inside by a printed circuit board (PCB) 105, and each respectively comprises an anode signal (that is R+, G+, B+) and a negative terminal signal (that is R-, G-, B-) to differential image signal.Analog front end processing device 110 is provided with a plurality of anode pins 122,124,126; Be used for receiving this many a plurality of anode signal R+, G+, B+ respectively to differential image signal; And a negative terminal pin 128, be used for receiving that these are many to a differential image signal specific negative terminal signal (for example R-) to differential image signal wherein.
Analog front end processing device 110 includes (but being not limited to) a plurality of anode clamp circuit 132～136, a negative terminal clamping circuit 140, a plurality of input buffer 150, a plurality of analog-digital converter 162～166, a plurality of sampling and holding circuit 210～230, a plurality of adjustment circuit 182～186, a reference voltage circuit 190; Wherein reference voltage circuit 190 is coupled to negative terminal clamping circuit 140 and a plurality of sampling and holding circuit 210～230, is used to provide one first reference voltage V
REF1Give negative terminal clamping circuit 140 and one second reference voltage V is provided
REF2Give a plurality of samplings and holding circuit 210～230.A plurality of anode clamp circuits 132～136 are respectively coupled to a plurality of anode pins 122～126, and the DC potential that is used for fixing each anode signal R+, G+, B+ respectively is in the positive terminal voltage of a pairing target.For example, anode signal R+ is fixed in the positive terminal voltage V of first target
TG1+, anode signal G+ is fixed in the positive terminal voltage V of second target
TG2+, and anode signal B+ is fixed in the positive terminal voltage V of the 3rd target
TG3+Negative terminal clamping circuit 140 is coupled to negative terminal pin 128, be used for fixing this to the DC potential of specific negative terminal signal R-to differential image signal in the first reference voltage V
REF1Each is somebody's turn to do the negative input end 154 that then can import each input buffer 150 to the negative terminal signal R-of specific differential image signal to the positive input terminal 152 that anode signal R+, G+, the B+ of differential image signal can input to pairing input buffer 150.
A plurality of samplings and holding circuit 210～230 are arranged at respectively among pairing numeral and the analog converter 162～166; Each sampling and holding circuit 210～230 respectively comprise a positive input terminal 212～232 and a negative input end 214～234; Each sampling and holding circuit 210～230 are in a sample period (sample period), and the pressure reduction of its positive input terminal and negative input end is the positive terminal voltage of pairing target (that is V
TG1+～V
TG3+) and the first reference voltage V
REF1Voltage difference, and in a hold period (hold period), the pressure reduction of its positive input terminal and negative input end is pairing target negative terminal voltage (that is V
TG1-～V
TG3-) and one second reference voltage V
REF2Voltage difference.For example, be example with sampling and holding circuit 210, in the sample period, positive input terminal 212 receives and is fixed in the positive terminal voltage V of first target
TG1+Anode signal R+, and negative input end 214 receives and is fixed in the first reference voltage V
REF1Negative terminal signal R-, both pressure reduction is (V
TG1+-V
REF1); In hold period, positive input terminal 212 receives and is fixed in the first target negative terminal voltage V
TG1-Signal, and negative input end 214 receives and is fixed in the second reference voltage V
REF2Signal, both pressure reduction is (V
TG1--V
REF2).182～186 in a plurality of adjustment circuit are respectively coupled to a plurality of samplings and holding circuit 210～230, are used for adjusting a plurality of samplings and holding circuit 210～230 respectively to pairing target negative terminal voltage V
TG1-～V
TG3-Last analog-digital converter 162～166 through separately again converts digital format with many to differential image signal R, G, B.
Note that the first above-mentioned reference voltage V
REF1Can equal the second reference voltage V
REF2, then in the sample period, the signal that sampling and holding circuit 210 are taken a sample is the voltage difference (V of the positive terminal voltage of pairing target and first reference voltage
TG1+-V
REF1), and in hold period, the signal of its output is the voltage difference (V of positive terminal voltage of pairing target and target negative terminal voltage
TG1+-V
TG1-), it can be learnt by following formula:
V
op-V
on＝(V
TG1+-V
REF1)-(V
TG1--V
REF1)
＝(V
TG1+-V
TG1-) (1)
Certainly, above-described embodiment only is used as example explanation of the present invention, is not restrictive condition of the present invention.In other embodiment, can adopt the first different reference voltage V
REF1With the second reference voltage V
REF2Put into practice disclosed analog front end processing device, this also belongs to the scope that the present invention is contained.Then in hold period, the signal of sampling and holding circuit 210～230 outputs is a variation value of gap (V only
REF2-V
REF1), can eliminate through simple DC potential translation.
Can know that by Fig. 1 three tunnel differential image signals of analog front end processing device 110 can shared same negative terminal pin 128.In the above embodiments, be to be example, but those skilled in the art should understand with differential image signal R, G, B, this is not a restrictive condition of the present invention, and the present invention also can be applicable to the image signal of extended formatting, for example Y, Pb, Pr.In addition, the number of differential image signal does not limit.For example, always total N is to differential image signal, and then disclosed DC potential reconstructing device only needs to be provided with (N+1) individual pin (comprising N anode pin and 1 negative terminal pin).
Note that above-described embodiment only is used as example explanation of the present invention, is not restrictive condition of the present invention.In other embodiment, also can adopt differential image signal G or B to come as this to specific differential image signal.Those skilled in the art should understand, and under spirit of the present invention, these various variations to specific differential image signal all are feasible.In addition, display system chip 100 can be a TV or a LCD Panel (LCD monitor), but the present invention is not limited thereto, also can be the display system chip of other kind.
Please refer to Fig. 2 and Fig. 3; Fig. 2 (including Fig. 2 A and Fig. 2 B) for tradition sampling and holding circuit in the synoptic diagram of sample period and hold period, Fig. 3 (including Fig. 3 A and Fig. 3 B) then is that sampling of the present invention and holding circuit are in the synoptic diagram of sample period and hold period.Shown in Fig. 2 A, in the sample period, tradition sampling and the positive input terminal of holding circuit and the pressure reduction (V of negative input end
Ip-V
In) be the voltage difference (V for example of positive terminal voltage of pairing target and pairing target negative terminal voltage
TG+-V
TG-); Shown in Fig. 2 B, in hold period, the pressure reduction (V of positive input terminal and negative input end
Ip-V
In) be 0.In other words, in the sample period, the signal of being taken a sample is (V
TG+-V
TG-), and in hold period, the signal (V of its output
Op-V
On) be the voltage difference (V of positive terminal voltage of pairing target and target negative terminal voltage
TG1+-V
TG1-), it can be learnt by following formula:
V
op-V
on＝(V
TG1+-V
REF1)-0
＝(V
TG1+-V
TG1-) (2)
Shown in Fig. 3 A, in the sample period, the pressure reduction (V of the positive input terminal of sampling of the present invention and holding circuit and negative input end
Ip-V
In) be the voltage difference (V for example of the positive terminal voltage of pairing target and first reference voltage
TG1+-V
REF1); Shown in Fig. 3 B, in hold period, the pressure reduction (V of positive input terminal and negative input end
Ip-V
In) be (V
TG1--V
REF2), as the first reference voltage V
REF1Equal the second reference voltage V
REF2The time, both pressure reduction are (V
TG1--V
REF1).Change speech, in the sample period, the signal of being taken a sample is (V
TG+-V
REF1), and in hold period, the signal (V of its output
Op-V
On) be the voltage difference (V of positive terminal voltage of pairing target and target negative terminal voltage
TG1+-V
TG1-) (can learn by above-mentioned formula (1)), identical with the tradition sampling of Fig. 2 with the resulting output signal of holding circuit.
Please refer to Fig. 4; Fig. 4 is the process flow diagram of an example operation of the method for the pin position of common analog front end processing device of the present invention; Its step that comprises below (but being not limited to) (please notes; If can obtain identical in fact result, then these steps might not be carried out in accordance with execution order shown in Figure 4):
Step 402: beginning.
Step 404: receive many to a plurality of anode signals in the differential image signal.
Step 406: the DC potential of fixing each anode signal is in the positive terminal voltage of pairing target respectively.
Step 408: receive that these are many to a differential image signal specific negative terminal signal to differential image signal wherein.
Step 410: the DC potential of fixing this negative terminal signal is in first reference voltage.
Step 412: a plurality of samplings and holding circuit are provided, and each sampling and holding circuit comprise a positive input terminal and a negative input end.
Step 414: in the sample period, the positive input terminal of each sampling and holding circuit is coupled to the positive terminal voltage of pairing target, and the negative input end of each sampling and holding circuit is coupled to first reference voltage.
Step 416: in hold period, the positive input terminal of each sampling and holding circuit is coupled to pairing target negative terminal voltage, and the negative input end of each sampling and holding circuit is coupled to second reference voltage.
Step 420: first reference voltage is provided.
Step 430: adjust a plurality of samplings and holding circuit to pairing target negative terminal voltage.
Step 440: provide second reference voltage to a plurality of samplings and holding circuit.
Next, with combining each step and each element shown in Figure 1 shown in Figure 4 to explain how each element operates.At first, a plurality of anode pins 122,124,126 receive many to each anode signal R+, G+, B+ (step 404) in the differential image signal respectively, and negative terminal pin 128 then receives this specific negative terminal signal R-(step 408) to differential image signal.Then, the DC potential of the fixing respectively a plurality of anode signal R+ of a plurality of anode clamp circuits 132～136, G+, B+ is in the positive terminal voltage V of pairing target
TG1+, V
TG2+, V
TG3+(step 406), negative terminal clamping circuit 140 then fixedly the DC potential of negative terminal signal R-in the first reference voltage V
REF1(step 410).In the sample period, the positive input terminal 212～232 of each sampling and holding circuit 210～230 is coupled to the positive terminal voltage V of pairing target
-TG1+, V
TG2+, V
TG3+, and the negative input end 214～234 of each sampling and holding circuit 210～230 is coupled to the first reference voltage V
REF1(step 414).And in hold period, the positive input terminal 212～232 of each sampling and holding circuit 210～230 is coupled to pairing target negative terminal voltage V
-TG1-, V
TG2-, V
TG3-, and the negative input end 214～234 of each sampling and holding circuit 212～230 is coupled to the second reference voltage V
REF2(step 416).In addition, the first reference voltage V
REF1And the second reference voltage V
REF2Be (step 420,440) to be provided, and a plurality of sampling and holding circuit 210～230th are adjusted to pairing target negative terminal voltage V by pairing adjustment circuit 182～186 by 190 of reference voltage circuits
-TG1-, V
TG2-, V
TG3-(step 430).
The step of above-mentioned flow process is merely the present invention and lifts feasible embodiment; And unrestricted restrictive condition of the present invention; And under the situation of spirit of the present invention, the method can also comprise other intermediate steps or can several steps be merged into one step, to do suitable variation.
Above-described embodiment only is used for technical characterictic of the present invention is described, is not to be used for limiting to category of the present invention.By on can know that the present invention provides a kind of pin position shared analog front end processing and pin position method for sharing thereof.DC potential through with all negative terminal signals all is fixed in first reference voltage; And this first reference voltage (perhaps second reference voltage) passed to simultaneously sampling and holding circuit and the improvement on each road, the signal that can let final sampling and holding circuit export still is the voltage difference (V for example of pairing anode target voltage and negative terminal target voltage
TG1+-V
TG1-).Thus, sampling is identical with the function of script with the signal that holding circuit is passed to next stage, and the DC potential that the differential image signal in each road can each self trim oneself.When always having N to differential signal, disclosed analog front end processing device only needs to be provided with (N+1) individual pin (comprising N anode pin and 1 negative terminal pin), to reach the purpose of saving pin and reducing cost.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (15)
1. pin position shared analog front end processing is used for receiving many to all anode signal of differential signal and a negative terminal signal wherein, and this analog front end processing device includes:
A plurality of anode pins are used for receiving this many a plurality of anode signals to differential signal respectively;
One negative terminal pin is used for receiving that these are many to differential signal specific this negative terminal signal to differential signal wherein;
A plurality of anode clamp circuits are respectively coupled to this a plurality of anode pins, and the DC potential that is used for fixing each anode signal is in the positive terminal voltage of a pairing target;
One negative terminal clamping circuit is coupled to this negative terminal pin, and the DC potential that is used for fixing this negative terminal signal is in one first reference voltage;
A plurality of samplings and holding circuit; Each sampling and holding circuit comprise a positive input terminal and a negative input end; Each sampling and holding circuit are in a sample period; The voltage difference of this positive input terminal and this negative input end is the voltage difference of the positive terminal voltage of pairing this target and this first reference voltage, and in a hold period, the voltage difference of this positive input terminal and this negative input end is the voltage difference of a pairing target negative terminal voltage and one second reference voltage; And
A plurality of adjustment circuit are respectively coupled to this a plurality of samplings and holding circuit, are used for respectively in this hold period, adjust this positive input terminal to pairing this target negative terminal voltage of these a plurality of samplings and holding circuit.
2. analog front end processing device as claimed in claim 1, wherein this first reference voltage and this second reference voltage are different.
3. analog front end processing device as claimed in claim 1, wherein this first reference voltage equates with this second reference voltage.
4. analog front end processing device as claimed in claim 3, wherein the signal in this hold period, exported of each sampling and holding circuit is the voltage difference of the positive terminal voltage of pairing this target and pairing this target negative terminal voltage.
5. analog front end processing device as claimed in claim 1, it also comprises:
One reference voltage circuit is coupled to this negative terminal clamping circuit and this a plurality of samplings and holding circuit, is used to provide this first reference voltage and gives this negative terminal clamping circuit and provide this second reference voltage to this a plurality of samplings and holding circuit.
6. analog front end processing device as claimed in claim 1, wherein this manyly comprises R, G, B signal to differential signal.
7. analog front end processing device as claimed in claim 1, wherein this manyly comprises Y, Pb, Pr signal to differential signal.
8. analog front end processing device as claimed in claim 1, wherein this many be the many of a display system to differential signal to differential image signal.
9. the method for a common analog front end processing device pin position, this method includes:
Receive many to a plurality of anode signals in the differential signal;
It is many to a differential signal specific negative terminal signal to differential signal wherein to receive this;
The DC potential of fixing each anode signal is in the positive terminal voltage of a pairing target respectively;
The DC potential of fixing this negative terminal signal is in one first reference voltage;
A plurality of samplings and holding circuit are provided, and each sampling and holding circuit comprise a positive input terminal and a negative input end;
In a sample period, this positive input terminal of each sampling and holding circuit is coupled to the positive terminal voltage of pairing this target, and this negative input end of each sampling and holding circuit is coupled to this first reference voltage;
In a hold period, this positive input terminal of each sampling and holding circuit is coupled to a pairing target negative terminal voltage, and this negative input end of each sampling and holding circuit is coupled to one second reference voltage; And
In this hold period, adjust this positive input terminal to pairing this target negative terminal voltage of these a plurality of samplings and holding circuit.
10. method as claimed in claim 9, wherein this first reference voltage and this second reference voltage are different.
11. method as claimed in claim 9, wherein this first reference voltage equates with this second reference voltage.
12. method as claimed in claim 11, it also comprises:
In this sample period, produce a sample signal, wherein this sample signal is the voltage difference of the positive terminal voltage of pairing this target and pairing this target negative terminal voltage.
13. method as claimed in claim 9, wherein this manyly comprises R, G, B signal to differential signal.
14. method as claimed in claim 9, wherein this manyly comprises Y, Pb, Pr signal to differential signal.
15. method as claimed in claim 9, wherein this many be the many of a display system to differential signal to differential image signal.
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| CN2008101710676A CN101739995B (en) | 2008-11-06 | 2008-11-06 | Pin shared analog front end processing device and method for sharing pin |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999017179A1 (en) * | 1997-09-29 | 1999-04-08 | Credence Systems Corporation | Multiple output programmable reference voltage source |
| JP3115108B2 (en) * | 1991-07-12 | 2000-12-04 | シュルンベルジェ テクノロジーズ， インコーポレイテッド | Pin driver / sensor reference voltage level setting device |
| CN101178886A (en) * | 2001-11-05 | 2008-05-14 | 三星电子株式会社 | Liquid crystal display and driving device thereof |
-
2008
- 2008-11-06 CN CN2008101710676A patent/CN101739995B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3115108B2 (en) * | 1991-07-12 | 2000-12-04 | シュルンベルジェ テクノロジーズ， インコーポレイテッド | Pin driver / sensor reference voltage level setting device |
| WO1999017179A1 (en) * | 1997-09-29 | 1999-04-08 | Credence Systems Corporation | Multiple output programmable reference voltage source |
| CN101178886A (en) * | 2001-11-05 | 2008-05-14 | 三星电子株式会社 | Liquid crystal display and driving device thereof |
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