CN101739962A - Drive circuit - Google Patents
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- CN101739962A CN101739962A CN200810174066A CN200810174066A CN101739962A CN 101739962 A CN101739962 A CN 101739962A CN 200810174066 A CN200810174066 A CN 200810174066A CN 200810174066 A CN200810174066 A CN 200810174066A CN 101739962 A CN101739962 A CN 101739962A
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Abstract
The invention provides a drive circuit which comprises a plurality of signal output end points, a digital signal generating module, a grey scale reference voltage generating module, a digital-to- analogue converter, a first multiplexing output module, an output buffer, a second multiplexing output module and a switch module. The invention can decrease the quantity of the required output buffers, thereby effectively reducing the area of the drive circuit and furthermore decreasing the production cost.
Description
Technical field
The present invention relates to a kind of driving circuit, relate in particular to a kind of one source pole driving circuit (source driver) that is applied in the display panels, this source electrode drive circuit can reduce the quantity of needed output buffer (output buffer), with the area that dwindles driving circuit effectively and and then reduce production costs.
Background technology
Please refer to Fig. 1, Fig. 1 illustrated for one of being applied in the display panels simplification block schematic diagram of source electrode drive circuit (source driver) 100 in the known technology.As shown in Figure 1, source electrode drive circuit 100 includes: a plurality of signal output part point S1～Sn, a data-signal generation module 110, a gray scale reference voltages generation module 120, a digital analog converter (digital-to-analogconverter, DAC) 130 and one output buffer and switch module 140.Data-signal generation module 110 is used for producing a plurality of digital data signal D1～Dn, and gray scale reference voltages generation module 120 is used for producing a plurality of gray scale reference voltages, and digital analog converter 130 is coupled to data-signal generation module 110 and gray scale reference voltages generation module 120, and be used for according to these a plurality of gray scale reference voltages to produce a plurality of voltage signal A1～An respectively corresponding to a plurality of digital data signal D1～Dn, and digital analog converter 130 includes a plurality of analog output point (not shown)s, is used for exporting a plurality of voltage signal A1～An respectively.Wherein, data-signal generation module 110 also includes: a shift register (shift register), a line latch (line latch) and a level shifter (levelshifter), because data-signal generation module 110 is well known to those skilled in the art, therefore for the sake of brevity, do not add to give unnecessary details the details of operation of data-signal generation module 110 at this.
Please refer to Fig. 2, Fig. 2 illustrated is the output buffer among Fig. 1 and the simplification circuit diagram of switch module 140.As shown in Figure 2, output buffer and switch module 140 include a plurality of on-off element SWg1～SWgn, a plurality of on-off element SWp1～SWpn and a plurality of output buffer B1～Bn, wherein, a plurality of on-off element SWg1～SWgn and a plurality of on-off element SWp1～SWpn are respectively coupled between a plurality of voltage signal A1～An and a plurality of signal output part point S1～Sn of digital analog converter 130, and a plurality of output buffer B1～Bn are respectively coupled between a plurality of voltage signal A1～An and a plurality of on-off element SWp1～SWpn of digital analog converter 130, in addition, a plurality of on-off element SWg1～SWgn are controlled by switch controlling signal GM_EN respectively, and a plurality of on-off element SWp1～SWpn is controlled by switch controlling signal PB_EN respectively.
Then, please refer to Fig. 3, what Fig. 3 illustrated is at 2 period T1, the voltage level change synoptic diagram of the sequential chart of switch controlling signal PB_EN and switch controlling signal GM_EN and a plurality of signal output part point S1～Sn among the T2, because a plurality of on-off element SWg1～SWgn and a plurality of on-off element SWp1～SWpn are N type field-effect transistor (for example NMOS field-effect transistor), therefore, as shown in Figure 3, in period T1, switch controlling signal PB_EN is that high logic level is with a plurality of on-off element SWp1～SWpn conducting, and switch controlling signal GM_EN be low logic level with not conducting of a plurality of on-off element SWg1～SWgn, make voltage signal A1～An by a plurality of output buffer B1～Bn the voltage level of a plurality of signal output part point S1～Sn to be drawn high near VGSy1～VGSyn from VGSx1～VGSxn respectively respectively thus; Then, in period T2, switch controlling signal PB_EN transfers low logic level to not conducting of on-off element SWp1～SWpn, and switch controlling signal PB_EN2 and GM_EN1 transfer high logic level to a plurality of on-off element SWg1～SWgn conducting, make the voltage level of a plurality of signal output part point S1～Sn directly to be calibrated to VGSy1～VGSyn respectively by voltage signal A1～An (that is gray scale reference voltages) thus.
Yet, in this known technology since a plurality of signal output part point S1～Sn in each signal output part point all need an output buffer, can cause the quantity of needed output buffer too many, and make that the area of source electrode drive circuit 100 is excessive and production cost can't be reduced.
Summary of the invention
In view of this, one of purpose of the present invention is to provide a kind of quantity that can reduce needed output buffer (output buffer), with the area that dwindles driving circuit effectively and and then the driving circuit that reduces production costs, to solve the above problems.
According to claimed scope of the present invention; it discloses a kind of driving circuit; this driving circuit includes: and a plurality of signal output part points, a data-signal generation module, a gray scale reference voltages generation module, a digital analog converter (digital-to-analog converter, DAC), one first multi-power output (multiplex output module), an output buffer, one second multi-power output and a switch module.This data-signal generation module is used for producing a plurality of digital data signals; This gray scale reference voltages generation module is used for producing a plurality of gray scale reference voltages; This digital analog converter is coupled to this data-signal generation module and this gray scale reference voltages generation module, and is used for according to these a plurality of gray scale reference voltages to produce a plurality of voltage signals corresponding to these a plurality of digital data signals respectively; This first multi-power output cording has one first exit point and a plurality of first input end point, and these a plurality of first input end points receive these a plurality of voltage signals respectively, and wherein this first multi-power output is chosen in these a plurality of voltage signals one first specific voltage signal and exported this first specific voltage signal by this first exit point in one first period; This output buffer is coupled to this first exit point, and is used for producing one first specific drive signal according to this first specific voltage signal in this first period; This second multi-power output has a plurality of second exit points and one second input endpoint, wherein these a plurality of second exit points are coupled to this a plurality of signal output part points respectively, this second input endpoint receives this first specific drive signal, and this second multi-power output exports this first specific drive signal one first specific exit point in these a plurality of second exit points to one first signal specific exit point in this first period; And this switch module is coupled between this digital analog converter and this a plurality of signal output part points, and is used for exporting this first specific voltage signal to this first signal specific exit point being different from one second period of this first period.
Description of drawings
What Fig. 1 illustrated is the simplification block schematic diagram that is applied to the one source pole driving circuit (source driver) in the display panels in the known technology.
Fig. 2 illustrated is the output buffer among Fig. 1 and the simplification circuit diagram of switch module.
What Fig. 3 illustrated is switch controlling signal PB_EN and the sequential chart of switch controlling signal GM_EN and the voltage level change synoptic diagram of a plurality of signal output part point S1～Sn among 2 period T1, T2.
Fig. 4 illustrated is the simplification block schematic diagram that is applied to the one source pole driving circuit in the display panels according to one embodiment of the invention.
The simplification circuit diagram that Fig. 5 illustrated for first multi-power output among Fig. 4.
The simplification circuit diagram that Fig. 6 illustrated for second multi-power output among Fig. 4.
The simplification circuit diagram that Fig. 7 illustrated for the switch module among Fig. 4.
What Fig. 8 illustrated is 3 switch controlling signal PB_EN1～PB_EN3 and the sequential chart of 3 switch controlling signal GM_EN1～GM_EN3 and the voltage level change synoptic diagram of 3 signal output part point S1～S3 among 4 period T1～T4.
The simplification block schematic diagram that Fig. 9 illustrated for source electrode drive circuit in period T1.
The simplification block schematic diagram that Figure 10 illustrated for source electrode drive circuit in period T2.
The simplification block schematic diagram that Figure 11 illustrated for source electrode drive circuit in period T3.
The simplification block schematic diagram that Figure 12 illustrated for source electrode drive circuit in period T4.
[main element symbol description]
100: source electrode drive circuit
110: the data-signal generation module
120: the gray scale reference voltages generation module
130: digital analog converter
140: output buffer and switch module
S1～Sn: signal output part point
D1～Dn: digital data signal
A1～An: voltage signal
GM_EN, PB_EN: switch controlling signal
SWp1～SWpn, SWg1～SWgn: on-off element
T1, T2: period
B1～Bn: output buffer
400: source electrode drive circuit
410: the data-signal generation module
420: the gray scale reference voltages generation module
430: digital analog converter
440: the first multi-power outputs
450: output buffer
460: the second multi-power outputs
470: switch module
I1～In: first input end point
O: first exit point
I: second input endpoint
O1～On: second exit point
S1～Sn: signal output part point
D1～Dn: digital data signal
A1～An: voltage signal
PB_EN1～PB_ENn, GM_EN1～GM_ENn: switch controlling signal
SW11～SW1n, SW21～SW2n, SW31～SW3n: on-off element
T1～T4: period
Embodiment
In the middle of this instructions and appending claims, used some vocabulary to censure specific element, and those skilled in the art should understand, hardware manufacturer may be called same element with different nouns, this instructions and appending claims are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function, be an open term mentioned " including " in the middle of instructions and the appending claims in the whole text, so should be construed to " include but be not limited to ", in addition, " couple " speech and include any indirect means that are electrically connected that directly reach at this, therefore, be coupled to one second device if describe one first device in the literary composition, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other devices or connection means.
Please refer to Fig. 4, Fig. 4 illustrated is the simplification block schematic diagram that is applied to the one source pole driving circuit (source driver) 400 in the display panels according to one embodiment of the invention.As shown in Figure 4, source electrode drive circuit 400 includes: a plurality of signal output part point S1～Sn, a data-signal generation module 410, a gray scale reference voltages generation module 420, a digital analog converter (digital-to-analog converter, DAC) 430,1 first multi-power output (multiplex outputmodule), 440, one output buffer 450, one second multi-power output 460 and a switch module 470.Data-signal generation module 410 is used for producing a plurality of digital data signal D1～Dn, and gray scale reference voltages generation module 420 is used for producing a plurality of gray scale reference voltages, and digital analog converter 430 is coupled to data-signal generation module 410 and gray scale reference voltages generation module 420, and be used for according to these a plurality of gray scale reference voltages to produce a plurality of voltage signal A1～An respectively corresponding to a plurality of digital data signal D1～Dn, and digital analog converter 430 includes a plurality of analog output point (not shown)s, is used for exporting a plurality of voltage signal A1～An respectively.
First multi-power output 440 has one first exit point and a plurality of first input end point I1～In, and a plurality of first input end point I1～In receive a plurality of voltage signal A1～An respectively, and wherein first multi-power output 440 is chosen among a plurality of voltage signal A1～An one first specific voltage signal (for example A1) and exported this first specific voltage signal by first exit point in one first period; Output buffer 450 is coupled to the first exit point O, and is used for producing one first specific drive signal (not shown) according to this first specific voltage signal in this first period; Second multi-power output, 460 cordings have a plurality of second exit point O1～On and one second input endpoint I, wherein a plurality of second exit point O1～On are coupled to a plurality of signal output part point S1～Sn respectively, the second input endpoint I receives this first specific drive signal, and second multi-power output 460 exports this first specific drive signal one first specific exit point (for example O1) in a plurality of second exit points to one first signal specific exit point (for example S1) in this first period; And switch module 470 is coupled between digital analog converter 430 and a plurality of signal output part point S1～Sn, and is used for exporting this first specific voltage signal to this first signal specific exit point being different from one second period of this first period.Simultaneously, first multi-power output 440 can be chosen the one second specific voltage signal (for example A2) that is different from this first specific voltage signal among a plurality of voltage signal A1～An and pass through this first exit point O output in this second period, and output buffer 450 can produce the second input endpoint I of one second specific drive signal (not shown) to the second multi-power output 460 according to this second specific voltage signal in this second period, and second multi-power output 460 can be different from this second specific drive signal this first specific exit point in a plurality of second exit point O1～On in this second period one second specific exit point (for example O2) exports one second signal specific exit point (for example S2) to.
Please refer to Fig. 5, the simplification circuit diagram that Fig. 5 illustrated for first multi-power output 440 among Fig. 4.As shown in Figure 5, first multi-power output 440 includes a plurality of on-off element SW11～SW1n, be respectively coupled between a plurality of first input end point I1～In and the first exit point O, wherein a plurality of on-off element SW11～SW1n are controlled by switch controlling signal PB_EN1～PB_ENn respectively.
Please refer to Fig. 6, the simplification circuit diagram that Fig. 6 illustrated for second multi-power output 460 among Fig. 4.As shown in Figure 6, second multi-power output 460 includes a plurality of on-off element SW21～SW2n, be respectively coupled between a plurality of second input endpoint O1～On and the second exit point I, wherein a plurality of on-off element SW21～SW2n are controlled by switch controlling signal PB_EN1～PB_ENn respectively.
Please refer to Fig. 7, the simplification circuit diagram that Fig. 7 illustrated for the switch module 470 among Fig. 4.As shown in Figure 7, second multi-power output 470 includes a plurality of on-off element SW31～SW3n, be respectively coupled between a plurality of voltage signal A1～An and a plurality of signal output part point S1～Sn of digital analog converter 430, wherein a plurality of on-off element SW31～SW3n are controlled by switch controlling signal GM_EN1～GM_ENn respectively.
For instance, when n=3, please also refer to Fig. 8, Fig. 9, Figure 10, Figure 11 and Figure 12, what Fig. 8 illustrated is 3 switch controlling signal PB_EN1～PB_EN3 and the sequential chart of 3 switch controlling signal GM_EN1～GM_EN3 and the voltage level change synoptic diagram of 3 signal output part point S1～S3 among 4 period T1～T4, the simplification block schematic diagram that Fig. 9 illustrated for source electrode drive circuit 400 in period T1, the simplification block schematic diagram that Figure 10 illustrated for source electrode drive circuit 400 in period T2, the simplification block schematic diagram that Figure 11 illustrated, and the simplification block schematic diagram that Figure 12 illustrated for source electrode drive circuit 400 in period T4 for source electrode drive circuit 400 in period T3.
In the present embodiment, 3 on-off element SW11～SW13,3 on-off element SW21～SW23 and 3 on-off element SW31～SW33 are N type field-effect transistor (for example NMOS field-effect transistor), therefore, as Fig. 8 and shown in Figure 9, in period T1, switch controlling signal PB_EN1 is that high logic level is with on-off element SW11 and on-off element SW21 conducting, and other switch controlling signals PB_EN2, switch controlling signal PB_EN3 and switch controlling signal GM_EN1～GM_EN3 are that low logic level is with on-off element SW12, on-off element SW13, on-off element SW22, on-off element SW23 and not conducting of on-off element SW31～SW33 make voltage signal A1 to draw high near VGSy1 from VGSx1 by the voltage level that output buffer 450 is put S1 with signal output part thus.
Then, as Fig. 8 and shown in Figure 10, in period T2, switch controlling signal PB_EN1 transfers low logic level to on-off element SW11 and not conducting of on-off element SW21, and switch controlling signal PB_EN2 and switch controlling signal GM_EN1 transfer high logic level to on-off element SW12, on-off element SW22 and on-off element SW31 conducting, and other switch controlling signals PB_EN3, switch controlling signal GM_EN2 and switch controlling signal GM_EN3 system keep low logic level with on-off element SW13, on-off element SW23 and not conducting of on-off element SW31～SW33, make voltage signal A2 to draw high near VGSy2 from VGSx2 thus, and the voltage level of signal output part point S1 can directly be calibrated to VGSy1 by voltage signal A1 (that is a gray scale reference voltages) by the voltage level that output buffer 450 is put S2 with signal output part.
Then, as Fig. 8 and shown in Figure 11, in period T3, switch controlling signal PB_EN1 keeps low logic level with on-off element SW11 and not conducting of on-off element SW21, and switch controlling signal GM_EN1 keeps high logic level with on-off element SW31 conducting, and switch controlling signal PB_EN2 transfers low logic level to on-off element SW12 and not conducting of on-off element SW22, and switch controlling signal PB_EN3 and GM_EN2 transfer high logic level to on-off element SW13, on-off element SW23 and on-off element SW32 conducting, and switch controlling signal GM_EN3 keeps low logic level with not conducting of on-off element SW3n, make voltage signal A3 to draw high near VGSy3 from VGSx3 thus by the voltage level that S3 put signal output part by output buffer 450, and the voltage level of signal output part point S2 can directly be calibrated to VGSy2 by voltage signal A2 (that is a gray scale reference voltages), and the voltage level of signal output part point S1 also can directly be maintained VGSy1 by voltage signal A1.
Then, as Fig. 8 and shown in Figure 12, in period T4, switch controlling signal PB_EN1 keeps low logic level with on-off element SW11 and not conducting of on-off element SW21, and switch controlling signal GM_EN1 keeps high logic level with on-off element SW31 conducting, and switch controlling signal PB_EN2 keeps low logic level with on-off element SW12 and not conducting of on-off element SW22, and switch controlling signal GM_EN2 keeps high logic level with on-off element SW32 conducting, and switch controlling signal PB_EN3 transfers low logic level to on-off element SW13 and not conducting of on-off element SW23, and switch controlling signal GM_EN3 transfers high logic level to on-off element SW3n conducting, make the voltage level of signal output part point S3 directly to be calibrated to VGSy3 thus by voltage signal A3 (that is a gray scale reference voltages), and the voltage level of signal output part point S1 also can directly be maintained VGSy1 by voltage signal A1, and the voltage level of signal output part point S2 also can directly be maintained VGSy2 by voltage signal A2.In addition, note that at this above embodiments only illustrate as of the present invention, rather than restrictive condition of the present invention, for instance, n can equal any positive integer.
In sum, source electrode drive circuit disclosed in this invention can reduce the quantity of needed output buffer, to dwindle area and and then to reduce production costs.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (5)
1. driving circuit includes:
A plurality of signal output part points;
One data-signal generation module is used for producing a plurality of digital data signals;
One gray scale reference voltages generation module is used for producing a plurality of gray scale reference voltages;
One digital analog converter is coupled to this data-signal generation module and this gray scale reference voltages generation module, is used for according to these a plurality of gray scale reference voltages to produce a plurality of voltage signals corresponding to these a plurality of digital data signals respectively;
One first multi-power output, have one first exit point and a plurality of first input end point, these a plurality of first input end points receive these a plurality of voltage signals respectively, and this first multi-power output is chosen in these a plurality of voltage signals one first specific voltage signal and exported this first specific voltage signal by this first exit point in one first period;
One output buffer is coupled to this first exit point, is used for producing one first specific drive signal according to this first specific voltage signal in this first period;
One second multi-power output, have a plurality of second exit points and one second input endpoint, these a plurality of second exit points are coupled to this a plurality of signal output part points respectively, this second input endpoint receives this first specific drive signal, and this second multi-power output exports this first specific drive signal one first specific exit point in these a plurality of second exit points to one first signal specific exit point in this first period; And
One switch module is coupled between this digital analog converter and this a plurality of signal output part points, is used for exporting this first specific voltage signal to this first signal specific exit point being different from one second period of this first period.
2. driving circuit as claimed in claim 1, wherein this first multi-power output is chosen the one second specific voltage signal that is different from this first specific voltage signal in these a plurality of voltage signals and is passed through this first exit point output in this second period; This output buffer produces one second specific drive signal this second input endpoint to this second multi-power output according to this second specific voltage signal in this second period; And this second multi-power output exports the one second specific exit point that is different from this first specific exit point in oneself these a plurality of second exit points of this second specific drive signal to one second signal specific exit point in this second period.
3. driving circuit as claimed in claim 1, it is the one source pole driving circuit that is applied in the display panels.
4. driving circuit as claimed in claim 1, wherein these a plurality of signal output part points include at least one first a signal output part point and a secondary signal exit point; This data-signal generation module is used for producing at least one first digital data signal and one second digital data signal; This digital analog converter includes at least one first analog output point and one second analog output point, is used for exporting one first voltage signal and one second voltage signal respectively; This switch module includes at least one first on-off element and is coupled between this first analog output point and this first signal output part point and a second switch element is coupled between this second analog output point and this secondary signal exit point; This first multi-power output includes at least one the 3rd on-off element and is coupled between this first analog output point and this first exit point and one the 4th on-off element is coupled between this first analog output point and this first exit point; And this second multi-power output includes one the 5th on-off element and is coupled between this second input endpoint and this first signal output part point and one the 6th on-off element is coupled between this second input endpoint and this secondary signal exit point.
5. driving circuit as claimed in claim 4, wherein in this first period, the 5th on-off element conducting of the 3rd on-off element of this first multi-power output and this second multi-power output, and this first on-off element of this switch module and this second switch element, the 4th on-off element of this first multi-power output and the 6th not conducting of on-off element of this second multi-power output; And in this second period, the 5th not conducting of on-off element of the 3rd on-off element of this first multi-power output and this second multi-power output, and this first on-off element of this switch module and this second switch element, the 4th on-off element of this first multi-power output and the 6th on-off element conducting of this second multi-power output.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810174066A CN101739962A (en) | 2008-11-13 | 2008-11-13 | Drive circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810174066A CN101739962A (en) | 2008-11-13 | 2008-11-13 | Drive circuit |
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| CN101739962A true CN101739962A (en) | 2010-06-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103310743A (en) * | 2012-03-13 | 2013-09-18 | 瑞鼎科技股份有限公司 | Driving circuit, operational amplification module thereof and data transmission method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103310743A (en) * | 2012-03-13 | 2013-09-18 | 瑞鼎科技股份有限公司 | Driving circuit, operational amplification module thereof and data transmission method |
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Open date: 20100616 |