CN101728316B - Method for manufacturing semiconductor chip with low warpage - Google Patents
Method for manufacturing semiconductor chip with low warpage Download PDFInfo
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- CN101728316B CN101728316B CN2008102021168A CN200810202116A CN101728316B CN 101728316 B CN101728316 B CN 101728316B CN 2008102021168 A CN2008102021168 A CN 2008102021168A CN 200810202116 A CN200810202116 A CN 200810202116A CN 101728316 B CN101728316 B CN 101728316B
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Abstract
The invention discloses a method for manufacturing a semiconductor chip with low warpage. The semiconductor chip is provided with a semiconductor device; a process for manufacturing an inter-metal dielectric layer and a metal interconnecting layer comprises at least once tempering step, so the movability of atoms of the inter-metal dielectric layer and the metal interconnecting layer is improved, the tractility of the two is increased, the stress of the two is correspondingly reduced, and the semiconductor chip has the advantage of low warpage.
Description
Technical field
The present invention relates to a kind of manufacture method with semiconductor wafer of low warpage.
Background technology
The situation of deformation all can take place in semiconductor wafer in manufacture process and when on semiconductor wafer, making circuit, electronic component subsequently.The deformation meeting influences the quality of semiconductor wafer, and for example in the photoengraving process, as if semiconductor wafer generation deformation, its illumination surface irregularity, in the case, the mask structure in the All Ranges of semiconductor wafer can not form distinct image.In addition, the mask structure that is transferred on the semiconductor wafer is displaced sideways, causes the overlapping of adjacent elements, can't bring into play its function.
Generally, available " angularity " described the global shape of semiconductor wafer.Angularity is meant the optimal reference face of relative semiconductor wafer intermediate surface, any 2 maximum deviation in the semiconductor wafer intermediate surface.Angularity is more little, explains that semiconductor wafer is smooth more; Angularity is big more, explains that the semiconductor wafer deformation extent is serious more.
The semiconductor bearing wafer that makes wafer provider provide owing to the production technology reason has certain angularity inevitably; In general; The angularity of 8inch semiconductor bearing wafer is at 0--30um; Correspondingly, the twice that 12inch semiconductor bearing wafer is of a size of 8inch semiconductor bearing wafer is many, and its angularity is at 0--67um.
Except the intrinsic angularity of above-mentioned semiconductor bearing wafer, on the semiconductor bearing wafer, make and to produce its angularity of deformation increase in circuit, the electronic component process equally.For example: metal intermetallic dielectric layer in the layer structure of semiconductor wafer or metal interconnecting layer increase because of self material behavior can cause the stress of layer structure self or interlayer structure; Perhaps semiconductive thin film also can cause the variation of stress owing to the variation of humiture under the external environment condition; So just make the angularity of semiconductor wafer increase; Increase the probability that semiconductor wafer produces jackknifing, reduce performance of products and yield.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method with semiconductor wafer of low warpage, and the angularity that how to prevent semiconductor wafer increases and influences the problem of product yield.
The present invention provides a kind of manufacture method with semiconductor wafer of low warpage, is manufactured with semiconductor device on the said semiconductor wafer, in the technology of metal intermetallic dielectric layer of making semiconductor device and metal interconnecting layer, comprises the temper step at least one time.
Alternatively, when semiconductor device had sandwich construction, said temper step was in the technology of the several layers making metal intermetallic dielectric layer of said sandwich construction posterior segment and metal interconnecting layer, to carry out.
Alternatively, said temper step comprises the metal interconnecting layer and the metal intermetallic dielectric layer that form is carried out temper respectively.
Alternatively, required temperature is 300 ℃ in the said temper--600 ℃, the duration of temperature is 20 minutes--and 90 minutes.
Alternatively, further be included on the semiconductor wafer and the bearing wafer of the semiconductor with low warpage be provided before making semiconductor device.
Alternatively, the angularity of said semiconductor bearing wafer when wafer size is 8 inches smaller or equal to 10 microns.
Alternatively, between the silicon oxide glass layers depositing technics of oxygen enrichment silicon dioxide deposition process of making metal intermetallic dielectric layer and fluorine doping, further comprise the step of being carried out management and control the stand-by period.
Alternatively, the said step that the stand-by period is carried out management and control comprises: set a regulation time limit to the stand-by period, and on semiconductor wafer, indicate the said regulation time limit; After accomplishing the oxygen enrichment silicon dioxide deposition process, pick up counting; When timing result is to exceed the said regulation time limit but when not carrying out silicon oxide glass layers depositing technics that fluorine mixes yet, produce information, and improve the priority of said semiconductor wafer.
Alternatively, when beginning the silicon oxide glass layers depositing technics that carries out the fluorine doping, then stop timing.
Alternatively, be limited to smaller or equal to 10 hours during said regulation to the stand-by period.
Compared with prior art; Technique scheme provides in the technology of making metal intermetallic dielectric layer and metal interconnecting layer and has comprised the temper step at least one time; Through temper, improve the atom action ability of metal intermetallic dielectric layer and metal interconnecting layer, increase its ductility; Corresponding reduction stress makes semiconductor wafer obtain the effect of low warpage.
In addition, through technique scheme,, guaranteed the low warpage after making semiconductor device on the semiconductor bearing wafer owing to just in advance the semiconductor bearing wafer with low warpage is provided before on semiconductor wafer, making semiconductor device.
Have again; Pass through technique scheme; Owing between the silicon oxide glass layers depositing technics that the oxygen enrichment silicon dioxide deposition process of making metal intermetallic dielectric layer and fluorine mix, further comprise the stand-by period carried out management and control, avoided the influence of the variation of humiture to the angularity of semiconductive thin film.
Description of drawings
Fig. 1 is a schematic flow sheet of making temper step in the semiconductor wafer in the embodiment of the present invention;
Fig. 2 to Fig. 4 forms the sketch map of making semiconductor wafer according to flow process shown in Figure 1;
Fig. 5 is the variation sketch map after metal interconnecting layer and the tempered processing of metal intermetallic dielectric layer in the embodiment of the present invention;
Fig. 6 is a variation of temperature curve chart in the temper in the embodiment of the present invention;
Fig. 7 is the schematic flow sheet that in the embodiment of the present invention is carried out management and control the stand-by period.
Embodiment
The embodiment of the invention is through provide the bearing wafer of the semiconductor with low warpage in advance; In the technology of metal intermetallic dielectric layer and metal interconnecting layer, comprise one time the temper step on this basis at least; And between oxygen enrichment silicon dioxide deposition process of making metal intermetallic dielectric layer and FGS depositing technics, further comprise the stand-by period is carried out management and control; Reduce the stress of metal intermetallic dielectric layer, metal interconnecting layer, semiconductive thin film in the semiconductor wafer, make semiconductor wafer obtain the effect of low warpage.
For making above-mentioned purpose of the present invention, characteristic and the advantage can be more obviously understandable, do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
The manufacture method of semiconductor wafer in the embodiment of the present invention comprises the temper step at least one time in the technology of metal intermetallic dielectric layer of making semiconductor device and metal interconnecting layer.Fig. 1 is the schematic flow sheet of an embodiment of temper step in the making semiconductor wafer of the present invention, and concrete steps comprise:
Execution in step S11 forms metal interconnecting layer 201 on semiconductor wafer 200, form structure shown in Figure 2, and metal interconnecting layer 201 is carried out temper.Wherein, the material of said metal interconnecting layer can be wherein any one or its combination of metals such as aluminium, lead, tin, silver, copper, gold, bismuth, antimony, zinc, nickel, zirconium, magnesium, indium, tellurium and gallium for example.In practical application; Said metal interconnecting layer is with commonly used for comparatively by copper or aluminium institute constitutor; Wherein, Because copper has than aluminium and has lower resistivity (resistivity of aluminium is 2.62 μ Ω cm, and Cu is 1.69 μ Ω cm) and higher electromigration resisting property (can increase about two one magnitude), so copper is a kind of preferred material of deep-submicron and nanometer integrated circuit multilayer interconnection line.
Execution in step S13 carries out photoetching, etching technics in regular turn, makes to form structure shown in Figure 3 by the interconnection line 202 that forms patterning at metal interconnecting layer 201.Because of this part is a prior art, so give unnecessary details no longer separately at this.
Execution in step S15 forms metal intermetallic dielectric layer 203 on semiconductor wafer 200, metal intermetallic dielectric layer 203 is to be formed on the metal interconnecting layer 201, forms structure shown in Figure 4, and metal intermetallic dielectric layer 203 is carried out temper.Wherein, In the present embodiment, this metal intermetallic dielectric layer can be for example epoxy resin (ABF), two benzocyclobutene (BCB) or polyimides organic dielectric material films such as (PI), but not as limit; In other embodiments, this metal intermetallic dielectric layer also can be to be processed by the organic liquid resin material.
In above-mentioned temper, along with the rising of temperature, the hardness of metal interconnecting layer and metal intermetallic dielectric layer and intensity can reduce, and ductility and toughness are improved, and the atom action ability strengthens, and reduces its inherent stress.
Fig. 5 is the variation sketch map of metal interconnecting layer and metal intermetallic dielectric layer in the temper.As shown in Figure 2, the metal interconnecting layer 21 tempered processing of heating can improve the mobility of its atom; Increase its ductility; Discharge inherent stress, make metal interconnecting layer 21 produce the trend of expansion downwards, the semiconductive thin film 20 in the middle of its edge progressively fits in because of being heated; Realize the tight bonding that the two is mutual, reduce the angularity of metal interconnecting layer 21; Accordingly, the metal intermetallic dielectric layer 22 tempered processing of heating can improve the mobility of atom; Increase its ductility; Discharge inherent stress, make metal intermetallic dielectric layer 22 produce the trend that upwards tightens, the semiconductive thin film 20 in the middle of its edge progressively fits in because of being heated; Realize the tight bonding that the two is mutual, reduce the angularity of metal intermetallic dielectric layer 22.This shows,, can improve the atom action ability of metal interconnecting layer 21 and metal intermetallic dielectric layer 22, increase its ductility, corresponding reduction stress, the effect of acquisition low warpage through temper.
Fig. 6 is a variation of temperature curve chart in the temper.As shown in Figure 3, at first, temperature is heated to temperature K by room temperature with certain firing rate; Keep temperature K and, make and in duration T, carry out temper its lasting a period of time T; At last, with certain cooling rate temperature is cooled to room temperature by temperature K.In the present embodiment, described temperature is 300 ℃--600 ℃, preferably, can choose about 400 ℃.In addition, duration T is 20 minutes--90 minutes, preferably, can choose about 70 minutes.Have again; Said firing rate and cooling rate can change according to actual conditions; For example can adopt Fast Heating cool off at a slow speed or at a slow speed heating fast the asymmetric mode of cooling carry out; But, for example also can adopt Fast Heating to cool off the symmetric mode that perhaps heats cooling at a slow speed at a slow speed fast and carry out not as limit.
What need explanation is; In the above-described embodiments, describe respectively metal interconnecting layer and metal intermetallic dielectric layer are carried out temper, but not as limit; In fact; Under some situation, as long as, can reach the effect that reduces angularity equally to wherein one carrying out temper in metal interconnecting layer and the metal intermetallic dielectric layer.
In addition, in practical application, for usually semiconductor wafers that adopt sandwich constructions in the prior art more, carry out the number of times of temper and can adjust, be not limited in once, can be repeatedly according to the number of plies of semiconductor structure or material etc.; And in repeatedly the time, each time temper can be continuous, also can be discontinuous.Yi Zhi, the number of times of temper is many more, and is just helpful more to reducing angularity.But, the number of times of temper can make also that too much the processing procedure of semiconductor wafer is complicated more, increases the operation of processing procedure, can take the process apparatus of carrying out technology more, reduces the utilance of process apparatus.Therefore, the temper number of times should combine angularity requirement and operating efficiency and comprehensive consideration.In general; Because which floor initial metal interconnecting layer and metal intermetallic dielectric layer are less relatively to the whole angularity influence of semiconductor wafer; Therefore, temper is in said sandwich construction, to be in the manufacture craft of several layers metal interconnecting layer and metal intermetallic dielectric layer of posterior segment to carry out basically.By way of example; Suppose that semiconductor wafer has 5 layers of metal interconnecting layer; So can be therein the the 3rd, the 4th and the 5th layer be carried out temper three times, but not as limit, and also can be therein the 3rd and the 5th layer or the 4th and the 5th layer be carried out repeatedly temper respectively.
In addition, in the manufacture method of semiconductor wafer, on semiconductor wafer, further comprise before the making semiconductor device bearing wafer of the semiconductor with low warpage is provided in the embodiment of the present invention.In the present embodiment, the angularity of said semiconductor bearing wafer when wafer size is 8 inches smaller or equal to 10 microns.Correspondingly, the angularity of the semiconductor bearing wafer of other sizes all can this standard as a reference, and for example when if the semiconductor bearing wafer is of a size of 12 inches, its angularity then is lower than 22.5 millimeters.Choose semiconductor bearing wafer and can realize that low warpage builds up a solid foundation for the semiconductor wafer that behind subsequent technique, forms with low warpage.
Have again, generally make the processing step that metal intermetallic dielectric layer includes silicon oxide glass layers (FGS) deposit of (SRO) deposit of oxygen enrichment silicon dioxide layer and fluorine doping.Wherein, The silica glass that fluorine mixes is a kind of advanced low-k materials; Can satisfy the requirement of integrated circuit low-k, but fluorine ion wherein possibly there are physics or chemical action to metal or barrier layer, badly influences device performance even causes component failure; So between metal interconnecting layer and FGS layer, be deposited with the SRO layer, said SRO layer can be avoided the metal interconnecting layer that fluorine ion infiltrates lower floor downwards in the FGS layer on upper strata.
In the embodiment of the present invention in the manufacture method of semiconductor wafer, between the SRO depositing technics of making metal intermetallic dielectric layer and FGS depositing technics, further comprise the stand-by period is carried out the step of management and control with the angularity that reduces semiconductive thin film.In the present embodiment, SRO depositing technics and FGS depositing technics can be high-density plasma chemical vapor deposition (HDP-CVD), but not as limit.Through management and control to the said stand-by period, can guarantee semiconductor wafer between the SRO of metal intermetallic dielectric layer depositing technics and FGS depositing technics during this period of time in can not change the quality that influence semiconductive thin film because of the humiture of external environment condition.
The step of Fig. 7 for the stand-by period is carried out management and control.As shown in Figure 7, execution in step S71 sets one to the stand-by period and stipulates the time limit, and on semiconductor wafer, indicates the said regulation time limit.
The length of said stand-by period can influence the quality of semiconductive thin film; Stand-by period is long more; The probability that humiture changes and intensity of variation is bigger under the external environment condition is just big more; Externally the following influence that makes its stress receive owing to the variation of humiture of environment is big more for semiconductive thin film, just might make the quality of semiconductive thin film produce deterioration more.For example when surpassing ± 5 ℃ in temperature, humidity surpasses under ± 20% the situation, can influence the quality of semiconductive thin film.In the present embodiment; The said regulation time limit to the stand-by period can be made as smaller or equal to 10 hours, but not as limit, for example for some semiconductor wafer; It is higher to outside environment requirement; Do not hope said waits for too long, avoid semiconductive thin film owing to the influence that receives the variation of humiture in the external environment condition for a long time causes the variation of its stress, thus said regulation time limit to the stand-by period can be made as less than 6 hours in addition more hour between.
In addition; In the present embodiment; On semiconductor wafer, indicating the said regulation time limit specifically can manage through the management system in the workshop; For example can set the said stipulated time in management system according to label on the carrying case of each batch semiconductor wafer or sequence number, like this, the staff just can inquire about and obtain the data of the stand-by period that comprises each semiconductor wafer and current situation thereof in real time through said management system.
Execution in step S73 then picks up counting after semiconductor wafer is accomplished the SRO depositing technics.In the present embodiment, the SRO layer is to be added in the layer oxide film that can reduce angularity between interlayer film and the metal interconnecting layer.
Execution in step S75, when timing result for exceeding the said regulation time limit but when not carrying out the FGS depositing technics yet, produce information, and improve the priority of said semiconductor wafer.In fact, in the present embodiment, when beginning to carry out technology, then stop timing, and when not beginning to carry out the FGS depositing technics, do not stop timing.It is alarm modes such as lamp is bright, audible alarm for example that said information can be passed through; But not as limit; For example also can be in management system through with the pairing data of the semiconductor wafer that exceeds the said regulation time limit in increase note or point out with the bright display mode of height; Like this; The staff can be directly or is recognized through inquiry that this part semiconductor wafer has exceeded schedule time but do not carry out the FGS depositing technics yet, and for carrying out the production distribution adjustment, the semiconductor wafer overtime to this part carries out the FGS depositing technics.In the present embodiment; Can set different priority to semiconductor wafer, exceed the said regulation time limit for those but when not carrying out the FGS depositing technics yet, can improve its priority automatically; The prompting staff must pay the utmost attention to; For example adjust layout, suspend or delay the lower semiconductor wafer of those priority, and those semiconductor wafers that will have a higher priority carry out priority treatment; Carry out the FGS depositing technics, avoid in the semiconductor wafer oxygen enrichment silicon dioxide externally environment down because its angularity of variable effect of humiture.
Through above-mentioned management and control for the stand-by period, can make semiconductor wafer can externally not wait for for a long time, avoided the influence of the variation of humiture to the angularity of semiconductive thin film.
In sum; Technique scheme provide the semiconductor wafer with low warpage manufacture method its be in the technology of making metal intermetallic dielectric layer and metal interconnecting layer, to comprise the temper step at least one time, through temper, the atom action ability of raising metal intermetallic dielectric layer and metal interconnecting layer; Increase its ductility; Corresponding reduction stress makes semiconductor wafer obtain the effect of low warpage, improves performance of products and increases the yield of product.
In addition, through technique scheme,, guaranteed the low warpage after making semiconductor device on the semiconductor bearing wafer owing to just in advance the semiconductor bearing wafer with low warpage is provided before on semiconductor wafer, making semiconductor device.
Have again; Pass through technique scheme; Owing between the silicon oxide glass layers depositing technics that the oxygen enrichment silicon dioxide layer depositing technics of making metal intermetallic dielectric layer and fluorine mix, further comprise the stand-by period carried out management and control, avoided the influence of the variation of humiture to the angularity of semiconductive thin film.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (5)
1. manufacture method with semiconductor wafer of low warpage; Be manufactured with semiconductor device on the said semiconductor wafer; Said semiconductor device comprises metal interconnecting layer, it is characterized in that: said manufacture method comprises: metal interconnecting layer is carried out temper one time; The process conditions of said tempering are 300 ℃--600 ℃, continue 20 minutes--and 90 minutes;
Formation is embedded in the metal interconnecting layer in the metal intermetallic dielectric layer;
Wherein said metal intermetallic dielectric layer comprises the silicon oxide glass layers that oxygen enrichment silicon dioxide layer and fluorine mix; Said manufacture method comprises: the silicon oxide glass layers depositing step that oxygen enrichment silicon dioxide deposition step and fluorine mix; Comprise the step of being carried out management and control the stand-by period between the silicon oxide glass layers depositing technics that said oxygen enrichment silicon dioxide deposition process and fluorine mix, be limited to smaller or equal to 10 hours during said regulation to the stand-by period;
The said step that the stand-by period is carried out management and control comprises:
Set one to the stand-by period and stipulate the time limit, and on semiconductor wafer, indicate the said regulation time limit;
After accomplishing the oxygen enrichment silicon dioxide deposition process, pick up counting;
When timing result is to exceed the said regulation time limit but when not carrying out silicon oxide glass layers depositing technics that fluorine mixes yet, produce information, and improve the priority of said semiconductor wafer; Wherein, when beginning the silicon oxide glass layers depositing technics that carries out the fluorine doping, then stop timing.
2. the manufacturing approach of semiconductor wafer according to claim 1; It is characterized in that; When semiconductor device had sandwich construction, said temper step was in the technology of the several layers making metal intermetallic dielectric layer of said sandwich construction posterior segment and metal interconnecting layer, to carry out.
3. the manufacturing approach of semiconductor wafer according to claim 1 and 2 is characterized in that, said temper step comprises carries out temper respectively to the metal interconnecting layer and the metal intermetallic dielectric layer that form.
4. the manufacturing approach of semiconductor wafer according to claim 1 is characterized in that, further is included on the semiconductor wafer and before the making semiconductor device bearing wafer of the semiconductor with low warpage is provided.
5. the manufacturing approach of semiconductor wafer according to claim 4 is characterized in that, the angularity of said semiconductor bearing wafer when wafer size is 8 inches smaller or equal to 10 microns.
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| CN2008102021168A CN101728316B (en) | 2008-10-31 | 2008-10-31 | Method for manufacturing semiconductor chip with low warpage |
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| CN101728316B true CN101728316B (en) | 2012-03-07 |
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| CN104637864B (en) * | 2013-11-14 | 2017-11-24 | 中芯国际集成电路制造(上海)有限公司 | The method for improving data holding ability |
| CN106469230A (en) * | 2015-08-19 | 2017-03-01 | 北大方正集团有限公司 | A kind of non-activity duration length determining method and its system |
| CN107452638B (en) * | 2017-08-11 | 2019-06-28 | 中国科学院上海微系统与信息技术研究所 | Wafer-level package structure and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100510464B1 (en) * | 1998-04-30 | 2005-10-24 | 삼성전자주식회사 | Deposition method of high density plasma oxide |
| CN101192571A (en) * | 2006-11-30 | 2008-06-04 | 东部高科股份有限公司 | Method of manufacturing cmos image sensor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100510464B1 (en) * | 1998-04-30 | 2005-10-24 | 삼성전자주식회사 | Deposition method of high density plasma oxide |
| CN101192571A (en) * | 2006-11-30 | 2008-06-04 | 东部高科股份有限公司 | Method of manufacturing cmos image sensor |
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