CN101728268A - Method for manufacturing MOS device and method for forming semiconductor device well region - Google Patents
Method for manufacturing MOS device and method for forming semiconductor device well region Download PDFInfo
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Abstract
The invention discloses a method for manufacturing a semiconductor device and a method for forming an MOS device well region. The manufacture method comprises the following steps of: providing a semiconductor substrate with a buffer oxide layer and a nitride layer, wherein a shallow groove isolating area is arranged in the semiconductor substrate, the buffer oxide layer is positioned on the semiconductor substrate outside the shallow groove isolating area, and the nitride layer is positioned on the buffer oxide layer; removing the nitride layer, carry out ion injection on the semiconductor substrate with the buffer oxide layer and forming a well region; removing the buffer oxide layer; forming a grid electrode on the semiconductor substrate; and forming a source electrode region and a drain electrode region in the semiconductor substrates at both sides of the grid electrode. The invention enables the threshold voltage of the semiconductor device to rise, thus the performance of the semiconductor device is higher.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the formation method of the manufacture method of MOS device and semiconductor device well region.
Background technology
In semiconductor fabrication, at first on Semiconductor substrate, form the buffer oxide layer usually, for example can be silicon dioxide (SiO
2) layer, on the buffer oxide layer, form nitride layer, for example silicon nitride (Si
3N
4) layer.Then the Semiconductor substrate with described buffer oxide layer and described nitride layer is carried out etching and form groove, in groove, fill dielectric, thereby form shallow channel isolation area (STI).After forming, STI removes described buffer oxide layer and nitride layer.
For example on open: on 04 18th, 2007; disclosed publication number is CN1949472; name is called: in the Chinese patent application of semiconductor device and manufacture method thereof; a kind of method that forms STI on semiconductor substrate is provided; as shown in Figures 1 to 3; at first on semiconductor substrate 1, form protection oxide-film 2; on protection oxide-film 2, form silicon nitride film 3; by photolithography and dry-etching; silicon nitride film 3 and protection oxide-film 2 are run through; and a part of removing semiconductor substrate is to form groove 4; on groove 4 and silicon nitride film 3, form buried oxidation film 5; remove the buried oxidation film 5 on the silicon nitride film and the surface element of silicon nitride film 3, a part of removing the buried oxidation film 5 that is deposited on groove by Wet-type etching by CMP.
In the MOS device making method in the prior art, after above-mentioned steps, to shown in Figure 5, also comprise and remove protection oxide-film 2 and silicon nitride film 3 with reference to figure 4; Forming oxidation masking layer 6 then on semiconductor substrate 1, for example can be silicon dioxide (SiO
2) layer, then mixing forms N well region or P well region, and the method for for example utilizing ion to inject is mixed.
But development along with the semiconductor technology size, the grid critical dimension of semiconductor device reduces gradually, for example grid becomes shorter and shorter, more and more narrow, the conducting channel that forms in the Semiconductor substrate under so corresponding grid is also shorter and shorter, more and more narrow, therefore also more and more stricter to the requirement of technology.But in the above-mentioned manufacture method; in the process of removing buffer oxide layer or protection oxide-film 2, may cause damage to Semiconductor substrate; and in the process that forms oxidation masking layer 6, Semiconductor substrate had compression; therefore mix when forming well region; dopant ion can be to outdiffusion; make the ion concentration in the conducting channel reduce,, make the degradation of semiconductor device so the semiconducter device testing of said method manufacturing is being found its threshold voltage is lower than ideal value.
Summary of the invention
In order to address the above problem, the invention provides a kind of manufacture method of MOS device and a kind of formation method of MOS device well region, described method has improved the threshold voltage of MOS device, makes the performance of MOS device better.
The invention provides a kind of manufacture method of MOS device, comprise step:
Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, described buffer oxide layer is positioned on the Semiconductor substrate outside the described shallow channel isolation area, and described nitride layer is positioned on the described buffer oxide layer;
Remove described nitride layer;
Semiconductor substrate with described buffer oxide layer is carried out ion inject, form well region;
Remove described buffer oxide layer;
On Semiconductor substrate, form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
Optionally, described forming process with Semiconductor substrate of buffer oxide layer and nitride layer is:
Semiconductor substrate is provided;
On described Semiconductor substrate, form the buffer oxide layer;
On described buffer oxide layer, form nitride layer;
To described Semiconductor substrate etching, form groove;
Form the trench liner oxide skin(coating) of covering groove sidewall and bottom surface;
Form the fill oxide layer in groove and on the nitride layer;
Planarization fill oxide layer exposes semiconducting nitride thing layer, and makes the top of groove and the semiconductor-based end be positioned at same plane.
Optionally, the material of described buffer oxide layer comprises silicon dioxide, and the material of described nitride layer comprises silicon nitride.
Optionally, described semiconductor device comprises any one in nmos device and the PMOS device.
Optionally, the ion of described nmos device ion injection comprises the boron ion; The ion that PMOS device ion injects comprises phosphonium ion.
Optionally, after removing described nitride layer step, before the Semiconductor substrate with described buffer oxide layer is carried out the ion implantation step, can also be included in and form the masking oxide layer on the buffer oxide layer.
Corresponding the present invention also provides a kind of formation method of semiconductor device well region, comprises step:
Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, described buffer oxide layer is positioned on the Semiconductor substrate outside the described shallow channel isolation area, and described nitride layer is positioned on the described buffer oxide layer;
Remove described nitride layer;
Semiconductor substrate with described buffer oxide layer is carried out ion inject, form well region.
Optionally, described semiconductor device comprises nmos device and PMOS device.
Optionally, the ion of described nmos device ion injection comprises the boron ion; The ion that PMOS device ion injects comprises phosphonium ion.
Optionally, after removing described nitride layer step, before the Semiconductor substrate with described buffer oxide layer is carried out the ion implantation step, can also be included in and form the masking oxide layer on the buffer oxide layer.
The advantage of technique scheme is:
Compare the resilient coating of the present invention with prior art by utilizing the buffer oxide layer that forms in the step formerly to inject as ion, and do not form oxidation masking layer in addition, eliminated in the process of removing the buffer oxide layer in the prior art infringement like this to Semiconductor substrate, also eliminated simultaneously and formed the compression that oxidation masking layer causes Semiconductor substrate, therefore reduced to mix when forming well region, dopant ion is to the phenomenon of outdiffusion, thereby improved the interior dopant ion concentration of conducting channel of later stage formation, improved threshold voltage.
In a technical scheme of the present invention, also comprised the process of formation shallow channel isolation area (STI), therefore utilized to form the buffer oxide layer that forms on the preceding Semiconductor substrate of STI, make the making step of semiconductor device simplify more.
In a technical scheme of the present invention, the ion that described nmos device ion injects comprises phosphonium ion; The ion that PMOS device ion injects comprises the boron ion, because compression is bigger to the mobility influence of boron ion and phosphonium ion, therefore the resilient coating that utilizes the buffer oxide layer on the Semiconductor substrate to inject as ion, and do not form oxidation masking layer in addition, eliminated and formed the compression that oxidation masking layer causes Semiconductor substrate, therefore reduced to mix when forming well region, dopant ion is to the phenomenon of outdiffusion, thereby improved the interior dopant ion concentration of conducting channel of later stage formation, improved threshold voltage.
Description of drawings
Fig. 1 to 5 is a kind of manufacture method schematic diagram of conventional semiconductor device;
Fig. 6 is the flow chart of manufacture method first embodiment of MOS device of the present invention;
Fig. 7 to Fig. 9 is the schematic diagram of the manufacture method embodiment of MOS device of the present invention;
Figure 10 is the flow chart of manufacture method second embodiment of MOS device of the present invention;
The experimental data of Figure 11 for the MOS device is tested.
Embodiment
In the MOS manufacturing technology, the step of traditional formation STI is: at first form dielectric layer on Semiconductor substrate, for example dielectric layer can be silicon dioxide SiO
2Layer and be positioned at SiO
2The laminated construction of silicon nitride SiN on the layer carries out etching to the Semiconductor substrate with dielectric layer then and forms groove, fills dielectric in groove, thereby forms shallow channel isolation area (STI).After forming, STI removes described dielectric layer.After removing described dielectric layer, on Semiconductor substrate, form oxidation masking layer, for example can be silicon dioxide SiO
2Layer, effect is the channeling effect that reduces in the back doping step.Then mixing forms N well region or P well region, for example utilizes ion to inject.The effect of N well region or P well region is to improve threshold voltage.Think after the present inventor's research: in the manufacturing of MOS device, owing to can damage Semiconductor substrate in the step of removal dielectric layer, for example produce deep depression (divot) at the active area edge, the oxidation masking layer of later stage formation can produce compression to Semiconductor substrate like this, these factors can cause in the step of formation N well region or P well region of mixing, the N type ion of the part dosage that mixes or P type ion under action of compressive stress to outdiffusion, especially short more and narrow more at short channel, the influence of compression is big more, thereby reduced the source area of later stage formation and the concentration of the dopant ion in the conducting channel between the drain region, thereby the gate threshold voltage of the feasible semiconductor device that forms reduces.
In conjunction with above-mentioned analysis, the inventor provides a kind of manufacture method of MOS device, comprises step:
Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, described buffer oxide layer is positioned on the Semiconductor substrate outside the described shallow channel isolation area, and described nitride layer is positioned on the described buffer oxide layer;
Remove described nitride layer;
Semiconductor substrate with described buffer oxide layer is carried out ion inject, form well region;
Remove described buffer oxide layer;
On Semiconductor substrate, form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
Optionally, described forming process with Semiconductor substrate of buffer oxide layer and nitride layer is:
Semiconductor substrate is provided;
On described Semiconductor substrate, form the buffer oxide layer;
On described buffer oxide layer, form nitride layer;
To described Semiconductor substrate etching, form groove;
Form the trench liner oxide skin(coating) of covering groove sidewall and bottom surface;
Form the fill oxide layer in groove and on the nitride layer;
Planarization fill oxide layer exposes semiconducting nitride thing layer, and makes the top of groove and the semiconductor-based end be positioned at same plane.
The material of described buffer oxide layer comprises silicon dioxide, and the material of described nitride layer comprises silicon nitride.
Described MOS device comprises any one in nmos device and the PMOS device.
The ion that described nmos device ion injects comprises the boron ion; The ion that PMOS device ion injects comprises phosphonium ion.
After removing described nitride layer step, before the Semiconductor substrate with described buffer oxide layer is carried out the ion implantation step, can also be included in and form the masking oxide layer on the buffer oxide layer.
Corresponding the present invention also provides a kind of formation method of semiconductor device well region, comprises step:
Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, described buffer oxide layer is positioned on the Semiconductor substrate outside the described shallow channel isolation area, and described nitride layer is positioned on the described buffer oxide layer;
Remove described nitride layer;
Semiconductor substrate with described buffer oxide layer is carried out ion inject, form well region.Described semiconductor device comprises nmos device and PMOS device.
The ion that described nmos device ion injects comprises the boron ion; The ion that PMOS device ion injects comprises phosphonium ion.
After removing described nitride layer step, before the Semiconductor substrate with described buffer oxide layer is carried out the ion implantation step, can also be included in and form the masking oxide layer on the buffer oxide layer.
Compare the resilient coating of the present invention with prior art by utilizing the buffer oxide layer that forms in the step formerly to inject as ion, and do not remove the buffer oxide layer, eliminated in the process of removing oxide skin(coating) in the prior art infringement like this to Semiconductor substrate, also reduced simultaneously to form the compression that oxidation masking layer causes Semiconductor substrate, therefore reduced to mix when forming well region, dopant ion is to the phenomenon of outdiffusion, thereby improved the interior dopant ion concentration of conducting channel of later stage formation, improved threshold voltage.
Come the embodiment of method of the present invention is described in detail below in conjunction with accompanying drawing.
Embodiment one
Please refer to Fig. 6.
S110: the Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, on the Semiconductor substrate outside the described shallow channel isolation area, have the buffer oxide layer, and be positioned at the nitride layer on the buffer oxide layer.
As shown in Figure 7, provide Semiconductor substrate 102, described Semiconductor substrate 102 can be monocrystalline silicon, polysilicon or amorphous silicon; Described Semiconductor substrate 102 also can be silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate 102 can also have epitaxial loayer or insulating barrier silicon-on; Described Semiconductor substrate 102 can also be other semi-conducting material, enumerates no longer one by one here.
Have shallow channel isolation area (STI) 104 in Semiconductor substrate 102, described STI 104 is used for isolating the active area of dissimilar MOS devices, for example PMOS device and nmos device in the cmos device.STI 104 can adopt method well known to those skilled in the art to form, and for example to having Semiconductor substrate 102 etchings of buffer oxide layer 106 and nitride layer 108, forms groove; Thermal oxidation forms the groove pad oxide skin(coating) 110 of covering groove sidewall and bottom surface; Deposit silicon dioxide SiO in groove and on the nitride layer 108
2Form fill oxide layer 112, covered fully up to the top of groove; Planarization fill oxide layer 112 for example adopts chemico-mechanical polishing (CMP), exposes nitride layer 108 and makes the top of groove and nitride layer 108 be positioned at same plane.
Because in the process of making STI 104, at first need etching semiconductor substrate 102, form groove, therefore buffer oxide layer 106 and the nitride layer 108 on the Semiconductor substrate 102 of STI 104 position correspondences also is removed, and on Semiconductor substrate 102, position outside the STI 104 still has buffer oxide layer 106, and for example buffer oxide layer 106 is silicon dioxide SiO
2, or doped silica material.Described buffer oxide layer 106 can adopt method well known to those skilled in the art to form, for example thermal oxide growth, physical vapor deposition (PVD) or chemical vapor deposition modes such as (CVD).This buffer oxide layer 106 has two effects in the present embodiment, first nitride layer and transition between the Semiconductor substrate and the buffering as follow-up formation, second this buffer oxide layer 106 also injects the process that forms well region at the ion of back and is used for playing cushioning effect, prevents channeling effect.The thickness of described buffer oxide layer 106 is relevant with the technology that semiconductor is made, if too thick being not easy of described buffer oxide layer 106 removed, influence make efficiency, if the too thin effect that does not have good transition and buffering, and the process that can not effectively inject at ion prevents channeling effect.Therefore the thickness that for example is used in buffer oxide layer 106 described in the technology that grid critical dimension is 0.18 μ m, 90nm or 65nm is also different, and in order to prevent channeling effect, the ion implantation dosage difference, the thickness of buffer oxide layer 106 is also different.Those skilled in the art can determine the thickness of buffer oxide layer 106 according to the dosage of process conditions and ion injection, for example can be under the 65nm process conditions, and the thickness of buffer oxide layer 106 is 50 dusts-100 dusts.
On described buffer oxide layer 106, has nitride layer 108.It for example can be silicon nitride.Described nitride layer 108 can adopt mode well known to those skilled in the art to form, for example thermal oxide growth, physical vapor deposition (PVD) or chemical vapor deposition modes such as (CVD).Described nitride layer 108 should be has bigger hardness, and therefore effect is that the grinding that is used as chemico-mechanical polishing in the manufacturing process of STI stops layer, determines the position that polishing stops.The technology that the thickness of described nitration case 108 and semiconductor are made is relevant, is not easy removal if described nitride layer 108 is too thick, influences make efficiency, if too thinly do not have a good protective effect.Those skilled in the art can determine the thickness of nitride layer 108 according to the needs of process conditions.
In the present embodiment because utilized resilient coating when forming the buffer oxide layer that forms on the Semiconductor substrate before the STI and injecting, so make the making step of semiconductor device simplify more as the back ion.
S120: remove described nitride layer 108.
The process of removing nitride layer 108 can adopt method well known to those skilled in the art, for example clean or chemico-mechanical polishing (CMP) with phosphoric acid solution, because phosphoric acid to the corrosivity of silicon dioxide a little less than, therefore present embodiment adopts phosphoric acid solution to clean, and has kept less to the infringement of buffer oxide layer 106 like this when removing silicon nitride layer 108.
After above-mentioned steps, also can on buffer oxide layer 106, form the masking oxide layer.Also can remove the buffer oxide layer 106 of segment thickness, on remaining buffer oxide layer 106, form the masking oxide layer then.The method that forms the masking oxide layer can be physical vapor deposition (PVD) or chemical vapor deposition modes such as (CVD).Those skilled in the art can be according to process conditions, the dosage of ion injection and the thickness of buffer oxide layer 106, determine the thickness of the masking oxide layer of formation, make the thickness sum of buffer oxide layer 106 and masking oxide layer can satisfy the requirement that ion injects.For example under the 65nm process conditions, if buffer oxide layer 106 thickness are 50 dusts, then the thickness of masking oxide layer is the 0-50 dust, is 50 dusts-100 dusts thereby make the thickness of masking oxide layer and the thickness sum of buffering oxide skin(coating) 106.If removed the buffer oxide layer 106 of segment thickness, for example under the 65nm process conditions, buffer oxide layer 106 thickness are 30 dusts after removing, and the thickness of the masking oxide layer of Xing Chenging is 20 dusts-70 dusts so.
Because remove the buffer oxide layer 106 surface meeting out-of-flatness after the nitride layer 108, and surface ratio buffer oxide layer 106 surface of the masking oxide layer that this step forms are more smooth, so this embodiment has improved the effect of later step intermediate ion injection formation well region.
S130: the Semiconductor substrate 102 with described buffer oxide layer 106 is carried out ion inject, form well region 114.
As shown in Figure 8.
In the manufacture process of MOS device, the mode of utilizing ion to inject in Semiconductor substrate is mixed usually, forms doped region, also is called well region.For example can be in substrate when making NMOS doping P type ion, boron ion for example, formation has the P well region of certain boron ion concentration, and then in the P well region, form source area and drain region, like this in the position of the conducting channel between source area and the drain region because be injected into P type ion, therefore need higher threshold voltage could form conducting channel, thereby the P trap has played the effect of rising threshold voltage.Same also can at first form the N trap in the manufacturing process of PMOS, be used for improving threshold voltage.The process of injecting at ion needs form oxidation masking layer on the Semiconductor substrate 102 in order to prevent channeling effect before ion injects usually, the ion that injects is played the effect of buffering.In conventional method, can after STI, remove the buffer oxide layer 106 on the Semiconductor substrate usually, deposit forms the oxidation masking layer that the more smooth oxide skin(coating) of layer of surface injects as ion then.But think after the present inventor research that the process of removing the buffer oxide layer in the conventional method causes damage to Semiconductor substrate easily, the oxidation masking layer of later stage formation can produce compression to Semiconductor substrate like this, these factors can cause in the step of formation N well region or P well region of mixing, the N type ion of the part dosage that mixes or P type ion are to outdiffusion, thereby reduced the source area of later stage formation and the concentration of the dopant ion in the conducting channel between the source area, thereby the gate threshold voltage of the feasible semiconductor device that forms reduces.Therefore after STI, do not remove buffer oxide layer 106 among the present invention, directly be used as the oxidation masking layer that ion injects, like this because do not remove the step of buffer oxide layer 106, bring infringement therefore just can for Semiconductor substrate 106 yet, and there is not deposit to form the step of oxide skin(coating), therefore the compression that does not yet exist deposition process to bring so just can not influence the distribution of ion concentration in Semiconductor substrate 106 of doping, thereby improve threshold voltage.
The process that described ion injects can adopt method well known to those skilled in the art, for example earlier applies photoresist on nitride layer 108, carries out photoetching then, defines to carry out the P well region that ion injects or the position of N well region, carries out ion then and injects.The energy that ion injects and the thickness of dosage and buffer oxide layer 106 have direct relation, because if energy and dosage that ion injects are too big, buffer oxide layer 106 does not have the effect that cushions in the ion implantation process, just can not well reduce channeling effect, if ability and dosage that ion injects are too little, then the concentration that Semiconductor substrate is mixed is not enough, can not effectively improve threshold voltage.Therefore according to the thickness of buffer oxide layer, those skilled in the art can draw ion and inject energy and the dosage that is fit to, and for example the thickness of buffer oxide layer 106 is 50 dust to 100 dusts among the present invention, so ion implantation energy is 8KeV, and dosage is 12E/cm
2To 13E/cm
2
Because compression plays a role clearly at the MOS of short channel and narrow raceway groove device to the influence of the concentration that ion injects, therefore the present invention is applied in the effect preferably that has in the manufacturing process of short channel and narrow channel MOS device, for example channel length is less than or equal to 0.06um, and channel width is less than or equal in the MOS device of 0.5um.And because the length of raceway groove is shorter, even width is less so experiment showed, after nitride layer 108 removals that buffer oxide layer 106 surface are not the smooth especially effects that the later stage ion injects that yet can not have influence on.
Because the influence of boron ion and phosphonium ion compression chord is bigger, in other words, when ion is injected to boron ion and phosphonium ion, the compression of the oxidation masking layer of deposit makes the more serious of boron ion and phosphonium ion diffusion in the conventional method, thereby bigger to the concentration affects of boron ion and phosphonium ion in the conducting channel between source area and the drain region.Therefore comprise in one embodiment of the present of invention that the boron ion implantation ion forms the process of P trap or the process that ion injects phosphonium ion formation N trap 124.
S140: remove described buffer oxide layer 106.
This step can be utilized the method for CMP, and plasma etching or use acid solution clean, and in addition also can adopt method well known to those skilled in the art to remove.
S150: on Semiconductor substrate, form grid.
This step can adopt method well known to those skilled in the art, CVD chemical vapor deposition for example, and perhaps epitaxially grown mode forms grid layer 116.As shown in Figure 9, grid layer 116 etching are formed grid 118.
S160：
In the Semiconductor substrate 102 of grid 118 both sides, form source area and drain region.
This step can adopt method well known to those skilled in the art, and for example the mode of boron ion implantation ion or phosphonium ion forms source area 120 and drain region 122.
Embodiment two
A kind of formation method of semiconductor device well region please refer to Figure 10.
S210: the Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, described buffer oxide layer is positioned on the Semiconductor substrate outside the described shallow channel isolation area, and described nitride layer is positioned on the described buffer oxide layer.
This step is with the step S110 of embodiment one.
S220: remove described nitride layer 108.
The process of removing nitride layer 108 can adopt method well known to those skilled in the art, for example clean or chemico-mechanical polishing (CMP) with phosphoric acid solution, because phosphoric acid to the corrosivity of silicon dioxide a little less than, therefore present embodiment adopts phosphoric acid solution to clean, and has kept less to the infringement of oxide skin(coating) 106 like this when removing silicon nitride layer 108.
After above-mentioned steps, also can on buffer oxide layer 106, form the masking oxide layer.Also can remove the buffer oxide layer 106 of segment thickness, on remaining buffer oxide layer 106, form the masking oxide layer then.The method that forms the masking oxide layer can be physical vapor deposition (PVD) or chemical vapor deposition modes such as (CVD).Those skilled in the art can determine the thickness of the masking oxide layer of formation according to process conditions, the dosage of ion injection and the thickness of buffer oxide layer 106.For example the thickness sum of the thickness of masking oxide layer and buffering oxide skin(coating) 106 is 50 dusts-100 dusts.
Because remove the buffer oxide layer 106 surface meeting out-of-flatness after the nitride layer 108, and surface ratio buffer oxide layer 106 surface of the masking oxide layer that this step forms are more smooth, therefore improved the later step intermediate ion and injected the effect that forms well region.S230: the Semiconductor substrate 102 with described buffer oxide layer is carried out ion inject, form well region 114.
This step is with the step S130 of embodiment.
Present embodiment also can be applied in the manufacturing of bipolar transistor in addition.
Compare the resilient coating of the present invention with prior art by utilizing the buffer oxide layer that forms in the step formerly to inject as ion, and do not form oxidation masking layer in addition, eliminated in the process of removing oxide skin(coating) in the prior art infringement like this to Semiconductor substrate, also eliminated simultaneously and formed the compression that oxidation masking layer causes Semiconductor substrate, therefore reduced to mix when forming well region, dopant ion is to the phenomenon of outdiffusion, thereby improved the interior dopant ion concentration of conducting channel of later stage formation, improved threshold voltage.The experimental data that semiconductor device is tested as shown in figure 11.Abscissa is a grid width among Figure 11, ordinate is a threshold voltage, curve 301, curve 302 and curve 303 are the resolution charts that utilize the semiconductor device that manufacture method of the present invention makes, and curve 304 is the resolution charts that utilize the semiconductor device that the method for prior art makes.From figure, can significantly find out the threshold voltage height of the semiconductor device that the threshold voltage Billy who utilizes the semiconductor device that method of the present invention makes under the situation of same grid width makes with prior art.And along with reducing of grid width, advantage of the present invention is more obvious.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the manufacture method of a MOS device is characterized in that, comprises step:
Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, described buffer oxide layer is positioned on the Semiconductor substrate outside the described shallow channel isolation area, and described nitride layer is positioned on the described buffer oxide layer;
Remove described nitride layer;
Semiconductor substrate with described buffer oxide layer is carried out ion inject, form well region;
Remove described buffer oxide layer;
On Semiconductor substrate, form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
2. the manufacture method of MOS device as claimed in claim 1 is characterized in that, described forming process with Semiconductor substrate of buffer oxide layer and nitride layer is:
Semiconductor substrate is provided;
On described Semiconductor substrate, form the buffer oxide layer;
On described buffer oxide layer, form nitride layer;
To described Semiconductor substrate etching, form groove;
Form the trench liner oxide skin(coating) of covering groove sidewall and bottom surface;
Form the fill oxide layer in groove and on the nitride layer;
Planarization fill oxide layer exposes semiconducting nitride thing layer, and makes the top of groove and the semiconductor-based end be positioned at same plane.
3. the manufacture method of MOS device as claimed in claim 1 is characterized in that, the material of described buffer oxide layer comprises silicon dioxide, and the material of described nitride layer comprises silicon nitride.
4. the manufacture method of MOS device as claimed in claim 1 is characterized in that, described MOS device comprises any one in nmos device and the PMOS device.
5. the manufacture method of MOS device as claimed in claim 4 is characterized in that, the ion that described nmos device ion injects comprises the boron ion; The ion that PMOS device ion injects comprises phosphonium ion.
6. the manufacture method of MOS device as claimed in claim 1, it is characterized in that, after removing described nitride layer step, before the Semiconductor substrate with described buffer oxide layer is carried out the ion implantation step, can also be included in and form the masking oxide layer on the buffer oxide layer.
7. the formation method of a semiconductor device well region is characterized in that, comprises step:
Semiconductor substrate with buffer oxide layer and nitride layer is provided, in Semiconductor substrate, has shallow channel isolation area, described buffer oxide layer is positioned on the Semiconductor substrate outside the described shallow channel isolation area, and described nitride layer is positioned on the described buffer oxide layer;
Remove described nitride layer;
Semiconductor substrate with described buffer oxide layer is carried out ion inject, form well region.
8. the formation method of semiconductor device well region as claimed in claim 7 is characterized in that, described semiconductor device comprises nmos device and PMOS device.
9. the formation method of conductor device well region as claimed in claim 8 is characterized in that, the ion that described nmos device ion injects comprises the boron ion; The ion that PMOS device ion injects comprises phosphonium ion.
10. the formation method of semiconductor device well region as claimed in claim 7, it is characterized in that, after removing described nitride layer step, the Semiconductor substrate with described buffer oxide layer is carried out can also being included in formation masking oxide layer on the buffer oxide layer before the ion injection.
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Cited By (2)
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| CN106128945A (en) * | 2016-07-18 | 2016-11-16 | 上海集成电路研发中心有限公司 | A kind of ion injection method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106128945A (en) * | 2016-07-18 | 2016-11-16 | 上海集成电路研发中心有限公司 | A kind of ion injection method |
| CN112903087A (en) * | 2021-01-18 | 2021-06-04 | 中国兵器工业集团第二一四研究所苏州研发中心 | MEMS monolithic integration standard vector composite acoustic wave sensor and processing method thereof |
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Application publication date: 20100609 |