CN101727961A - Imbedded reconfigurable memorizer in programmable gate array - Google Patents
Imbedded reconfigurable memorizer in programmable gate array Download PDFInfo
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- CN101727961A CN101727961A CN200810224990A CN200810224990A CN101727961A CN 101727961 A CN101727961 A CN 101727961A CN 200810224990 A CN200810224990 A CN 200810224990A CN 200810224990 A CN200810224990 A CN 200810224990A CN 101727961 A CN101727961 A CN 101727961A
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Abstract
The invention discloses an imbedded reconfigurable memorizer in a programmable gate array. The imbedded reconfigurable memorizer is characterized in that: the memorizer comprises a storage unit array, an A port peripheral circuit, a B port peripheral circuit, and a word line selector and two bit line selectors configured between the A port peripheral circuit and a programmable gate array chip configuration layer; the storage unit array is a double-port storage unit array and is provided with an A port and a B port; the A port peripheral circuit is connected with the A port of the double-port storage unit array through the word line selector and the bit line selectors; and the B port peripheral circuit is directly connected with the B port of the double-port storage unit array. The imbedded reconfigurable memorizer meets the requirements of large-capacity storage of the programmable gate array, and achieves the aim of storage in a large-capacity chip.
Description
Technical field
(Field Programmable GateArray, FPGA) chip design field relate in particular to the design of embedded memory module in the fpga chip to the present invention relates to integrated circuit (IC) design and programmable gate array.In order to satisfy the demand of data storage capacities on a large amount of sheets of FPGA, the invention provides imbedded reconfigurable memorizer in a kind of programmable gate array.
Background technology
Storage resources has two kinds of implementations on the sheet of FPGA: particulate formula and coarse grain formula.So-called particulate formula is meant that each basic logic unit can be configured to a little storer, and several small memories are expanded by merging again.It does not need added logic, but storage density is lower, is applicable to the application that storage demand is few.And the coarse grain formula is embedded into jumbo memory module in the fpga chip exactly as mailbox memory, compares with the particulate formula to have the high advantage of storage density, is applicable to that data processing etc. needs the situation of storage space on a large amount of sheets.
Along with the FPGA application is increasingly extensive, especially in multimedia, communication and signal Processing field, the high capacity storage demand is more and more, and therefore embedded memory module becomes crucial resource in the fpga chip.In order to improve application flexibility and popularity, these memory modules need have certain restructural characteristics.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide imbedded reconfigurable memorizer in a kind of programmable gate array, to satisfy the demand of programmable gate array high capacity storage, reaches the purpose of storing on the high capacity sheet.
The present invention is the storer of a 18Kb, by periphery circuit design, has realized the various configurations pattern of storer, has improved its application flexibility and popularity.
(2) technical scheme
For achieving the above object, the technical solution used in the present invention is as follows:
Imbedded reconfigurable memorizer in a kind of programmable gate array, this storer comprises memory cell array, A port peripheral circuit, B port peripheral circuit, and a wordline selector and two bit line selector switchs between A port peripheral circuit and the programmable gate array chip configuration layer; This memory cell array is the dual port memory unit array, have A port and B port, A port peripheral circuit is connected with the A port of dual port memory unit array by wordline selector and bit line selector switch, and B port peripheral circuit directly is connected with the B port of dual port memory unit array.
In the such scheme, described memory cell array is made of 64 * 288 storage unit, and each storage unit is 6 pipe dual-port structures.
In the such scheme, described A port and B port have independently control signal and control circuit respectively, can independently carry out read or write.
In the such scheme, described A port peripheral circuit comprise pre-charge circuit and 4-1 MUX, sense amplifier, output select array, input select array, output bus switch matrix, input bus switch matrix, output buffer, input buffer, OK/column decoder and control circuit; Wherein, input buffer, input bus switch matrix, input select array to be connected successively with pre-charge circuit and 4-1 MUX, and this pre-charge circuit and 4-1 MUX, sense amplifier, output select array, output bus switch matrix to be connected successively with output buffer, OK/and column decoder and control circuit are connected in pre-charge circuit and 4-1 MUX, sense amplifier simultaneously, array, input selection array, output bus switch matrix, input bus switch matrix, output buffer and input buffer are selected in output.
In the such scheme, described outlet selector array is made of six groups of alternative multi path selector array, and every group selector array is controlled by an address signal; First group of 36 alternative selector switch is used for selecting 36 from 72 bit data, second group of 18 alternative selector switch is used for selecting 18 from 36 of last group of output, the 3rd group of 9 alternative selector switchs are used for selecting 9 from 18 of last group of output, the 4th group of 4 alternative selector switch are used for selecting 4 from 9 of last group of output 8, the 5th group of 2 alternative selector switchs are used for selecting 2 from 4 of last group of output, and the 6th group of 1 alternative selector switch is used for selecting 1 from 2 of last group of output.
In the such scheme, the pre-charge circuit in described pre-charge circuit and the 4-1 MUX is used to realize the function of write-after-read in the clock period, and read and write is to carry out at two different time windows.
In the such scheme, the structure of described B port peripheral circuit is identical with the structure of described A port peripheral circuit.
In the such scheme, at the programmable gate array configuration phase this programmable gate array is carried out initialization, utilize signal modesel that wordline selector and bit line selector switch are controlled, when modesel is low level, word line wl, bit line bl and bln from programmable gate array chip configuration layer enter A port peripheral circuit by the 4-1 MUX respectively, thereby configuration signal ' 1 ' or ' 0 ' is write storage unit in this storer by the A port, realize that this storer uses as ROM.
In the such scheme, this storer is divided into 3 kinds of mode of operations: write-after-read, write-then-read and output keep; Wherein, write-after-read promptly writes before the data at every turn, and the data that will store originally read and deliver on the output bus earlier; Write-then-read, the data that promptly newly write appear on the output bus simultaneously immediately; Output keeps, and promptly in the write operation process, output bus is unaffected, remains unchanged; Write-after-read is a default mode, can be used for The pipeline design.
(3) beneficial effect
Imbedded reconfigurable memorizer in this programmable gate array provided by the invention has following characteristics:
1, can be configured as ROM (read-only memory) (ROM) or normal static storer (SRAM);
2, have A, B and connect individual independently port, each port has control signal and the control circuit of oneself, can carry out read-write operation independently;
3,, this memory module can be configured to following 5 kinds of structures according to application need: 512 * 36,1k * 18,2k * 9,4k * 4,8k * 2,16k * 1;
4, support three kinds and optionally write pattern, three kinds of different output states when correspondence writes data comprise " write-after-read " pattern that is applicable to The pipeline design;
5, can independently put ' 0 ' or put ' 1 ' to every output
6, for fpga chip provides storage resources on the special-purpose high capacity sheet, make fpga chip can expire the demand of higher data storage capacity;
7, can be used as ROM and use, under configuration mode, memory cell array is carried out initialization; Also can so-called normal static random access memory use, under logical schema, storage unit is read and write.
8, data width can be selected, and can be configured as 512 * 36,1k * 18,2k * 9,4k * 4,8k * 2, these five kinds of tactic patterns of 16k * 1.36 input buss are shared in the input of each pattern, and 36 output buss are shared in output, and use ad-hoc location in 36.
9, this storer can be expanded, and can obtain wideer or darker storer by the cascade of a plurality of storeies.
Description of drawings
Fig. 1 is the structural representation of imbedded reconfigurable memorizer among the FPGA provided by the invention;
Fig. 2 is the circuit diagram of 6 pipe dual port memory unit;
Fig. 3 is three kinds of synoptic diagram that write pattern;
Fig. 4 is precharge circuit diagram;
Fig. 5 is the synoptic diagram that array is selected in output;
Fig. 6 is the synoptic diagram of output bus switch matrix.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the structural representation of imbedded reconfigurable memorizer among the FPGA provided by the invention.This storer comprises memory cell array, A port peripheral circuit, B port peripheral circuit, and a wordline selector and two bit line selector switchs between A port peripheral circuit and the programmable gate array chip configuration layer; This memory cell array is the dual port memory unit array, have A port and B port, A port peripheral circuit is connected with the A port of dual port memory unit array by wordline selector and bit line selector switch, and B port peripheral circuit directly is connected with the B port of dual port memory unit array.
Memory cell array is made of 64 * 288 storage unit, and each storage unit is 6 pipe dual-port structures.A port and B port have independently control signal and control circuit respectively, can independently carry out read or write.
A port peripheral circuit comprise pre-charge circuit and 4-1 MUX, sense amplifier, output select array, input select array, output bus switch matrix, input bus switch matrix, output buffer, input buffer, OK/column decoder and control circuit; Wherein, input buffer, input bus switch matrix, input select array to be connected successively with pre-charge circuit and 4-1 MUX, and this pre-charge circuit and 4-1 MUX, sense amplifier, output select array, output bus switch matrix to be connected successively with output buffer, OK/and column decoder and control circuit are connected in pre-charge circuit and 4-1 MUX, sense amplifier simultaneously, array, input selection array, output bus switch matrix, input bus switch matrix, output buffer and input buffer are selected in output.The structure of B port peripheral circuit is identical with the structure of described A port peripheral circuit.
The outlet selector array is made of six groups of alternative multi path selector array, and every group selector array is controlled by an address signal; First group of 36 alternative selector switch is used for selecting 36 from 72 bit data, second group of 18 alternative selector switch is used for selecting 18 from 36 of last group of output, the 3rd group of 9 alternative selector switchs are used for selecting 9 from 18 of last group of output, the 4th group of 4 alternative selector switch are used for selecting 4 from 9 of last group of output 8, the 5th group of 2 alternative selector switchs are used for selecting 2 from 4 of last group of output, and the 6th group of 1 alternative selector switch is used for selecting 1 from 2 of last group of output.
At the programmable gate array configuration phase this programmable gate array is carried out initialization, utilize signal modesel that wordline selector and bit line selector switch are controlled, when modesel is low level, word line wl, bit line bl and bln from programmable gate array chip configuration layer enter A port peripheral circuit by the 4-1 MUX respectively, thereby configuration signal ' 1 ' or ' 0 ' is write storage unit in this storer by the A port, realize that this storer uses as ROM.
As shown in Figure 3, the state of output bus during according to write operation, this storer are divided into 3 kinds of mode of operations: write-after-read, write-then-read and output keep; Wherein, write-after-read promptly writes before the data at every turn, and the data that will store originally read and deliver on the output bus earlier; Write-then-read, the data that promptly newly write appear on the output bus simultaneously immediately; Output keeps, and promptly in the write operation process, output bus is unaffected, remains unchanged; Write-after-read is a default mode, can be used for The pipeline design.
In order to realize the selection of 5 kinds of data widths, designed I/O and selected array, input/output bus switch matrix.Fig. 5 has provided the structural drawing of outlet selector array, and it is made up of six groups of alternative multi path selector array, and every group selector array is controlled by an address signal.First group of 36 alternative selector switch is responsible for selecting 36 from 72 bit data, second group of 18 alternative selector switch is responsible for selecting 18 from last group of 36 of exporting, the 3rd group of 9 alternative selector switchs are responsible for selecting 9 from last group of 18 of exporting, the 4th group of 4 alternative selector switch are responsible for selecting 4 among from last group of output 98, the 5th group of 2 alternative selector switchs are responsible for selecting 2 from last group of 4 of exporting, and the 6th group of 1 alternative selector switch is responsible for selecting 1 from last group of 2 of exporting.
Whether control respectively organizes the work of alternative selector switch according to configuration information, for example if realize that bit wide is 18 mode of operations, 36 alternative selector switchs are responsible for selecting 36 from 72 bit data so, second group of 18 alternative selector switch is responsible for selecting 18 from last group of 36 of exporting, and all the other four group selector arrays then are switched off.Except 18 these group data selecting, other each signals all are changed to 0.The output bus switch matrix is responsible for bit wide with outlet selector array output and is respectively 36,18,9,4,2 and 1 data and reasonably is distributed in 36 output data bus.Bit wide is that 36 data occupy in 36 buses fully, 0,2, to be used for bit wide be 18 data to 4...32,34,36,1,5,9,13,17,23,27,31,35 to be used for bit wide be 9 data, 3,11,25,33 to be used for bit wide be 4 data, 7,24 to be used for bit wide be 2 data, and 15 to be used for bit wide be 1 data.Junction shown in the figure is made of the transmission gate of configuration signal control, and whether configuration signal decision conducting.Input selects the structure of array, input bus switch matrix identical with output, and just data flow direction is opposite.
In order to realize the function of write-after-read in the clock period, read and write just must be carried out at two different time windows.Design is as the pre-charge circuit of Fig. 4 (a) for this reason.Dw, dwn are the data that preparation writes, and are produced through certain logic by input signal; Dr, drn are the data that preparation is read, through delivering to output terminal after the processing of circuit such as sense amplifier.Yi is a precharge control signal, and rdctl is a read control signal, and wtctl is a write control signal, and their sequential relationship is shown in Fig. 4 (b).Yi is that two bit lines all are pulled to VDD between low period, and read-write operation all is closed.The high level window of yi is about 0.5ns, carries out read operation (rdctl drags down) with half window time earlier around here, carries out write operation (wtctl drags down) with half window time of back again.Write paths is closed when reading like this, and read-out path is closed when writing, thereby has realized reading earlier writing behind the legacy data purpose of new data.The pattern of write-then-read then is output register directly to be delivered in input arrive output bus then.Output keeps also realizing by output register.
Read operation process (is example with the A port): the word line that code translator produces is opened the NMOS transfer tube in the storage unit, the bit line that the data of storage arrive through transfer tube, through bit line selector switch (then not needing through this link) for the B port, enter pre-charge circuit and four and select a MUX, amplify through sense amplifier again, obtain a bit wide and be 72 data.These data enter output and select array, obtain bit wide and be respectively 5 groups of data of 36,18,9,4,2 and 1, according to configuration requirement wherein one group of data enter the output bus selection matrix, be distributed on 36 output buss by designing requirement.
Write operation process (is example with the A port): the input data at first enter input buffer, be cushioned and be positive negative signal, enter positive input bus selection matrix and negative input bus selection matrix respectively, the output bit wide is respectively 5 groups of data of 36,18,9,4,2 and 1, enters positive input respectively according to the positive negative data of a certain group of exterior arrangement information and selects array and negative input to select array.In selecting array, according to different addresses, data are selected to be distributed in 72 signal line, enters precharge and four subsequently and selects one to select in the circuit, four selects a selector circuit to be assigned in 288 pairs of bit line by this again.Bit line enters memory cell array then, thereby data are write.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. imbedded reconfigurable memorizer in the programmable gate array, it is characterized in that, this storer comprises memory cell array, A port peripheral circuit, B port peripheral circuit, and a wordline selector and two bit line selector switchs between A port peripheral circuit and the programmable gate array chip configuration layer; This memory cell array is the dual port memory unit array, have A port and B port, A port peripheral circuit is connected with the A port of dual port memory unit array by wordline selector and bit line selector switch, and B port peripheral circuit directly is connected with the B port of dual port memory unit array.
2. imbedded reconfigurable memorizer in the programmable gate array according to claim 1 is characterized in that, described memory cell array is made of 64 * 288 storage unit, and each storage unit is 6 pipe dual-port structures.
3. imbedded reconfigurable memorizer in the programmable gate array according to claim 1 is characterized in that, described A port and B port have independently control signal and control circuit respectively, can independently carry out read or write.
4. imbedded reconfigurable memorizer in the programmable gate array according to claim 1, it is characterized in that, described A port peripheral circuit comprise pre-charge circuit and 4-1 MUX, sense amplifier, output select array, input select array, output bus switch matrix, input bus switch matrix, output buffer, input buffer, OK/column decoder and control circuit; Wherein, input buffer, input bus switch matrix, input select array to be connected successively with pre-charge circuit and 4-1 MUX, and this pre-charge circuit and 4-1 MUX, sense amplifier, output select array, output bus switch matrix to be connected successively with output buffer, OK/and column decoder and control circuit are connected in pre-charge circuit and 4-1 MUX, sense amplifier simultaneously, array, input selection array, output bus switch matrix, input bus switch matrix, output buffer and input buffer are selected in output.
5. imbedded reconfigurable memorizer in the programmable gate array according to claim 4 is characterized in that, described outlet selector array is made of six groups of alternative multi path selector array, and every group selector array is controlled by an address signal; First group of 36 alternative selector switch is used for selecting 36 from 72 bit data, second group of 18 alternative selector switch is used for selecting 18 from 36 of last group of output, the 3rd group of 9 alternative selector switchs are used for selecting 9 from 18 of last group of output, the 4th group of 4 alternative selector switch are used for selecting 4 from 9 of last group of output 8, the 5th group of 2 alternative selector switchs are used for selecting 2 from 4 of last group of output, and the 6th group of 1 alternative selector switch is used for selecting 1 from 2 of last group of output.
6. imbedded reconfigurable memorizer in the programmable gate array according to claim 4, it is characterized in that, pre-charge circuit in described pre-charge circuit and the 4-1 MUX, be used to realize the function of write-after-read in the clock period, read and write is to carry out at two different time windows.
7. imbedded reconfigurable memorizer in the programmable gate array according to claim 4 is characterized in that, the structure of described B port peripheral circuit is identical with the structure of described A port peripheral circuit.
8. imbedded reconfigurable memorizer in the programmable gate array according to claim 1, it is characterized in that, at the programmable gate array configuration phase this programmable gate array is carried out initialization, utilize signal modesel that wordline selector and bit line selector switch are controlled, when modesel is low level, word line wl from programmable gate array chip configuration layer, bit line bl and bln enter A port peripheral circuit by the 4-1 MUX respectively, thereby configuration signal ' 1 ' or ' 0 ' is write storage unit in this storer by the A port, realize that this storer uses as ROM.
9. imbedded reconfigurable memorizer in the programmable gate array according to claim 1 is characterized in that, this storer is divided into 3 kinds of mode of operations: write-after-read, write-then-read and output keep; Wherein, write-after-read promptly writes before the data at every turn, and the data that will store originally read and deliver on the output bus earlier; Write-then-read, the data that promptly newly write appear on the output bus simultaneously immediately; Output keeps, and promptly in the write operation process, output bus is unaffected, remains unchanged; Write-after-read is a default mode, can be used for The pipeline design.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107464207A (en) * | 2017-07-17 | 2017-12-12 | 南京华磊易晶微电子有限公司 | 3D graphics based on reconfigurable data streaming system chip array renders acceleration system |
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| US4984214A (en) * | 1989-12-05 | 1991-01-08 | International Business Machines Corporation | Multiplexed serial register architecture for VRAM |
| US7002867B2 (en) * | 2002-09-25 | 2006-02-21 | Infineon Technologies Aktiengesellschaft | Refresh control circuit for ICs with a memory array |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107464207A (en) * | 2017-07-17 | 2017-12-12 | 南京华磊易晶微电子有限公司 | 3D graphics based on reconfigurable data streaming system chip array renders acceleration system |
| CN107464207B (en) * | 2017-07-17 | 2020-06-02 | 南京华磊易晶微电子有限公司 | 3D (three-dimensional) graphics rendering acceleration system based on reconfigurable data stream system chip array |
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