CN101727011A - Alignment method of lithography machine - Google Patents
Alignment method of lithography machine Download PDFInfo
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- CN101727011A CN101727011A CN200810043868A CN200810043868A CN101727011A CN 101727011 A CN101727011 A CN 101727011A CN 200810043868 A CN200810043868 A CN 200810043868A CN 200810043868 A CN200810043868 A CN 200810043868A CN 101727011 A CN101727011 A CN 101727011A
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Abstract
The invention discloses an alignment method of a lithography machine, which comprises a two-stage alignment method. A first stage is similar to the prior method and is wafer normal region alignment for obtaining 6 parameters of a wafer alignment model 1: Tx1, Ty1, Ex1, Ey1, Rotaion1 and Ortho1; and the second stage is wafer twisted region alignment for obtaining 6 parameters of a wafer alignment model 2: Tx2, Ty2, Ex2, Ey2, Rotaion2 and Ortho2. The lithography machine respectively regulates exposure forms according to two groups of different parameters. In consideration of the special wafer deformation state of the twisted region, the method is capable of subjecting the place to registration correction so as to obtain a satisfactory registration precision.
Description
Technical field
The present invention relates to the process that a kind of semiconductor is made, relate in particular to a kind of litho machine alignment methods.
Background technology
Wafer processes layer by layer through series of steps, and for making the device operate as normal, necessary alignment is in definite accuracy between layer and the layer.Along with live width is more and more littler, alignment precision requires more and more stricter.On semi-conductive production technology, layer is aimed at realization with the alignment between the layer by litho machine, principle is: during the processing ground floor, ad-hoc location at exposing unit is provided with some alignment marks, after the processing during each layer litho machine measure the coordinate of the alignment mark that some ground floors stay, fit out the wafer alignment model then, exposure then, this model is used to reflect the wafer deformation state that causes owing to technology, and model is made up of 6 parameters: translation (each one of the transverse axis and the longitudinal axis, Tx, Ty), expand (each Ex of the transverse axis and the longitudinal axis, Ey), rotation (Rotation) and orthogonality (Ortho).Litho machine according to this model adjustment exposure form (such as the imaging multiplying power of stepping rate, camera lens etc.) thus realize good alignment precision.
When present litho machine alignment methods was used, this model can depart from coordinate the to a certain degree exposing unit eliminating of (just wafer deformation state herein and integral body differ greatly) of this model, so can cause alignment bad in this exposing unit.But in the process of wafer, because technological reason (particularly high-temperature heat treatment) wafer inside exists stress will inevitably cause the bird caging distortion.Therefore under existing litho machine alignment methods, not will consider this regional torsional deformation, thereby will inevitably cause the interlayer alignment bad.As shown in Figure 1, measure 4 alignment mark X, draw wafer alignment model parameter Tx1, Ty1, Ex1, Ey1, Rotation1 and Ortho1, wafer lower-left this model of coordinate abnormal deviation can be got rid of, and it is bad that the result should locate alignment.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of litho machine alignment methods, and it is bad that this method can be revised the local alignment that is caused by the wafer distortion, thereby obtain better alignment precision.
For solving the problems of the technologies described above, the invention provides a kind of litho machine alignment methods, comprise two stage alignment methods, the phase one is that the wafer normal region is aimed at, and comprises the steps: that (1) is provided with some alignment marks on exposing unit; (2) litho machine is measured the coordinate of the anterior layer alignment mark of some exposing units; (3) fit out wafer alignment model 1; (4) draw the bad wafer warped regions of alignment after the exposure; Subordinate phase is that the wafer warped regions is aimed at, and comprises the steps: that (A) is provided with some alignment marks in the wafer warped regions; (B) litho machine is measured the coordinate of alignment mark; (C) fit out wafer alignment model 2; (D) carry out the alignment correction after the exposure.
Be on the Cutting Road at exposing unit on the exposing unit described in the step (1).
Be on the Cutting Road of wafer warped regions in the wafer warped regions described in the step (A).
Described step (3) fits out wafer alignment model 1 and adopts least square method.
Described step (C) fits out wafer alignment model 2 and adopts least square method.
Wafer alignment model 1 described in the step (3) is made up of following 6 parameters: translation transverse axis parameter Tx1, translation longitudinal axis parameter Ty1, expansion transverse axis parameter Ex1, expansion longitudinal axis parameter Ey1, rotation parameter Rotation1 and orthogonality parameter Ortho1.
Wafer alignment model 2 described in the step (C) is made up of following 6 parameters: translation transverse axis parameter Tx2, translation longitudinal axis parameter Ty2, expansion transverse axis parameter Ex2, expansion longitudinal axis parameter Ey2, rotation parameter Rotation2 and orthogonality parameter Ortho2.
Compare with prior art, the present invention has following beneficial effect: increased on the basis that the present invention aims in existing method wafer normal region the wafer warped regions is done aligning again, owing to considered the special wafer deformation state of warped regions, thereby can carry out the alignment correction to this place, obtain satisfied alignment precision.
Description of drawings
Fig. 1 is the synoptic diagram that carries out the interlayer alignment by present litho machine alignment methods, and wherein, X represents alignment mark;
Fig. 2 is the synoptic diagram that carries out the interlayer alignment by litho machine alignment methods of the present invention, and wherein, X represents alignment mark.
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
As shown in Figure 2, the present invention sets up two stage alignment methods, phase one and present method roughly the same, promptly (same Fig. 1) aimed in the wafer normal region, when comprising the steps: (1) processing ground floor, on the ad-hoc location (normally Cutting Road) of exposing unit, some alignment marks are set; (2) after the processing during each layer, litho machine is measured the coordinate of the alignment mark that some ground floors stay; (3) fit out wafer alignment model 1 (adopting least square method usually); (4) exposure then; This wafer alignment model 1 is used to reflect the whole deformed state of the wafer that causes owing to technology, and this model 1 is made up of following 6 parameters: translation transverse axis parameter Tx1, translation longitudinal axis parameter Ty1, expansion transverse axis parameter Ex1, expansion longitudinal axis parameter Ey1, rotation parameter Rotation1 and orthogonality parameter Ortho1.Show that wafer lower-left this model of coordinate abnormal deviation can be got rid of after the phase one aims at, it is bad that the result should locate alignment.Subordinate phase, wafer warped regions are aimed at (see Fig. 2 phase one aims at the lower left corner wafer warped regions of back demonstration), comprise the steps: that (1) is provided with some alignment marks on wafer warped regions (normally Cutting Road); (2) litho machine is measured the coordinate of alignment mark; (3) fit out wafer alignment model 2 (adopting least square method usually); (4) exposure then; This wafer alignment model 2 is used to reflect the wafer deformation state of the warped regions that causes owing to technology, and this model 2 is made up of following 6 parameters: translation transverse axis parameter Tx2, translation longitudinal axis parameter Ty2, expansion transverse axis parameter Ex2, expansion longitudinal axis parameter Ey2, rotation parameter Rotation2 and orthogonality parameter Ortho2.Litho machine is adjusted the exposure form respectively according to above two groups of different parameters (Tx1, Ty1, Ex1, Ey1, Rotation1 and Ortho1) and (Tx2, Ty2, Ex2, Ey2, Rotation2 and Ortho2).Under the method, by the wafer warped regions is done aligning again, owing to considered the special wafer deformation state of warped regions, thus can carry out the alignment correction to this place, considered the deformed state of each exposing unit, can obtain satisfied alignment precision.
Claims (7)
1. litho machine alignment methods is characterized in that: comprise two stage alignment methods, the phase one is that the wafer normal region is aimed at, and comprises the steps: that (1) is provided with some alignment marks on exposing unit; (2) litho machine is measured the coordinate of the anterior layer alignment mark of some exposing units; (3) fit out wafer alignment model 1; (4) draw the bad wafer warped regions of alignment after the exposure; Subordinate phase is that the wafer warped regions is aimed at, and comprises the steps: that (A) is provided with some alignment marks in the wafer warped regions; (B) litho machine is measured the coordinate of alignment mark; (C) fit out wafer alignment model 2; (D) carry out the alignment correction after the exposure.
2. litho machine alignment methods as claimed in claim 1 is characterized in that: be on the Cutting Road at exposing unit on the exposing unit described in the step (1).
3. litho machine alignment methods as claimed in claim 1 is characterized in that: be on the Cutting Road of wafer warped regions in the wafer warped regions described in the step (A).
4. litho machine alignment methods as claimed in claim 1 is characterized in that: described step (3) fits out wafer alignment model 1 and adopts least square method.
5. litho machine alignment methods as claimed in claim 1 is characterized in that: described step (C) fits out wafer alignment model 2 and adopts least square method.
6. litho machine alignment methods as claimed in claim 1 is characterized in that: the wafer alignment model 1 described in the step (3) is made up of following 6 parameters: translation transverse axis parameter Tx1, translation longitudinal axis parameter Ty, expansion transverse axis parameter Ex1, expansion longitudinal axis parameter Ey1, rotation parameter Rotation1 and orthogonality parameter Ortho1.
7. litho machine alignment methods as claimed in claim 1 is characterized in that: the wafer alignment model 2 described in the step (C) is made up of following 6 parameters: translation transverse axis parameter Tx2, translation longitudinal axis parameter Ty2, expansion transverse axis parameter Ex2, expansion longitudinal axis parameter Ey2, rotation parameter Rotation2 and orthogonality parameter Ortho2.
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| CN2008100438684A CN101727011B (en) | 2008-10-28 | 2008-10-28 | Alignment method of lithography machine |
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| CN101727011B CN101727011B (en) | 2011-08-24 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104281009A (en) * | 2013-07-12 | 2015-01-14 | 台湾积体电路制造股份有限公司 | Lithographic Overlay Sampling |
| CN105988305A (en) * | 2015-02-28 | 2016-10-05 | 上海微电子装备有限公司 | Silicon wafer pre-aligning method |
| CN110631518A (en) * | 2019-09-25 | 2019-12-31 | 上海华力集成电路制造有限公司 | Wafer surface flatness detection and incomplete exposure unit flatness detection compensation method |
| WO2022022069A1 (en) * | 2020-07-31 | 2022-02-03 | 长鑫存储技术有限公司 | Photolithography alignment method and system |
| US11782411B2 (en) | 2021-07-28 | 2023-10-10 | Kla Corporation | System and method for mitigating overlay distortion patterns caused by a wafer bonding tool |
| US11829077B2 (en) | 2020-12-11 | 2023-11-28 | Kla Corporation | System and method for determining post bonding overlay |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1279584C (en) * | 2002-11-25 | 2006-10-11 | 南亚科技股份有限公司 | Multiple alignment mark and method |
| TW200704146A (en) * | 2005-02-21 | 2007-01-16 | Fuji Photo Film Co Ltd | Plotting method, plotting device, plotting system and correction method |
| CN100394306C (en) * | 2005-04-04 | 2008-06-11 | 中国科学院微电子研究所 | Prepn process of exposure registering mark for mixing and matching between electron beam and optical device |
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2008
- 2008-10-28 CN CN2008100438684A patent/CN101727011B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104281009A (en) * | 2013-07-12 | 2015-01-14 | 台湾积体电路制造股份有限公司 | Lithographic Overlay Sampling |
| CN104281009B (en) * | 2013-07-12 | 2016-05-04 | 台湾积体电路制造股份有限公司 | Photoetching overlap sampling |
| CN105988305A (en) * | 2015-02-28 | 2016-10-05 | 上海微电子装备有限公司 | Silicon wafer pre-aligning method |
| CN105988305B (en) * | 2015-02-28 | 2018-03-02 | 上海微电子装备（集团）股份有限公司 | Wafer pre-alignment method |
| US10416578B2 (en) | 2015-02-28 | 2019-09-17 | Shanghai Micro Electronics Equipment (Group) Co., Ltd. | Substrate pre-alignment method |
| CN110631518A (en) * | 2019-09-25 | 2019-12-31 | 上海华力集成电路制造有限公司 | Wafer surface flatness detection and incomplete exposure unit flatness detection compensation method |
| CN110631518B (en) * | 2019-09-25 | 2021-06-15 | 上海华力集成电路制造有限公司 | Wafer surface flatness detection and incomplete exposure unit flatness detection compensation method |
| WO2022022069A1 (en) * | 2020-07-31 | 2022-02-03 | 长鑫存储技术有限公司 | Photolithography alignment method and system |
| US11829077B2 (en) | 2020-12-11 | 2023-11-28 | Kla Corporation | System and method for determining post bonding overlay |
| US11782411B2 (en) | 2021-07-28 | 2023-10-10 | Kla Corporation | System and method for mitigating overlay distortion patterns caused by a wafer bonding tool |
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|---|---|
| CN101727011B (en) | 2011-08-24 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131218 |
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Effective date of registration: 20131218 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |