CN101719378A - Data sensing device and data sensing method - Google Patents
Data sensing device and data sensing method Download PDFInfo
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- CN101719378A CN101719378A CN200910252154A CN200910252154A CN101719378A CN 101719378 A CN101719378 A CN 101719378A CN 200910252154 A CN200910252154 A CN 200910252154A CN 200910252154 A CN200910252154 A CN 200910252154A CN 101719378 A CN101719378 A CN 101719378A
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Abstract
The invention provides a data sensing device and a data sensing method. The data sensing device comprises a plurality of storage units, a plurality of data lines, a plurality of sensing amplifiers and at least one precharge circuit, wherein the storage units are used for storing data; the data lines are respectively coupled to the storage units and are used for controlling the reading or the writing of the storage units; bit lines are respectively coupled to the storage units and are used for outputting the data stored in the storage units; the sensing amplifiers are respectively coupled to the bit lines and are used for amplifying the data output by the storage units; and the precharge circuit is used for setting a preset period according to a first synchronous signal, a precharge signal is generated in the preset period, and the storage units and the sensing amplifiers are charged through the data lines.
Description
Technical field
The present invention is relevant for a kind of data sensing device, but particularly about a kind of data sensing device of pre-charge.
Background technology
Along with the progress of manufacture of semiconductor, the area and the operating voltage of electric crystal are more and more littler, make that now electronic circuit can be more and more at a high speed and also microminiaturization more and more of chip area.
Yet in memory circuitry, for example: (Dynamic RandomAccess Memory DRAM), has comprised many data lines (Data Line) and bit line (Bit line) to dynamic RAM.
And when the capacity of storer increases gradually, will make that data line and bit circuit are elongated, data line and bit line will exist the phenomenon of signal accumulation.Shown in Figure 1A, if the logical value of data line signal is not always fixedly the time, the logical zero that shows among the figure, 1,0,1 for example, this moment, the phenomenon of signal accumulation was not obvious or do not exist, and circuit can correctly sense logical zero, 1,0,1 data; But shown in Figure 1B, when those data lines receive the signal of identical logical values for a long time, as show among the figure 0,0,0,1 when continuously receiving three logical zeros, it is suitable serious that the phenomenon of signal accumulation often becomes, the scope of adding accumulator system fast operation, operating voltage is little, when being easy to cause the logical value conversion, the situation that logical value can't correctly be changed takes place, and the data that for example sense become logical zero, 0,0,0.So, will the mistake that write and read of memory data take place.
Summary of the invention
One of purpose of the present invention is a kind of data sensing device to be provided, the pre-charge of short time can be provided.
One of purpose of the present invention is that a kind of data sensing device is being provided, and can solve the problem of data read errors that signal accumulation causes.
One embodiment of the invention provide a kind of data sensing device, according to the running of one first synchronizing signal.This data sensing device includes a plurality of storage unit, a plurality of data line, a plurality of sensing amplifier, at least one pre-charge circuit.Those storage unit are in order to storage data.Data line is coupled to those storage unit respectively, and reading or writing in order to the control store unit.And the bit line is coupled to storage unit is stored in storage unit in order to output data respectively.Sensing amplifier then is coupled to the bit line respectively, the data of exporting in order to amplifying and storage unit.And pre-charge circuit in order to set according to first synchronizing signal one default during, and during this is default, produce a precharging signal, see through data line storage unit and sensing amplifier charged.
One embodiment of the invention provide a kind of pre-charge circuit, provide precharge in order to the objective circuit that produces cumulative errors at the signal transmission, and this pre-charge circuit includes a synchronous controller, a delay circuit and a precharge pulse generator.This isochronous controller produces one second synchronizing signal according to a read-write and one first synchronizing signal, and wherein the running of first synchronizing signal and objective circuit is synchronous.Delay circuit is in order to delay control one synchronous signal, to produce the 3rd synchronizing signal that postpones.And the precharge pulse generator produces this precharging signal in order to according to second synchronizing signal and the 3rd synchronizing signal;
Wherein, pre-charge circuit according to first synchronizing signal set one default during, and during this is default, produce precharging signal, to this objective circuit charging.
One embodiment of the invention provide a kind of data sensing method, are applicable to storage arrangement, and this method includes the following step: at first, receive a synchronous signal.Then, according to synchronizing signal set one default during, and during this is default, produce a precharging signal.A data line that sees through this storage arrangement afterwards charges time of a predetermined width to a storage unit of storer and a sensing amplifier.
Technology of the present invention is utilized the technology of pre-charge, objective circuit is charged the time of a predetermined width during default in one, and can solve the problem of the various circuit signals accumulation data read errors that cause.
Description of drawings
Figure 1A shows the signal waveforms under the known techniques normal condition.
Figure 1B shows the oscillogram of known techniques signal accumulation phenomenon.
Fig. 2 A shows the synoptic diagram of the data sensing device of one embodiment of the invention.
The signal waveforms of Fig. 2 B displayed map 2A.
Fig. 3 A shows the synoptic diagram of the pre-charge circuit of one embodiment of the invention.
The signal waveforms of Fig. 3 B displayed map 3A.
Fig. 4 shows the process flow diagram of the data sensing method of one embodiment of the invention.
Description of reference numerals:
The 200-data sensing device; The 200a-memory array circuit; The 200b-control circuit; The 201-data line; 202-bit line; The 203-sensing amplifier; The 204-storage unit; The 205-data line switch; 200c-pre-charge control circuit; The 200c1-isochronous controller; The 200c2-delay circuit; 200c3-precharge pulse generator.
Embodiment
Please consult Fig. 2 A, Fig. 2 B simultaneously.Fig. 2 A shows the synoptic diagram of the data sensing device partial circuit of one embodiment of the invention; The signal waveforms of Fig. 2 B displayed map 2A data sensing device.
Shown in Fig. 2 A, data sensing device 200 includes a memory array circuit 200a, a control circuit 200b, at least one pre-charge circuit 200c.
This memory array circuit 200a includes plurality of data lines (Data lines) 201, most bar bit line (Bit lines) 202, most sensing amplifiers (Sense Amplifier) 203, most storage unit (memorycell) 204, most data wiretaps 205, and it couples relation as shown in the figure.Data line 201 sees through data line switch 205 and reads the data of storage unit 204 or write data to storage unit 204; Sensing amplifier 203 is coupled to bit line 202, in order to amplify the data-signal that bit line 202 is exported.
Control circuit 200b operates, reads and writes in order to control this memory array circuit 200a ... waits processing.
Pre-charge control circuit 200c couples memory array 200a, in order to export a precharging signal (Nimble pre-charge signal) P memory array 200a is carried out the pre-charge action.Wherein, this precharging signal P can be a pulse signal (Pulse).
Below describe the operation principles of data sensing device 200 of the present invention in detail.
The data sensing device 200 of the embodiment of the invention has designed a pre-charge circuit 200c, and in order to memory array 200a is carried out pre-charge, its charging modes please refer to Fig. 2 B.The precharging signal P that pre-charge circuit 200c is exported in the present embodiment can one default during Du (duration) to the charge width of a preset time t of data line signal.One embodiment, shown in Fig. 2 B, pre-charge circuit 200c during default-per half clock pulse cycle is (during as time T 0～T1), see through 201 pairs of data wiretaps of data line 205 with preset time t (as time T 1～T1 ') less than the width of 0.5 nanosecond (n) s and carry out the pre-charge action with sensing amplifier 203, make the voltage level of data line signal DLQ can return to a predetermined voltage in per half clock pulse cycle, the problem that reduces signal accumulation takes place.So, can avoid the delay of logical value when conversion time of origin of data line signal, prevent that sensing amplifier from reading or writing data make a mistake (error).
The person of noting, among the embodiment, pre-charge circuit 200c sets default during the time width t of Du and precharging signal P can design arbitrarily according to the demand of circuit designers or the characteristic of storer.For example, pre-charge circuit 200c sees through data line data wiretap 205 and sensing amplifier 203 is carried out pre-charge once during per 1 synchronizing signal S1 cycle, or per 1.5 synchronizing signal S1 cycles during see through data line data wiretap 205 and sensing amplifier 203 carried out pre-charge once ... etc.One embodiment, pre-charge circuit 200c only need to carry out pre-charge and get final product before the situation of signal accumulation exceeds the tolerable scope.
Note that in one embodiment of the invention that pre-charge circuit 200b sees through data line data wiretap and sensing amplifier are carried out pre-charge; But the present invention can cause the circuit of data read errors because of the phenomenon of signal accumulation not as limit in any circuit of storer, all can use.Certainly, the various circuit of technology of the present invention except memory circuitry, for example processor, various chip, application chip ... etc., as long as there is the problem that the signal accumulation phenomenon takes place all applicable, and all fall into patent claim of the present invention.
Please also refer to figure A, Fig. 3 B, Fig. 3 A shows the synoptic diagram of the pre-charge circuit of one embodiment of the invention; The signal waveforms of Fig. 3 B displayed map 3A.
This pre-charge circuit 200c includes a synchronous controller 200c1, a delay circuit 200c2 and a precharge pulse generator 200c3.Its function mode is as follows:
Isochronous controller 200c1 produces one second synchronizing signal S2 according to a read-write R/W and one first synchronizing signal S1.Among one embodiment, when isochronous controller 200c1 is logical zero according to read-write R/W, output and the second anti-phase each other synchronizing signal S2 of the first synchronizing signal S1.
Delay circuit 200c2 postpones a schedule time with the first synchronizing signal S1, to produce one the 3rd synchronizing signal S3.
Then, precharge pulse generator 206c produces the precharging signal P of width t according to the second synchronizing signal S2 and the 3rd synchronizing signal S3.Note that the first synchronizing signal S1 and the 3rd synchronizing signal S3 are same-phase signal, but have a phase differential, this phase differential differs the time of a width t in fact.
The data sensing device 200 of one embodiment of the invention be a dynamic random access memory means (Dynamic Random Access Memory, DRAM), wherein, when this read-write R/W was logical zero, data sensing device 200 was carried out the action of reading of data; When read-write R/W was logical one, data sensing device 200 write the action of data.
Fig. 4 shows the data sensing method of one embodiment of the invention, is applicable to storage arrangement, and this method includes the following step:
Step S402: beginning.
Step S404: receive a synchronous signal.
Step S406: according to this synchronizing signal set one default during, and during this is default, produce a precharging signal.
Step S408: a data line that sees through this storage arrangement charges time of a predetermined width to a storage unit of this storer and a sensing amplifier.
Step S410: finish.
Wherein, can be two/one-period of synchronizing signal during this data sensing method default, and the time of this predetermined width can be greater than zero second less than 0.5 nanosecond.
In sum, data sensing device of the present invention has designed a pre-charge circuit, its in one default during charging signals to the data line switch and sensing amplifier of output one Preset Time width charge.By this, can avoid data read errors that signal accumulation causes and the problem of solution known techniques.
The above description of this invention is illustrative, and nonrestrictive, and those skilled in the art is understood, and can carry out many modifications, variation or equivalence to it within spirit that claim limits and scope, but they will fall within the scope of protection of the present invention all.
Claims (14)
1. a data sensing device operates according to one first synchronizing signal, it is characterized in that this data sensing device comprises:
A plurality of storage unit;
A plurality of data lines are coupled to those storage unit respectively, in order to control reading or writing of those storage unit;
A plurality of bit lines are coupled to those storage unit respectively, are stored in data of those storage unit in order to output;
A plurality of sensing amplifiers are coupled to those bit lines respectively, in order to amplify these data that those storage unit are exported; And
At least one pre-charge circuit, in order to set according to this first synchronizing signal one default during, and during this is default, produce a precharging signal, see through this data line this storage unit and this sensing amplifier charged.
2. the data sensing device of putting down in writing as claim 1 is characterized in that, this pre-charge circuit saw through this data line this storage unit and this sensing amplifier are charged time of a predetermined width when per two/one-period of this first synchronizing signal.
3. the data sensing device of putting down in writing as claim 2 is characterized in that, the time of this precharging signal predetermined width greater than zero second less than 0.5 nanosecond.
4. as claim 1 or 2 data sensing device of being put down in writing, it is characterized in that this pre-charge circuit comprises:
One synchronous controller according to a read-write and one first synchronizing signal, produces one second synchronizing signal;
One delay circuit is in order to postpone this first synchronizing signal, to produce the 3rd synchronizing signal that postpones; And
One precharge pulse generator in order to according to this second synchronizing signal and the 3rd synchronizing signal, produces this precharging signal.
5. the data sensing device of putting down in writing as claim 2 is characterized in that, when this read-write was logical zero, this data sensing device was carried out the action of reading of data; When these read-write news were logical one, this data sensing device write the action of data.
6. the data sensing device of putting down in writing as claim 4 is characterized in that, this first synchronizing signal and this second synchronizing signal be inversion signal each other.
7. the data sensing device of putting down in writing as claim 4 is characterized in that, this first synchronizing signal and the 3rd synchronizing signal have a phase differential.
8. the data sensing device of putting down in writing as claim 7 is characterized in that, the predetermined width of this precharging signal equals this phase differential in fact.
9. the data sensing device of putting down in writing as claim 1 is characterized in that, is a storage arrangement.
10. a pre-charge circuit provides precharge in order to the objective circuit that produces cumulative errors at the signal transmission, it is characterized in that this pre-charge circuit includes:
One synchronous controller according to a read-write and one first synchronizing signal, produces one second synchronizing signal, and wherein the running of this first synchronizing signal and this objective circuit is synchronous;
One delay circuit is in order to postpone this first synchronizing signal, to produce the 3rd synchronizing signal that postpones; And
One precharge pulse generator in order to according to this second synchronizing signal and the 3rd synchronizing signal, produces this precharging signal;
Wherein, this pre-charge circuit according to this first synchronizing signal set one default during, and during this is default, produce this precharging signal, to this objective circuit charging.
11. the pre-charge circuit as claim 10 is put down in writing is characterized in that, the time of this predetermined width equals the difference of this second synchronizing signal and the 3rd synchronizing signal in fact.
12. a data sensing method is applicable to storage arrangement, it is characterized in that, this method includes:
Receive a synchronous signal;
According to this synchronizing signal set one default during, and during this is default, produce a precharging signal; And
A data line that sees through this storage arrangement charges time of a predetermined width to a storage unit of this storer and a sensing amplifier.
13. the data sensing method as claim 1 is put down in writing is characterized in that, is two/one-period of this synchronizing signal during this is default.
14. the data sensing method as claim 12 is put down in writing is characterized in that, the time of this predetermined width greater than zero second less than 0.5 nanosecond.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910252154A CN101719378B (en) | 2009-12-07 | 2009-12-07 | Data sensing device and data sensing method |
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| CN200910252154A CN101719378B (en) | 2009-12-07 | 2009-12-07 | Data sensing device and data sensing method |
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| CN101719378A true CN101719378A (en) | 2010-06-02 |
| CN101719378B CN101719378B (en) | 2012-10-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971718A (en) * | 2014-05-12 | 2014-08-06 | 北京兆易创新科技股份有限公司 | Pre-charge system and pre-charge judging method for bit line in memorizer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6798712B2 (en) * | 2002-07-02 | 2004-09-28 | Advanced Micro Devices, Inc. | Wordline latching in semiconductor memories |
| US7359265B2 (en) * | 2006-01-04 | 2008-04-15 | Etron Technology, Inc. | Data flow scheme for low power DRAM |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971718A (en) * | 2014-05-12 | 2014-08-06 | 北京兆易创新科技股份有限公司 | Pre-charge system and pre-charge judging method for bit line in memorizer |
| CN103971718B (en) * | 2014-05-12 | 2017-05-31 | 北京兆易创新科技股份有限公司 | A kind of pre-charge system of memory neutrality line and the determination methods of precharge |
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| CN101719378B (en) | 2012-10-03 |
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