CN101719378A - Data sensing device and method - Google Patents

Abstract

The invention provides a data sensing device and a data sensing method. The data sensing device comprises a plurality of memory cells, a plurality of data lines, a plurality of sense amplifiers and at least one pre-charge circuit. The memory units are used for storing data. The data lines are respectively coupled to the memory cells and used for controlling reading or writing of the memory cells. The bit lines are respectively coupled to the memory cells for outputting the data stored in the memory cells. The sense amplifiers are respectively coupled to the bit lines for amplifying the data outputted from the memory cells. The pre-charge circuit is used for setting a preset period according to the first synchronous signal, generating a pre-charge signal in the preset period and charging the memory cell and the sensing amplifier through the data line.

Description

Data sensing device and method

technical field

The present invention relates to a data sensing device, in particular to a pre-chargeable data sensing device.

Background technique

With the advancement of semiconductor manufacturing process, the area and operating voltage of transistors are getting smaller and smaller, which makes the current electronic circuits more and more high-speed and the chip area is also getting smaller and smaller.

However, in a memory circuit, such as a DRAM (Dynamic Random Access Memory, DRAM), many data lines (Data Line) and bit lines (Bit line) are included.

When the capacity of the memory gradually increases, the data lines and the bit lines will become longer, and there will be a signal accumulation phenomenon in the data lines and the bit lines. As shown in Figure 1A, if the logic value of the data line signal is not always fixed, such as the logic 0, 1, 0, 1 shown in the figure, the phenomenon of signal accumulation is not obvious or does not exist at this time, and the circuit can correctly sense The data of logic 0, 1, 0, 1; but as shown in Figure 1B, when these data lines receive the signal of the same logic value for a long time, the 0, 0, 0, 1 shown in the figure continuously receive three logic When the value is 0, the phenomenon of signal accumulation often becomes quite serious. Coupled with the fast operation speed of the memory system and the small range of operating voltage, it is easy to cause the situation that the logic value cannot be converted correctly when the logic value is converted, such as sensing The data becomes logic 0, 0, 0, 0. In this way, errors in writing and reading memory data will occur.

Contents of the invention

One of the objectives of the present invention is to provide a data sensing device that can provide short-time pre-charging.

One of the objectives of the present invention is to provide a data sensing device that can solve the problem of data reading errors caused by signal accumulation.

An embodiment of the present invention provides a data sensing device that operates according to a first synchronization signal. The data sensing device includes a plurality of storage units, a plurality of data lines, a plurality of sense amplifiers, and at least one pre-charging circuit. The storage units are used for storing data. The data lines are respectively coupled to the storage units and are used to control reading or writing of the storage units. The bit lines are respectively coupled to the memory cells for outputting data stored in the memory cells. The sense amplifiers are respectively coupled to the bit lines for amplifying the data output by the memory cells. The pre-charge circuit is used to set a preset period according to the first synchronous signal, and generate a pre-charge signal during the preset period to charge the storage unit and the sense amplifier through the data line.

An embodiment of the present invention provides a pre-charging circuit for providing pre-charging for a target circuit that generates cumulative errors in signal transmission, the pre-charging circuit includes a synchronous controller, a delay circuit, and a pre-charging pulse generator . The synchronous controller generates a second synchronous signal according to a read-write signal and a first synchronous signal, wherein the first synchronous signal is synchronous with the operation of the target circuit. The delay circuit is used for delaying the first synchronous signal to generate a delayed third synchronous signal. The precharge pulse generator is used to generate the precharge signal according to the second synchronous signal and the third synchronous signal;

Wherein, the pre-charging circuit sets a preset period according to the first synchronization signal, and generates a pre-charging signal during the preset period to charge the target circuit.

An embodiment of the present invention provides a data sensing method suitable for a memory device. The method includes the following steps: first, receiving a synchronization signal. Then, a preset period is set according to the synchronization signal, and a pre-charge signal is generated during the preset period. Afterwards, a memory cell and a sense amplifier of the memory are charged for a preset width time through a data line of the memory device.

The technology of the present invention utilizes the pre-charging technology to charge the target circuit for a preset width of time in a preset period, so as to solve the problem of data reading errors caused by the accumulation of various circuit signals.

Description of drawings

FIG. 1A shows a signal waveform diagram under normal conditions in the conventional technology.

FIG. 1B shows a waveform diagram of the signal accumulation phenomenon in the prior art.

FIG. 2A shows a schematic diagram of a data sensing device according to an embodiment of the present invention.

FIG. 2B shows the signal waveform diagram of FIG. 2A.

FIG. 3A shows a schematic diagram of a pre-charging circuit according to an embodiment of the present invention.

FIG. 3B shows the signal waveform diagram of FIG. 3A.

FIG. 4 shows a flowchart of a data sensing method according to an embodiment of the invention.

Explanation of reference signs:

200-data sensing device; 200a-memory array circuit; 200b-control circuit; 201-data line; 202-bit line; 203-sense amplifier; 204-memory unit; 205-data line switch; 200c-precharge Control circuit; 200c1-synchronous controller; 200c2-delay circuit; 200c3-precharge pulse generator.

Detailed ways

Please refer to FIG. 2A and FIG. 2B at the same time. FIG. 2A shows a schematic diagram of a part of the circuit of the data sensing device according to an embodiment of the present invention; FIG. 2B shows a signal waveform diagram of the data sensing device in FIG. 2A .

As shown in FIG. 2A , the data sensing device 200 includes a memory array circuit 200a, a control circuit 200b, and at least one pre-charging circuit 200c.

The memory array circuit 200a includes a plurality of data lines (Data lines) 201, a plurality of bit lines (Bit lines) 202, a plurality of sense amplifiers (Sense Amplifier) 203, a plurality of memory cells (memorycell) 204, a plurality of The coupling relation of the data line switch 205 is shown in the figure. The data line 201 reads the data of the storage unit 204 through the data line switch 205, or writes data to the storage unit 204; the sense amplifier 203 is coupled to the bit line 202, and is used to amplify the output of the bit line 202 data signal.

The control circuit 200b is used to control the memory array circuit 200a to perform operations, read and write, and so on.

The pre-charge control circuit 200c is coupled to the memory array 200a, and is used to output a pre-charge signal (Nimble pre-charge signal) P to pre-charge the memory array 200a. Wherein, the precharge signal P can be a pulse signal (Pulse).

The operation principle of the data sensing device 200 of the present invention will be described in detail below.

The data sensing device 200 according to the embodiment of the present invention is designed with a pre-charging circuit 200c for pre-charging the memory array 200a. Please refer to FIG. 2B for the charging method. In this embodiment, the pre-charging signal P output by the pre-charging circuit 200c will charge the data line signal for a width of a preset time t within a preset period Du (duration). In one embodiment, as shown in FIG. 2B , the pre-charging circuit 200c performs a preset time t (such as time T1 ~ T1') less than 0.5 The width of the nanosecond (n)s pre-charges the data line switch 205 and the sense amplifier 203 through the data line 201, so that the voltage level of the data line signal DLQ can be restored to a predetermined voltage every half clock cycle , reducing the problem of signal accumulation occurring. In this way, it is possible to avoid a time delay when the logic value of the data line signal is converted, and to prevent errors in reading or writing data by the sense amplifier.

It should be noted that, in one embodiment, the preset period Du set by the pre-charging circuit 200c and the time width t of the pre-charging signal P can be arbitrarily designed according to the requirements of the circuit designer or the characteristics of the memory. For example, the pre-charging circuit 200c pre-charges the data line switch 205 and the sense amplifier 203 through the data line during every cycle of the synchronization signal S1, or through the data line pair during every 1.5 cycles of the synchronization signal S1. The data line switch 205 and the sense amplifier 203 are pre-charged once . . . etc. In one embodiment, the pre-charging circuit 200c only needs to perform pre-charging before the signal accumulation exceeds a tolerable range.

Please note that in one embodiment of the present invention, the pre-charging circuit 200b pre-charges the data line switch and the sense amplifier through the data line; Circuits that cause data reading errors due to cumulative phenomena can be used. Of course, the technology of the present invention is applicable to various circuits other than memory circuits, such as processors, various chips, application chips, etc., as long as there is a problem of signal accumulation, and they all fall into the scope of the present invention. In the scope of patent application.

Please refer to FIG. A and FIG. 3B at the same time. FIG. 3A shows a schematic diagram of a pre-charging circuit according to an embodiment of the present invention; FIG. 3B shows a signal waveform diagram of FIG. 3A .

The pre-charge circuit 200c includes a synchronous controller 200c1, a delay circuit 200c2, and a pre-charge pulse generator 200c3. It works like this:

The synchronization controller 200c1 generates a second synchronization signal S2 according to a read/write signal R/W and a first synchronization signal S1. In one embodiment, the synchronization controller 200c1 outputs the second synchronization signal S2 which is opposite to the first synchronization signal S1 when the read/write signal R/W is logic 0.

The delay circuit 200c2 delays the first synchronization signal S1 for a predetermined time to generate a third synchronization signal S3.

Next, the precharge pulse generator 206c generates the precharge signal P with a width t according to the second synchronous signal S2 and the third synchronous signal S3. It should be noted that the first synchronous signal S1 and the third synchronous signal S3 are signals with the same phase, but there is a phase difference, and the phase difference substantially differs by a time width t.

The data sensing device 200 of an embodiment of the present invention is a dynamic random access memory device (Dynamic Random Access Memory, DRAM), wherein, when the read/write signal R/W is logic 0, the data sensing device 200 performs a read The action of fetching data; when the read/write signal R/W is logic 1, the data sensing device 200 performs the action of writing data.

FIG. 4 shows a data sensing method according to an embodiment of the present invention, which is applicable to a memory device. The method includes the following steps:

Step S402: start.

Step S404: Receive a synchronization signal.

Step S406: Set a preset period according to the synchronization signal, and generate a pre-charge signal during the preset period.

Step S408 : charging a memory cell and a sense amplifier of the memory for a preset duration through a data line of the memory device.

Step S410: end.

Wherein, the preset period of the data sensing method may be one-half cycle of the synchronization signal, and the preset width may be greater than zero seconds and less than 0.5 nanoseconds.

To sum up, the data sensing device of the present invention designs a pre-charging circuit, which outputs a charging signal with a preset time width to the data line switch and the sense amplifier for charging during a preset period. In this way, data reading errors caused by signal accumulation can be avoided, and problems in the prior art can be solved.

The above description of the present invention is illustrative rather than restrictive. Those skilled in the art understand that many modifications, changes or equivalents can be made to it within the spirit and scope of the claims, but they will all fall into within the protection scope of the present invention.

Claims (14)

1. A data sensing device operating according to a first synchronous signal, characterized in that the data sensing device comprises: Multiple storage units; A plurality of data lines are respectively coupled to the storage units for controlling reading or writing of the storage units; A plurality of bit lines are respectively coupled to the memory units for outputting a data stored in the memory units; a plurality of sense amplifiers, respectively coupled to the bit lines, for amplifying the data output by the memory cells; and At least one pre-charging circuit is used to set a preset period according to the first synchronous signal, and generate a pre-charging signal during the preset period to charge the storage unit and the sense amplifier through the data line. 2. The data sensing device as claimed in claim 1, wherein the pre-charging circuit senses the memory unit and the sensing unit through the data line at every half cycle of the first synchronous signal. The amplifier is charged for a preset width of time. 3. The data sensing device as claimed in claim 2, wherein the time of the preset width of the pre-charging signal is greater than zero seconds and less than 0.5 nanoseconds. 4. The data sensing device as claimed in claim 1 or 2, wherein the pre-charging circuit comprises: A synchronous controller, generating a second synchronous signal according to a read-write signal and a first synchronous signal; a delay circuit for delaying the first synchronization signal to generate a delayed third synchronization signal; and A precharge pulse generator is used for generating the precharge signal according to the second synchronous signal and the third synchronous signal. 5. The data sensing device as claimed in claim 2, wherein when the read/write signal is logic 0, the data sensing device performs the action of reading data; when the read/write signal is logic 1, The data sensing device performs an action of writing data. 6. The data sensing device as claimed in claim 4, wherein the first synchronous signal and the second synchronous signal are mutually inverse signals. 7. The data sensing device as claimed in claim 4, wherein the first synchronization signal and the third synchronization signal have a phase difference. 8. The data sensing device as claimed in claim 7, wherein the preset width of the precharge signal is substantially equal to the phase difference. 9. The data sensing device as claimed in claim 1, which is a memory device. 10. A pre-charging circuit for providing pre-charging to a target circuit that generates cumulative errors in signal transmission, characterized in that the pre-charging circuit includes: A synchronous controller generates a second synchronous signal according to a read-write signal and a first synchronous signal, wherein the first synchronous signal is synchronous with the operation of the target circuit; a delay circuit for delaying the first synchronization signal to generate a delayed third synchronization signal; and a pre-charge pulse generator, used for generating the pre-charge signal according to the second synchronous signal and the third synchronous signal; Wherein, the pre-charging circuit sets a preset period according to the first synchronization signal, and generates the pre-charging signal during the preset period to charge the target circuit. 11. The pre-charging circuit as claimed in claim 10, wherein the predetermined width is substantially equal to the difference between the second synchronous signal and the third synchronous signal. 12. A data sensing method suitable for a memory device, characterized in that the method comprises: receiving a synchronization signal; setting a preset period according to the synchronization signal, and generating a precharge signal during the preset period; and A storage cell and a sense amplifier of the memory are charged for a preset width time through a data line of the memory device. 13. The data sensing method according to claim 1, wherein the preset period is one-half period of the synchronization signal. 14. The data sensing method as claimed in claim 12, wherein the preset width is greater than zero seconds and less than 0.5 nanoseconds.

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