CN101719068A - counting loop-oriented C-to-VHDL mapping method and device - Google Patents
counting loop-oriented C-to-VHDL mapping method and device Download PDFInfo
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Abstract
The invention provides a counting loop-oriented C-to-VHDL mapping method and device. The device consists of a counter generating loop key variables, a comparer deciding whether to carry out arithmetic in a loop body or not according to a comparing arithmetic result, a selector acquiring data values outside the loop body or feedback values of the operation result in the loop body according to select switch values and an arithmetic unit for executing arithmetic operation in the loop body. A counting quasi-loop program realized by C language is automatically converted into a VHDL program which can be realized on Xilinx-series FPGA. Based on a sequential circuit and through separating loop control signals and enable output signals, the method carries out loop control in advance to decompose the counting quasi loop in C language into a loop basic module with higher clock frequency. Various forms of C language loop can be realized through combining a plurality of high-frequency loop basic modules.
Description
Technical field
What the present invention relates to is a kind of method that higher level lanquage is converted to hardware circuit.Specifically a kind of towards counting class round-robin C-to-VHDL comprehensive optimization method, be about to loop program that the C language realizes convert to automatically can be comprehensive the VHDL program, finally be transplanted to the method for moving on the Xilinx Series FPGA.The invention still further relates to the device that is applicable to this method.
Background technology
Convert higher level lanquage to hardware circuit and mainly adopt two kinds of methods: a kind of is starting class C language early, promptly design a kind of new software/hardware descriptive language or programming model, with it is net meter file comprehensively, re-uses special hardware synthesis instrument and realizes placement-and-routing; Another method is that directly (Matlab) program synthesis becomes the VHDL hardware description language for C, C++, re-uses existing commercial tool the VHDL file is carried out comprehensively, connects up with higher level lanquage.
Because class C language is a kind of language that can realize simultaneously that software/hardware is described, yet, there are the different of essence in software design idea with hardware design thought, software configuration (von Neumann structure) is a kind of Time Calculation model (time computing model), and its essence is the serialization of program; And hardware configuration is a kind of SPATIAL CALCULATION model (spatial computing model), and its essence is the parallelization of program.So, the class C language that on the such software language basis of C, designs, on the performance of hardware description, all exist the defective that can't overcome, its implementation effect can not compare favourably with the such hardware description language of Verilog or VHDL, some implementation effects are class C language preferably, ANSI C having been expanded in fact revises changed beyond recognitionly, the program development personnel Equivalent is in learning a kind of new software/hardware descriptive language again, therefore, began in recent years to pay close attention to directly higher level lanquage comprehensively was the method for VHDL hardware description language.
At present, realize that the C language is a lot of to the instrument of VHDL language conversion, as SPARK, ROCCC, DWARV etc.SPARK
[1]With ANSI-C as input, the register transfer level VHDL program that generation can be comprehensive.SPARK is based on SPARK intermediate representation (IR) exploitation, and the VHDL program of generation adopts the control forms of FSM (finite automaton).Though SPARK passes through systolic arrays
[2]Realized the counting class is circulated and the support of non-counting class round-robin, but do not supported break, continue and goto control structure in the loop body
[3]ROCCC
[4]With higher level lanquage such as C, C++ is as input, and it generates the VHDL program also is to control by FSM.ROCCC adopts SUIF and Machine-SUIF as the mapping front end, and the algorithm that is fit to the computing intensity quickens, and can be used as the hardware identification code accelerator.ROCCC only supports the counting class circulation of canonical form, as for (i=0; I＜b; I++); Support requirement to loop nesting is very strict, can not support the loop nesting of arbitrary form; The uncertain non-counting class of initial value, final value and step value of not supporting to circulate circulates, and this causes the treatable cyclical patterns of ROCCC limited.Simultaneously, ROCCC also has requirement for the statement in the loop body, as not having data dependence etc. between statement in the loop body.DWARV
[5](Delf workbenchAutomated reconfigurable VHDL generator): DWARV adopts the control forms of FSM, utilizes data flow diagram to realize the conversion of for round-robin
[6]DWARV only supports to count the class circulation, does not support non-counting class circulation, and simultaneously, DWARV does not support redirect in cycle control.
Open report related to the present invention has:
[1]R.K.Gupta，A.Nicolau，S.Gupta?and?N.D.Dutt，“SPARK：A?high-levelsynthesis?framework?for?applying?parallelizing?compilertransformations.”，Int.Conference?on?VLSI?Design?2003，January?2003
[2]Jae-Jin?Lee，Gi-Yong?Song.“High-Level?Synthesis?Using?SPARK?andSystolic?Array”，ARC?2006，LNCS?3985，pp.455-4602006
[3]UserManual?for?the?SPARK?Parallelizing?High-Level?Synthesis?FrameworkVersion1.1
[4]W.Najjar，B.A.Buyukkurt?and?Z.Guo，“Compiler?optimization?forconfigurable?accelerators”，Int.Workshop?On?applied?ReconfigurableComputing(ARC?2006)，Delft，The?Netherlands，2006
[5]Y.D.Yankova，G.K.Kuzmanov，K.L.M.Bertels，G.N.Gaydadjiev，J.Lu?andS.Vassiliadis，DWARV：Delft?Workbench?Automated?Recongurable?VHDLGenerator，In?Proceedings?of?the?17th?International?Conference?on?FieldProgrammable?Logic?and?Applications(FPL07)，Delft，TheNetherlands，2007
[6]Yana?Yankova，Georgi?Kuzmanov，Keon?Bertels，Georgi?Gaydadjiev，YiLu，Stamatis?Vassliiadis.“DWARV：DELFTWORKBENCH?AUTOMATEDRECONFIGURABLE?VHDL?GENERATOR”，Computer?Engineering?Laboratory，DelftUniversity?of?Technology。
Summary of the invention
The object of the present invention is to provide a kind of control signal by separating cycle and enable output signal, realize the circulation basic module of high frequency; Can realize the circulation of arbitrary form by making up these two groups of signals; Arbitrary node place at circulating path can add computing module, Extended Cyclic function a kind of towards counting class round-robin C-to-VHDL mapping method.The present invention also aims to provide method a kind of and of the present invention relevant mapping device.
The object of the present invention is achieved like this:
Of the present inventionly a kind ofly be towards counting class round-robin C-to-VHDL mapping method:
After analysis module redirect relation, find the loop head module; After entering the loop head module, seek the circulation key variables; After finding the circulation key variables, with circulation crucial advance to the loop head module from add operation by the loop body execution module, make the round-robin control operation and the arithmetic operation of loop body separate; Finally separate the round-robin control signal and enabled output signal.At cycle control signal and enable to finish the arithmetic operation in the circulation under the effect of output signal.
Of the present invention a kind of as follows towards counting class round-robin C-to-VHDL mapping method realization high frequency circulation basic module step:
S301: when Restart Signal is effective, enter cycle criterion first; Utilize comparer comparison loop key variables value and n value; Circulation is judged that if circulation effectively then enters and carries out corresponding computing in the loop body, arithmetical unit is started working according to comparator results;
S302: after Restart Signal lost efficacy, enter loop control variable, do not restart the judgment part from adding then to come back to from adding judgement; Otherwise utilize counter that the circulation key variables are carried out counting operation;
S303: after adding certainly or restarting, selector switch is selected the operation result of key variables and arithmetical unit; And then utilize comparer to compare selector switch to the selection result of key variables and the magnitude relationship of n value, bearing results according to comparer judges whether to satisfy the effective condition of circulation, satisfies entering circulation once more; Do not satisfy and then finish whole circulation;
S304: finish this cycling.
Of the present invention a kind of as follows towards the concrete treatment step of counting class round-robin C-to-VHDL mapping method realization round-robin:
(1) analysis module redirect relation finds LoopEntry;
(2) handle the PHI instruction, finish special processing the circulation key variables; By the instruction of the dyn_cast among the LLVM each operand in the PHI instruction is carried out the instruction type conversion; If operand can be converted to instruction, and the instruction type that converts to be addition or subtraction then this operand be key variables; Simultaneously the addition at this operand place or subtraction are advanceed in the module of PHI instruction place and carry out computing;
(3) judge key variables, produce the cycle control signal; According to the cycle control signal, enter or jump out the loop body operation; If enter loop body, then carry out the related operation operation in the loop body circularly, do not satisfy the effective condition of circulation up to the circulation key variables, produce the circulation invalid signals this moment, thereby jump out circulation, carries out the outer related operation operation of loop body;
(4) No_exit module converts; With the enable signal of this module No. of No_exit, represent during for high level to circulate and proceed as the loop body operational module; All arithmetic operations in the No_exit module are converted to basic operation corresponding in the VHDL language; The addition or the subtraction that are shifted to an earlier date in the step (2) operate in no longer computing in the No_exit module;
(5) Loop_exit module converts; This module No. of Loop_exit as the loop ends enable signal, is represented loop ends during for high level; All arithmetic operations in the Loop_exit module are converted to basic operation corresponding in the VHDL language.
Of the present invention a kind ofly can also handle by two groups of formed parallel constructions that circulate towards counting class round-robin C-to-VHDL mapping method.Concrete grammar is: if do not have intermediate operations between twice circulation, then the No_exit_0 module is just carried out simple redirect, directly enters new circulation; Otherwise, in the No_exit_0 module, do corresponding intermediate operations, and then jump to new circulation; The enable signal transfer mode is as follows between twice circulation:
After finishing first circulation basic module, instruct according to the br in the loop ends module, Loop_exit passes to the module that jumps to the loop ends enable signal: if do not have intermediate operations between twice circulation, then analysis module redirect relation finds next BLoopentry_1, gives BLoopentry_1 with the Loop_exit enable signal according to logical delivery; Otherwise, give the computing module enable signal with the Loop_exit enable signal according to logical delivery, analysis module redirect relation finds next BLoopentry_1 more at last, gives BLoopentry_1 with the computing module enable signal according to logical delivery.
Of the present invention a kind of towards all right cycle of treatment nested structure of counting class round-robin C-to-VHDL mapping method.Concrete grammar is: be embedded with circulation basic structure in the No_exit_0 module; If there are not other computings among the outer round-robin loop body No_exit_0, directly enter interior loop, then outer round-robin BLoopentry_0 enable signal is directly passed to the BLoopentry_1 of interior loop according to logic; Otherwise, give outer loop body module enable signal No_exit_0 with outer round-robin BLoopentry_0 enable signal according to logical delivery, give the BLoopentry_1 of interior loop with No_exit_0 according to logical delivery more at last, thereby finish the transmission of module enable signal between outer circulation and interior loop.
A kind of mapping device of the present invention towards counting class round-robin C-to-VHDL mapping method, by the counter that produces the circulation key variables, the comparer that whether decision carries out computing in the loop body according to the comparison operation result, obtain the selector switch of operation result value of feedback in outer data value of loop body or the loop body according to the selector switch value, carry out the arithmetical unit of the arithmetic operation in the loop body and form.
Counter, according in the circulation to the action type of key variables, for the circulation key variables carry out plus coujnt or subtraction counting.
Comparer, comparison loop key variables value and round-robin total degree when condition is carried out in satisfied circulation, enter loop body and carry out computing; Do not satisfy and circulate when carrying out condition, jump out circulation, finish loop computation.
Selector switch enters circulation time when first, select the circulation vitro data that initialization is carried out in data input in the loop body; Otherwise, select operation result value of feedback in the loop body, input data in the loop body are upgraded.
Arithmetical unit, enter loop body after, carry out corresponding computing according to various arithmetic operations in the loop body.
The invention provides a kind of towards counting class round-robin C-to-VHDL mapping method.Allow the core texture for circulation of software move on on the hardware and carry out, carry out efficient, reach hardware-accelerated realization round-robin purpose thereby accelerate it.The present invention by to the round-robin control signal with enable output signal and carry out clear and definite separating, realize the circulation basic module of high frequency; Simultaneously, by these two groups of signals are made up, can realize the circulation of arbitrary form.The present invention allows to add various computing modules neatly at any place of circulating path, and the circulation input is had no requirement, and supports the break and the continue control of loop body.These characteristics make the present invention be different from other and realize the round-robin design proposal.
The present invention also provides the mapping device that uses above-mentioned mapping method, is used for solving the problem that practical application uses said method of the present invention.
The C language has similar function to VHDL language, but bigger difference is also arranged.Though loop structure is arranged among the VHDL, the circulation that can only realize fixed number of times is that round-robin initial value, step-length, final value all are static datas.Circulating on the function of the circulation of fixed number of times and C language can't be mated, and therefore will realize circulating and the round-robin structure will be broken up, and adopts branch's judgement statement (IF) to finish the round-robin computing with timing Design.All the circulation key variables are judged when each clock arrives, thereby whether decision carries out the operation of loop body.The circulation key variables are finger-type such as for (i=0; I＜b; I++) variable i of expression circulation initial value, final value etc. in.The round-robin operating process is similar to counter, and the part of expansion is: the value according to counter generates corresponding enable signal, and its basic realization flow is seen mistake! Do not find Reference source.。A but mistake! Do not find Reference source.Shown in the flow process S202 " variable is from adding " of circulation key variables do not separated with " circulation effectively ", judge whether that at every turn the operation of carrying out loop body will directly be subjected to the interior operating influence of loop body.This implementation hierarchical structure is unintelligible, and control is complicated, can't realize the multiple combination of a plurality of round-robin flexibly.
The present invention by the key variables that circulate in advance from add operation, computing in cycle control and the loop body is separated, thereby has separated the round-robin control signal and enabled output signal, make cycle control succinct, its realization flow such as mistake! Do not find Reference source.Shown in.Restarting and be respectively the control signal that (initialization) and stepping are restarted in circulation from adding among S301 and the S302, it is the control signal of the corresponding execution module of control that the circulation among the S303 is effectively finished with circulation.Owing to will carry out the cascade of module, so all enable signals all are the high level of one-period.Enable signal transmits according to logic between module, thereby finishes the corresponding calculating of circulation.The essential characteristic of enable signal is: the high level that has only one-period.The enable signal that the high level of one-period refers to module is the one-period high level, if control is transferred to the next stage module from this module simultaneously, then this module is that corresponding next stage generates one-period high level enable signal.The high level of one-period guaranteed when loop body carry out to need a plurality of timeticks, the corresponding module of the loop body one-period that only is enabled.This characteristic is also effective to other corresponding module.
The circulation basic module of the present invention design has carried out clear and definite definition with various signals, and the independent assortment of circulation basic module has been played decisive role.Effective and adding certainly of self, join if will circulate, then realized a circulation that does not have loop body; Effectively join with a computing module if will circulate, computing module joins with adding certainly, has then realized a basic circulation.If signal is finished in the circulation of basic round-robin and another round-robin Restart Signal joins, realized that then 2 round-robin are arranged side by side; Join as if round-robin is circulated useful signal and another basic round-robin Restart Signal, signal is finished in basic round-robin circulation and round-robin joins from plus signal, has realized that then 2 round-robin are nested.According to realize circulation side by side and the principle of loop nesting by that analogy, just can realize the circulation of arbitrary form.
The invention has the advantages that cycle control is shifted to an earlier date, separated cycle control signal and data operation enable signal simultaneously, thereby make cycle control become succinctly, circulation basic module maximum clock frequency height.Simultaneously, after being more conducive to circulation is optimized, as circular flow aquation etc.
Description of drawings
Fig. 1 is the basic module principle figure of circulation; Fig. 2 is the conventional realization flow synoptic diagram of round-robin; Fig. 3 is a modularization treatment scheme synoptic diagram; Fig. 4 is an arithmetic element treatment scheme synoptic diagram; Fig. 5 is the basic modular structure figure of circulation; Fig. 6 is round-robin parallel construction figure; Fig. 7 is round-robin nested structure figure; Fig. 8 is a PHI treatment scheme synoptic diagram; Fig. 9 is single circulation (cycle index is a 3) oscillogram; Figure 10 is 2 circulations (cycle index all is 3) oscillograms in turn; Figure 11 is the nested oscillograms of 2 circulations (cycle index all is 3).
Embodiment
For example the present invention is done description in more detail below in conjunction with accompanying drawing:
The circulation basic module of 1 high frequency
1.1 circulation IR structure analysis
The present invention can utilize LLVM as front end for cyclic transformation in the C language to be become LLVM IR based on the LLVM framework, then for round-robin LLVM IR is carried out conversion process.LLVM IR is a kind of intermediate expression of machine-independent framework.
A round-robin BasicBlock (basic module) is mainly by LoopEntry (loop head module), Loop_exit (module is jumped out in circulation) and No_exit (circulation execution module) three parts are formed, wherein LoopEntry mainly finishes the selection of selection, public operation (circulation can shift to an earlier date part) and the tributary circuit of data, No_exit finishes the operation in the loop body, and Loop_exit finishes the operation after circulation is finished.The relation of these cyclic module interblocks such as a mistake! Do not find Reference source.Shown in.
A mistake! Do not find Reference source.In, instruct by PHI and to carry out data and select.PHI instructs expression: variable is selected corresponding value when the module enable signal is effective.As %indvar=phi i32[0, %LoopHeader], [%nextindvar, %Loop], this PHI instruction expression indvar variable is got ' 0 ' value when LoopHeader module enable signal is effective, and the value of when Loop module enable signal is effective, getting this variable of next indvar.
A mistake! Do not find Reference source.In, BLoopentry carries out branch's redirect by the br instruction, enters loop body or jumps out circulation according to the redirect result.Br instructs expression: according to the comparison order result, carry out branch and select, jump to corresponding module.As br bool%tmp_19, label%BNo_exit, label%Loop_exit, this br instruction expression BLoopentry carries out branch and selects according to the value of tmp_19, if tmp_19 is true, jumps to BNo_exit; Otherwise jump to Loop_exit.
1.2 the circulation key variables are handled
The present invention concerns by the redirect between analysis module and discerns circulation, finds BLoopentry, and key variables then circulate among the treatments B Loopentry.LLVM IR carries out data by the PHI instruction to the circulation key variables and selects, and its data are selected flow process such as mistake! Do not find Reference source.Shown in.
S801: identification key variables, initialization key variables i;
S802: key variables are carried out from add operation, upgrade key variables i value,
S803: when circulation continues, carry out the loop body arithmetic operation;
S804: this loop ends.
Key of the present invention is the special processing mode to the circulation key variables:
(1) identification circulation key variables
Find the loop head module by redirect relation: judge whether carry out the round-robin conditional-variable to intermodule, find corresponding comparison order by conditional-variable, operand by comparison order obtains key variables then, at last key variables is joined in the KeyVariable array.
(2) from the add operation instruction in advance with key variables
Read the PHI instruction, if this instruction is then read its operand in KeyVariable, will in the No_exit module key variables be advanceed to the LoopEntry module from the add operation instruction then, and will join in the KeyOperation array from the add operation instruction.
(3) ignore key variables from add operation
When the translation of instructing,, then directly skip if should instruct in the KeyOpeartion array.
After above-mentioned special processing to the PHI instruction, separate the round-robin control signal and enabled output signal, thus the circulation basic module maximum clock frequency height after the feasible conversion.Simultaneously, more help realizing various forms of for circulations, strengthened circulatory function.
1.3 the realization of circulation basic module
The present invention is the object basic Module Design that circulates with the circulation key variables mainly.Cycle control signal and computing signal are separated its treatment scheme such as mistake! Do not find Reference source.Shown in.
S301: when Restart Signal is effective, enter cycle criterion first.Utilize comparer comparison loop key variables value and n value in the device shown in Figure 1.Circulation is judged that if circulation effectively then enters and carries out corresponding computing in the loop body, the interior arithmetical unit of device this moment is started working according to comparator results, the arithmetical unit treatment scheme as shown in Figure 4;
S302: after Restart Signal lost efficacy, enter loop control variable, do not restart the judgment part from adding then to come back to from adding judgement; Otherwise the counter in the use device carries out counting operation to the circulation key variables.
S303: after adding certainly or restarting, the selector switch in the device is selected the operation result of key variables and arithmetical unit.And then utilize comparer to compare selector switch to the selection result of key variables and the magnitude relationship of n value, bearing results according to comparer judges whether to satisfy the effective condition of circulation, satisfies entering circulation once more; Do not satisfy and then finish whole circulation.
S304: finish this cycling.
Realize that the basic module converts treatment step of circulation is as follows.
(1) analysis module redirect relation finds LoopEntry.
(2) handle the PHI instruction, finish special processing the circulation key variables.By the instruction of the dyn_cast among the LLVM each operand in the PHI instruction is carried out the instruction type conversion.If operand can be converted to instruction, and the instruction type that converts to be addition or subtraction then this operand be key variables.Simultaneously the addition at this operand place or subtraction are advanceed in the module of PHI instruction place and carry out computing.
(3) judge key variables, produce the cycle control signal.According to the cycle control signal, enter or jump out the loop body operation.If enter loop body, then carry out the related operation operation in the loop body circularly, do not satisfy the effective condition of circulation up to the circulation key variables, produce the circulation invalid signals this moment, thereby jump out circulation, carries out the outer related operation operation of loop body.
(4) No_exit module converts.With the enable signal of this module No. of No_exit, represent during for high level to circulate and proceed as the loop body operational module.All arithmetic operations in the No_exit module are converted to basic operation corresponding in the VHDL language.The addition or the subtraction that are shifted to an earlier date in the step (2) operate in no longer computing in the No_exit module.
(5) Loop_exit module converts.This module No. of Loop_exit as the loop ends enable signal, is represented loop ends during for high level.All arithmetic operations in the Loop_exit module are converted to basic operation corresponding in the VHDL language.
A mistake! Do not find Reference source.Be the hardware unit figure of circulation fundamental block, form by counter, comparer, selector switch, arithmetical unit four parts.Counter is used for cycle of treatment key variables i; Comparer is among the BLoopentry, and foundation is selected by br instruction carrying out branch; Selector switch is used for the data of PHI instruction and selects; Arithmetical unit then is used to carry out the interior computing of loop body, and this tetrameric particular content is decided by the structure of the actual C code of changing.
The realization of 2 circulation combinations
The present invention's realize circulating principle of combination is that circulation basic module by a plurality of high frequencies makes up the circulation combination that realizes arbitrary form accordingly.
2.1 circulation side by side
A mistake! Do not find Reference source.Be two groups of formed parallel constructions that circulate.If do not have intermediate operations between twice circulation, then mistake! Do not find Reference source.In the No_exit_0 module just carry out simple redirect, directly enter new circulation; Otherwise, in the No_exit_0 module, do corresponding intermediate operations, and then jump to new circulation.Utilize the method that realizes the circulation basic module to realize two circulation basic modules in proper order, thereby realize that circulation side by side.The enable signal transfer mode is as follows between twice circulation:
After finishing first circulation basic module, instruct according to the br in the loop ends module, Loop_exit passes to the module that jumps to the loop ends enable signal: if do not have intermediate operations between twice circulation, then analysis module redirect relation finds next BLoopentry_1, gives BLoopentry_1 with the Loop_exit enable signal according to logical delivery; Otherwise, give the computing module enable signal with the Loop_exit enable signal according to logical delivery, analysis module redirect relation finds next BLoopentry_1 more at last, gives BLoopentry_1 with the computing module enable signal according to logical delivery.
2.2 loop nesting
A mistake! Do not find Reference source.Be nested structure, circulation basic structure shown in Figure 5 is arranged again in No_exit_0 module (loop body).The method that realizes each circulation basic module in the loop nesting structure is identical with the method that realizes single circulation basic module.The key that realizes the loop nesting structure is how the module enable signal transmits between the ectonexine circulation module.A mistake! Do not find Reference source.In, if there are not other computings among the outer round-robin loop body No_exit_0, directly entering interior loop, then outer round-robin BLoopentry_0 enable signal is directly passed to the BLoopentry_1 of interior loop according to logic; Otherwise, give outer loop body module enable signal No_exit_0 with outer round-robin BLoopentry_0 enable signal according to logical delivery, give the BLoopentry_1 of interior loop with No_exit_0 according to logical delivery more at last, thereby finish the transmission of module enable signal between outer circulation and interior loop.
3 circulations realize the result
Utilization is towards counting class round-robin C-to-VHDL mapping method and device, handles single circulation, circulation and nested loop side by side respectively.Utilize the emulation of Xilinx ISE instrument comprehensive the VHDL program that processing obtains, can obtain Fig. 9, Figure 10 and simulation result shown in Figure 11.
A mistake! Do not find Reference source.Be 1 round-robin oscillogram, cycle index is 3.As seen from the figure, the loop body execution time is 1 timeticks in this example, and promptly the phase differential of EN and No_exit is 1 cycle.In the application of reality, loop body is carried out a plurality of timeticks possibly, and then EN just becomes high level after corresponding beat counts up to.A mistake! Do not find Reference source.Be 2 oscillograms that circulation connects in turn, 2 round-robin cycle indexes all are 3.A mistake! Do not find Reference source.Be the oscillogram that 2 loop nestings connect, inside and outside round-robin cycle index all is 3.In mistake! Do not find Reference source.In, outer round-robin EN and No_exit differ 9 cycles.Because finish whole computings (circulation) afterwards in interior loop, the stepping of outer circulation ability once.
Claims (6)
1. one kind towards counting class round-robin C-to-VHDL mapping method, it is characterized in that: the key variables that circulate in advance from add operation, computing in cycle control and the loop body is separated, thereby has separated the round-robin control signal and enabled output signal; The method from add operation of key variables of circulating in advance is as follows:
After analysis module redirect relation, find the loop head module; After entering the loop head module, seek the circulation key variables; After finding the circulation key variables, with circulation crucial advance to the loop head module from add operation by the loop body execution module, make the round-robin control operation and the arithmetic operation of loop body separate; Finally separate the round-robin control signal and enabled output signal.
2. according to claim 1 a kind of towards counting class round-robin C-to-VHDL mapping method, it is characterized in that realizing that the concrete treatment step of round-robin is as follows:
(1) analysis module redirect relation finds LoopEntry;
(2) handle the PHI instruction, the key variables that circulate in advance from add operation; By the instruction of the dyn_cast among the LLVM each operand in the PHI instruction is carried out the instruction type conversion; If operand can be converted to instruction, and the instruction type that converts to be addition or subtraction then this operand be key variables; Simultaneously the addition at this operand place or subtraction are advanceed in the module of PHI instruction place by loop body execution module (No_exit) and carry out computing;
(3) judge key variables, produce the cycle control signal; According to the cycle control signal, enter or jump out the loop body operation; If enter loop body, then carry out the related operation operation in the loop body, do not satisfy the effective condition of circulation up to the circulation key variables, produce the circulation invalid signals this moment, thereby jump out circulation, carries out the outer related operation operation of loop body;
(4) No_exit module converts; With the enable signal of this module No. of No_exit, represent during for high level to circulate and proceed as the loop body operational module; All arithmetic operations in the No_exit module are converted to basic operation corresponding in the VHDL language; The addition or the subtraction that are shifted to an earlier date in the step (2) operate in no longer computing in the No_exit module;
(5) Loop_exit module converts; This module No. of Loop_exit as the loop ends enable signal, is represented loop ends during for high level; All arithmetic operations in the Loop_exit module are converted to basic operation corresponding in the VHDL language.
3. according to claim 2 a kind of towards counting class round-robin C-to-VHDL mapping method, the treatment step of the basic module that it is characterized in that realizing circulating is as follows:
S301: when Restart Signal is effective, enter cycle criterion first; Utilize comparer comparison loop key variables value and n value; Circulation is judged that if circulation effectively then enters and carries out corresponding computing in the loop body, arithmetical unit is started working according to comparator results;
S302: after Restart Signal lost efficacy, enter loop control variable, do not restart the judgment part from adding then to come back to from adding judgement; Otherwise utilize counter that the circulation key variables are carried out counting operation;
S303: after adding certainly or restarting, selector switch is selected the operation result of key variables and arithmetical unit; And then utilize comparer to compare selector switch to the selection result of key variables and the magnitude relationship of n value, bearing results according to comparer judges whether to satisfy the effective condition of circulation, satisfies entering circulation once more; Do not satisfy and then finish whole circulation;
S304: finish this cycling.
4. according to claim 2 a kind of towards counting class round-robin C-to-VHDL mapping method, it is characterized in that: can handle by two groups of formed loop structures arranged side by side that circulate; The method of handling loop structure arranged side by side is as follows: if do not have intermediate operations between twice circulation, then the No_exit_0 module is just carried out simple redirect, directly enters new circulation; Otherwise, in the No_exit_0 module, do corresponding intermediate operations, and then jump to new circulation; The enable signal transfer mode is as follows between twice circulation:
After finishing first circulation basic module, instruct according to the br in the loop ends module, Loop_exit passes to the module that jumps to the loop ends enable signal: if do not have intermediate operations between twice circulation, then analysis module redirect relation finds next BLoopentry_1, gives BLoopentry_1 with the Loop_exit enable signal according to logical delivery; Otherwise, give the computing module enable signal with the Loop_exit enable signal according to logical delivery, analysis module redirect relation finds next BLoopentry_1 more at last, gives BLoopentry_1 with the computing module enable signal according to logical delivery.
5. according to claim 2 a kind of towards counting class round-robin C-to-VHDL mapping method, it is characterized in that: can handle by two groups of formed nested loop structures that circulate; The method of handling nested loop structure is as follows:
If there are not other computings among the outer round-robin loop body No_exit_0, directly enter interior loop, then outer round-robin BLoopentry_0 enable signal is directly passed to the BLoopentry_1 of interior loop according to logic; Otherwise, give outer loop body module enable signal No_exit_0 with outer round-robin BLoopentry_0 enable signal according to logical delivery, give the BLoopentry_1 of interior loop with No_exit_0 according to logical delivery more at last, thereby finish the transmission of module enable signal between outer circulation and interior loop.
6. mapping device towards counting class round-robin C-to-VHDL mapping method, it is characterized in that: by the counter that produces the circulation key variables, the comparer that whether decision carries out computing in the loop body according to the comparison operation result, obtain the selector switch of operation result value of feedback in outer data value of loop body or the loop body according to the selector switch value, carry out the arithmetical unit of the arithmetic operation in the loop body and form.
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Cited By (3)
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| CN103345381A (en) * | 2013-06-18 | 2013-10-09 | 邱涌 | C TO HDL circulation mapping method based on feedback circuit |
| CN104199652A (en) * | 2014-08-26 | 2014-12-10 | 邱涌 | C TO HDL synchronous mapping method based on data flow |
| CN107832496A (en) * | 2017-10-16 | 2018-03-23 | 北京腾凌科技有限公司 | Method and system for emulation |
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| CN101366013A (en) * | 2005-04-22 | 2009-02-11 | 阿尔特雷克斯逻辑公司 | Array of data processing elements with variable precision interconnect |
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