CN101702637B - Time slot cross method and system - Google Patents
Time slot cross method and system Download PDFInfo
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- CN101702637B CN101702637B CN200910209621.XA CN200910209621A CN101702637B CN 101702637 B CN101702637 B CN 101702637B CN 200910209621 A CN200910209621 A CN 200910209621A CN 101702637 B CN101702637 B CN 101702637B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1652—Optical Transport Network [OTN]
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Abstract
The invention provides a time slot cross method which comprises: demapping and interweaving OTUk data frame to obtain ODUd data frame; carrying out high-capacity time slot cross on the obtained ODUd data frame after demapping and interweaving; de-interweaving the obtained ODUd data frame after high-capacity time slot cross to obtain OTUk data frame. The invention also provides a time slot cross system. The invention enhances cross capacity and reduces design difficulty of cross.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of time slot cross method and system.
Background technology
Exchange and be generally divided into 2 kinds: packet switch and circuit switching (being again intersection).Exchange chip and equipment are generally divided into 3 kinds: packet switch, time-slot cross, space division cross.Packet switch belongs to the 2nd, 3 layer (i.e. data link layer, network layer) of the definition of OSI 7 layer network, and time-slot cross, space division cross belong to the 1st layer (i.e. physical layer) of the definition of OSI 7 layer network.The cross granularity of time-slot cross is a time slot of pin, and namely cross granularity speed is about 1/4 ~ 1/16 or less of pin speed, and all pin speed of a chip are all the same; And the cross granularity of space division cross is exactly pin speed, all pin speed of a chip can be different, and support that mixing intersects.
The implementation method of existing time-slot cross system realizes mainly through the cascade of cross chips, and current jumbo cross chips has 160Gbit/s, 180Gbit/s, realizes the method construct that high capacity of switch capacity needs to adopt multi-disc cascade.
At least there is following problem in prior art: traditional time-slot cross system is realized the cross chips that adopts more and realized by the mode of cascade.Cross chips inside is all a square matrices, and the cross-capacity of chip is limited to semiconductor technology.Multiple cross chips is formed a larger cross matrix or intersection equipment, adopts the implementation method of multiple chip square matrices expansion capacity if simple, complexity with square speed increase.In addition, traditional cross chips also exists that power consumption is large, cost is high, design the shortcomings such as dumb.
Summary of the invention
The present invention aims to provide a kind of time slot cross method and system, with solve prior art exist complexity high, power consumption is large, cost is high, design inflexible problem.
According to an aspect of the present invention, provide a kind of time slot cross method, comprising: to OTU
kframe carries out demapping and intertexture, obtains ODU
dframe; By the ODU obtained after demapping and intertexture
dframe carries out Large Copacity time-slot cross; To the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe.
Wherein, ODU
cthe frame structure of Frame is 4 row, and often row 4080 arranges; ODU
dthe frame structure of Frame is 2 row, and often row 4080 arranges.
Preferably, to OTU
kframe carries out demapping and intertexture, obtains ODU
dframe comprises: from OTU
kseparate output time slot frame in Frame, after removing the byte of padding in time slot frame, obtain ODU
cframe; To ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe.
Preferably, to the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe comprises: to the ODU after Large Copacity time-slot cross
dframe carries out 2 than deinterleave, obtains ODU
cframe; By the ODU obtained after deinterleaving
cframe is converted to time slot frame, and the method adopting byte to interleave is assembled into OTU add byte of padding in time slot frame after
kframe.
Preferably, to ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe comprises: by 2 ODU
cframe is mapped to 4 ODU
dframe, comprising: by 2 ODU
ceach ODU of Frame
ceach byte in Frame is divided into 4 parts, every part of 2 bits; By 2 ODU
cfirst ODU in Frame
c7 to the position, position 6 of the odd column byte of Frame, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d7 to the position, position 6 of a byte of Frame, 7 to the position, position 6 of even column byte, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d5 to the position, position 4 of the byte of Frame; By 2 ODU
csecond ODU in Frame
c7 to the position, position 6 of the odd column byte of Frame, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d3 to the position, position 2 of the byte of Frame, 7 to the position, position 6 of even column byte, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d1 to the position, position 0 of the byte of Frame.
According to another aspect of the present invention, additionally provide a kind of time-slot cross system, comprising: demapping interleaving block, for OTU
kframe carries out demapping and intertexture, obtains ODU
dframe; Repeat in work module, for the ODU will obtained after demapping and intertexture
dframe carries out Large Copacity time-slot cross; Deinterleaving mapping block, for the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe.
Preferably, demapping interleaving block comprises: de-mapping unit, for from OTU
kseparate output time slot frame in Frame, after removing the byte of padding in time slot frame, obtain ODU
cframe; Interleave unit, for ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe;
Wherein, interleave unit is also for by 2 ODU
cframe is mapped to 4 ODU
dframe.
Preferably, deinterleaving mapping block comprises: deinterleaving unit, for the ODU after Large Copacity time-slot cross
dframe carries out 2 than deinterleave, obtains ODU
cframe; Map unit, for the ODU will obtained after deinterleaving
cframe is converted to time slot frame, and the method adopting byte to interleave is assembled into OTU add byte of padding in time slot frame after
kframe.
Preferably, in above-mentioned device, also comprise: spending process module, for monitoring and maintenance management de-mapping unit, map unit and repeat in work module.
Preferably, de-mapping unit, interleave unit, repeat in work module, deinterleaving unit, map unit, spending process module are realized by field programmable gate array chip.
Due to the method by adopting Bit Interleave before entering cross matrix in data, the data of intersecting are carried out bitslicing by time slot, so be equivalent to one-level intersection many, solve prior art exist complexity high, power consumption is large, cost is high, design inflexible problem, thus improve the capacity of intersection on the one hand, reduce the difficulty of intersection on the other hand.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 shows the schematic diagram of the time-slot cross system according to the embodiment of the present invention;
Fig. 2 shows the flow chart of the time slot cross method according to the embodiment of the present invention;
Fig. 3 shows the overall plan block diagram of time-slot cross system according to the preferred embodiment of the invention;
Fig. 4 shows the flow chart of time slot cross method according to the preferred embodiment of the invention;
Fig. 5 shows the flow chart of 2 Bit Interleaves according to the preferred embodiment of the invention.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Fig. 1 shows the schematic diagram of the time-slot cross system according to the embodiment of the present invention, comprising: demapping interleaving block 10, for OTU
k(Optical Channel Transport Unit, optical channel delivery unit) Frame carries out demapping and intertexture, obtains ODU
d(OpticalChannel Data Unit, optical channel data cell) Frame; Repeat in work module 20, for the ODU will obtained after demapping and intertexture
dframe carries out Large Copacity time-slot cross; Deinterleaving mapping block 30, for the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe.
This embodiment is due to the method by adopting Bit Interleave before entering cross matrix in data, the data of intersecting are carried out bitslicing by time slot, so be equivalent to one-level intersection many, solved that the complexity that prior art exists is high, power consumption is large, cost is high, design inflexible problem.Use this embodiment can improve the capacity of intersection on the one hand, the difficulty of intersection can be reduced on the other hand.
As shown in Figure 3, demapping interleaving block 10 comprises: de-mapping unit 101, for from OTU
kseparate output time slot frame in Frame, after removing the byte of padding in time slot frame, obtain ODU
cframe; Interleave unit 102, for ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe.
Deinterleaving mapping block 30 comprises: deinterleaving unit 301, for the ODU after Large Copacity time-slot cross
dframe carries out 2 than deinterleave, obtains ODU
cframe; Map unit 302, for the ODU will obtained after deinterleaving
cframe is converted to time slot frame, and the method adopting byte to interleave is assembled into OTU add byte of padding in time slot frame after
kframe.
Wherein, ODU
cthe frame structure of Frame is 4 row, and often row 4080 arranges; ODU
dthe frame structure of Frame is 2 row, and often row 4080 arranges.
Interleave unit 102 is also for by 2 ODU
cframe is mapped to 4 ODU
dframe.Its concrete interweaving realization method is as shown in table 1 to table 6, Fig. 5, and in like manner the deinterleaving process of known deinterleaving unit 301 is the inverse process of this interleaving process.
Above preferred embodiment provides the specific embodiments that demapping interleaving block 10 conciliates interlace map module 30.
Preferably, in above-mentioned system, also comprise: spending process module 40, for monitoring and maintenance management de-mapping unit 101, map unit 302 and repeat in work module 20.
Preferably, de-mapping unit 101, interleave unit 102, repeat in work module 20, deinterleaving unit 301, map unit 302, spending process module 40 can be passed through field programmable gate array chip (i.e. fpga chip) and realize.Wherein, above-mentioned module and unit are placed on wiring board 50.
This embodiment is by FPGA (Field-Programmable Gate Array, field programmable gate array) internal algorithm design realization, adopt Bit Interleave technology, achieve the Large Copacity time-slot cross system based on 2 bits, thus can system resource be reduced, reduce costs and design difficulty, flexibility is strong simultaneously, can cost be saved, shorten Time To Market.
Fig. 2 shows the flow chart of the time slot cross method according to the embodiment of the present invention, comprises the following steps:
Step S10, to OTU
kframe carries out demapping and intertexture, obtains ODU
dframe;
Step S20, by the ODU obtained after demapping and intertexture
dframe carries out Large Copacity time-slot cross;
Step S30, to the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe.
Wherein, ODU
cthe frame structure of Frame is 4 row, and often row 4080 arranges; ODU
dthe frame structure of Frame is 2 row, and often row 4080 arranges.
This embodiment is due to the method by adopting Bit Interleave before entering cross matrix in data, the data of intersecting are carried out bitslicing by time slot, so be equivalent to one-level intersection many, solved that the complexity that prior art exists is high, power consumption is large, cost is high, design inflexible problem.Use this embodiment can improve the capacity of intersection on the one hand, the difficulty of intersection can be reduced on the other hand.
Preferably, step S10 comprises: from OTU
kseparate output time slot frame in Frame, after removing the byte of padding in time slot frame, obtain ODU
cframe; To ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe.
Step S30 comprises: to the ODU after Large Copacity time-slot cross
dframe carries out 2 than deinterleave, obtains ODU
cframe; By the ODU obtained after deinterleaving
cframe is converted to time slot frame, and the method adopting byte to interleave is assembled into OTU add byte of padding in time slot frame after
kframe.
Wherein, to ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe comprises: by 2 ODU
cframe is mapped to 4 ODU
dframe.By 2 ODU
cframe is mapped to 4 ODU
dframe comprises: by 2 ODU
ceach ODU of Frame
ceach byte in Frame is divided into 4 parts, every part of 2 bits; By 2 ODU
cfirst ODU in Frame
c7 to the position, position 6 of the odd column byte of Frame, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d7 to the position, position 6 of a byte of Frame, 7 to the position, position 6 of even column byte, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d5 to the position, position 4 of the byte of Frame; By 2 ODU
csecond ODU in Frame
c7 to the position, position 6 of the odd column byte of Frame, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d3 to the position, position 2 of a byte of Frame, 7 to the position, position 6 of even column byte, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into 4 ODU respectively
d1 to the position, position 0 of the byte of Frame.
Above preferred embodiment provides the specific embodiments of above-mentioned steps S10 and step S30.Wherein, to concrete ODU
cthe interweaving realization method of Frame is as shown in table 1 to table 6, Fig. 5, and in like manner known deinterleaving process is the inverse process of this interleaving process.
The present invention mainly to realize between multi-service plate by cross board at ODU
kinterconnecting on (k=0,1,2).Realizing particle is ODU
k(Optical Channel Data Unit, optical channel data cell, k is that subscript represents speed grade) high capacity of switch technical difficulty larger, the words that the capacity of intersection is larger, the scale of intersecting is larger, so just needs to take more logical resource.Multiple FPGA chip can be adopted to realize high capacity of switch.
As shown in Figure 3, the main functional module of time-slot cross system that proposes of the present invention and unit comprise: map unit 302, interleave unit 102, repeat in work module 20, deinterleaving unit 301, spending process module 40, de-mapping unit 101.ODU
cframe is the frame of a kind of similar OTN (Optical Transport Network, optical transfer network).
1, map unit: be responsible for ODU
cbe converted to time slot frame, and adopt byte interleaving mode that time slot frame is assembled into OTU
k(Optical Channel Transport Unit, optical channel delivery unit) frame.
2, interleave unit: completion logic realizes the function that 2bit-slice interweaves, by ODU
cframe obtains ODU after 2 Bit Interleaves
dframe.
3, repeat in work module: realize cross matrix, namely based on ODU
dthe high capacity of switch scheduling of frame.
4, deinterleaving unit: completion logic realizes the function of 2bit-slice deinterleaving, its process is the inverse process of the interleaving process of above-mentioned interleave unit.
5, spending process module: realize the functions such as framing, frame alignment, scrambler, error detection.
6, de-mapping unit: from OTU
kin solve ODU
ctime slot frame, weeds out ODU
cbyte of padding in time slot frame.
What the present invention proposed designs by FPGA the high capacity of switch system realized based on Bit Interleave, overcome the defect that the traditional design design cycle is long, dumb, power consumption is large, cost is high, propose a kind of new implementation method, simplify design, reduce design difficulty, shorten time to market (TTM).
First, the ration of division, number of time slots, backboard speed, intersecting grain, cross-capacity should be specified when systems organization.
1. determine the ration of division: the intertexture (least unit namely interweaved is 2bit) of 2 bits, the ration of division is 4, by byte 4 decile;
2. number of time slots is determined: the number of time slots=backplane interface speed * ration of division/(ODU
kspeed);
3. backboard speed: can determine according to the serdes of cross chips (serioparallel exchange interface) speed;
4. intersecting grain: can be ODU0/1/2 and STM-16, STM-64 etc.;
5. cross-capacity: the crossing etc. according to system requirements and cross chips considers.
OTU
kdata via line plate 50 export, through de-mapping unit 101, extract ODU
ctime slot frame, then forms unified frame format ODU in interleave unit 102
d, then play backboard, enter repeat in work module 20 and carry out jumbo cross scheduling, the particle ODU after intersection
doDU is obtained after deinterleaving unit 301 carries out 2bit deinterleaving
cand enter map unit 302, finally export from wiring board 50.Wherein, de-mapping unit 101, repeat in work module 20, map unit 302 all have overhead processing, are undertaken by spending process module 40, and this module realizes the function of monitoring, maintenance management.System block diagram as shown in Figure 3.
Set forth the implementation method of the Bit Interleave of Bit interleaving block below:
System parameters: the ration of division is 4, number of time slots is m, and backboard speed is N Gbit/s, and intersecting grain is ODU
k.
Define into the frame before interleaving block be ODU
c, after intertexture, the frame format of lower backboard is ODU
d.ODU
cframe is 4 row, and often row 4080 arranges, ODU
dframe is 2 row, and often row 4080 arranges.
By 2 ODU
cframe is mapped to 4 ODU
d, adopt 2 Bit Interleave technology.
First, ODU
dbe divided into 4 time slots, from the 9th byte (front 8 bytes are frame head and BIP-8 (byte for error correction)), 2 row altogether, often row 4080 arranges.Row 1 row 9,13,17, until row 2 row 4077 are a time slot, row 1 row 10,14,18, until row 2 row 4078 are a time slot, row 1 row 11,15,19, until row 2 row 4079 are a time slot, row 1 row 12,16,20, until row 2 row 4080 are a time slot.
First ODU
cbe mapped to 4 ODU
dtime, need ODU
cin each byte be divided into 4 parts, every part of 2bit, for odd column byte (columns is from 1), 7 to the position, position 6 of this byte is put into the 1st ODU
d7 to the position, position 6 of a byte of frame, puts into the 2nd ODU by 5 to the position, position 4 of this byte
dthe position 7 of a byte of frame most 6, the like, this odd bytes will put into 4 ODU like this
d7 to the position, position 6 of a byte of frame; For even column byte, equally this byte is divided into 4 2bit, then puts into 4 ODU
d5 to the position, position 4 of a byte of frame, the ODU of such 2 bytes
c4 ODU will be placed into
dfront nybble, each ODU
d3 to the position, position 0 of byte leaves the 2nd ODU for
cframe, like this can by 2 ODU
csignal averaging is assigned to 4 ODU
don the signal of speed, each ODU
d7 to position, position 4 comprise the 1st ODU
cthe content of odd and even number byte, 3 to position, position 0 comprises the 2nd ODU
cthe content of odd and even number byte.2bit interleaving process in table 1 to table 6.ODU in table 1 to table 6
c_ 1_1_1 represents first ODU
cthe first row first row, the like.
In table 1 to table 6, a grid represents an ODU
c2 of 1 byte in frame, each grid represents an ODU
codd number or even column byte 2 in frame, 2 ODU
call odd bytes in frame and even bytes will be evenly distributed to 4 ODU
don frame, like this for each ODU
dframe, can be divided into 4 parts by a byte, every part of 2 positions, and every 2 represent certain ODU
ceven bytes in frame or odd bytes, only need at multiple ODU
dthe exchange realizing between 4 adjacent byte any 2 in frame can realize 2 ODU
cany exchange in frame between adjacent 8 bytes.
After 2 Bit Interleave process, every 4 ODU
din all contain 2 ODU
call time slots.Each Time Slot Occupancy 2bit data, every 4 bytes complete and once circulate.
Table 1 the 1st ODU
cframe
| Odd column | Even column | Odd column | Even column | |
| Bit7-6 | ODU c_1_1_1 | ODU c_1_1_2 | ODU c_1_1_3 | ODU c_1_1_4 |
| Bit5-4 | ODU c_1_2_1 | ODU c_1_2_2 | ODU c_1_2_3 | ODU c_1_2_4 |
| Bit3-2 | ODU c_1_3_1 | ODU c_1_3_2 | ODU c_1_3_3 | ODU c_1_3_4 |
| Bit1-0 | ODU c_1_4_1 | ODU c_1_4_2 | ODU c_1_4_3 | ODU c_1_4_4 |
Table 2 the 2nd ODU
cframe
| Odd column | Even column | Odd column | Even column | |
| Bit7-6 | ODU c_2_1_1 | ODU c_2_1_2 | ODU c_2_1_3 | ODU c_2_1_4 |
| Bit5-4 | ODU c_2_2_1 | ODU c_2_2_2 | ODU c_2_2_3 | ODU c_2_2_4 |
| Bit3-2 | ODU c_2_3_1 | ODU c_2_3_2 | ODU c_2_3_3 | ODU c_2_3_4 |
| Bit1-0 | ODU c_2_4_1 | ODU c_2_4_2 | ODU c_2_4_3 | ODU c_2_4_4 |
Table 3 the 1st ODU
dframe
| Odd column | Even column | |
| Bit7-6 | ODU c_1_1_1 | ODU c_1_1_3 |
| Bit5-4 | ODU c_1_1_2 | ODU c_1_1_4 |
| Bit3-2 | ODU c_2_1_1 | ODU c_2_1_3 |
| Bit1-0 | ODU c_2_1_2 | ODU c_2_1_3 |
Table 4 the 2nd ODU
dframe
| Odd column | Even column | |
| Bit7-6 | ODU c_1_2_1 | ODU c_1_2_3 |
| Bit5-4 | ODU c_1_2_2 | ODU c_1_2_4 |
| Bit3-2 | ODU c_2_2_1 | ODU c_2_2_3 |
| Bit1-0 | ODU c_2_2_2 | ODU c_2_2_3 |
Table 5 the 3rd ODU
dframe
| Odd column | Even column | |
| Bit7-6 | ODU c_1_3_1 | ODU c_1_3_3 |
| Bit5-4 | ODU c_1_3_2 | ODU c_1_3_4 |
| Bit3-2 | ODU c_2_3_1 | ODU c_2_3_3 |
| Bit1-0 | ODU c_2_3_2 | ODU c_2_3_3 |
Table 6 the 4th ODU
dframe
| Odd column | Even column | |
| Bit7-6 | ODU c_1_4_1 | ODU c_1_4_3 |
| Bit5-4 | ODU c_1_4_2 | ODU c_1_4_4 |
| Bit3-2 | ODU c_2_4_1 | ODU c_2_4_3 |
| Bit1-0 | ODU c_2_4_2 | ODU c_2_4_3 |
Total thinking of Bit Interleave is: all business are divided into an identical n fragment, and each fragment interleave circuit intersects, and the cross-over configuration of n cross chips is duplicate.By than deinterleave circuit, business fragment after intersection is spelled again.The capacity of whole intersection equals the capacity of n cross chips, and the whole quantity to smallest particles repeat in work equals the quantity of intersecting to smallest particles degree of single cross chips.
Composition graphs 3 describes the flow chart (as shown in Figure 4) of time slot cross method according to the preferred embodiment of the invention in detail, comprises the following steps:
Step S402, wiring board exports OTU
kframe;
Step S406, by OTU
kframe demapping is ODU
cframe;
Step S408, to ODU
cframe carries out 2bit intertexture, by 2 ODU
cframe is mapped to 4 ODU
dframe;
Step S410, to ODU
dframe carries out the scheduling of Large Copacity time-slot cross;
Step S412, to the ODU that repeat in work module exports
dframe carries out 2bit deinterleaving, by 4 ODU
dframe demapping is to 2 ODU
cframe;
Step S414, by ODU
cframe is mapped as OTU
kframe;
Step S416, exports OTU by wiring board
kframe.
Fig. 5 shows the flow chart of 2 Bit Interleaves according to the preferred embodiment of the invention, comprises the following steps:
Step S502, by ODU
ddata frame dividing time slot;
Step S504, by first ODU
cdata frame dividing time slot;
Step S506, by ODU
cthe odd numbered slots of Frame loads 4 ODU
din Frame;
Step S508, judges whether odd numbered slots all loads 4 ODU
din Frame, if so, then proceed to step S510, if not, then return step S506;
Step S510, by ODU
cthe even timeslots of Frame loads 4 ODU
din Frame;
Step S512, judges whether even timeslots all loads 4 ODU
din Frame, if so, then proceed to step S514, if not, then return step S510;
Step S514, continues second ODU
cdata frame dividing time slot, and according to above-mentioned steps S506 to step S512 respectively by second ODU
cthe odd numbered slots of Frame and even timeslots all load 4 ODU
din Frame.
As can be seen from the above description, present invention achieves following technique effect:
(1) due to the method by adopting Bit Interleave before entering cross matrix in data, the data of intersecting are carried out bitslicing by time slot, so be equivalent to one-level intersection many, the capacity of intersection can have been improved on the one hand, the difficulty of intersection can have been reduced on the other hand.
(2) can system resource be reduced, reduce costs and design difficulty simultaneously, shorten time to market (TTM).
Obviously, those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on network that multiple calculation element forms, alternatively, they can realize with the executable program code of calculation element, thus, they can be stored and be performed by calculation element in the storage device, or they are made into each integrated circuit modules respectively, or the multiple module in them or step are made into single integrated circuit module to realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a time slot cross method, is characterized in that, comprising:
To OTU
kframe carries out demapping and intertexture, obtains ODU
dframe, wherein, to OTU
kframe carries out demapping and intertexture, obtains ODU
dframe comprises: from OTU
kseparate output time slot frame in Frame, after removing the byte of padding in described time slot frame, obtain ODU
cframe; To described ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe;
By the ODU obtained after demapping and intertexture
dframe carries out Large Copacity time-slot cross;
To the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe.
2. method according to claim 1, is characterized in that, described ODU
cthe frame structure of Frame is 4 row, and often row 4080 arranges; Described ODU
dthe frame structure of Frame is 2 row, and often row 4080 arranges.
3. method according to claim 2, is characterized in that, to the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe comprises:
To described ODU after Large Copacity time-slot cross
dframe carries out 2 than deinterleave, obtains ODU
cframe;
By the ODU obtained after deinterleaving
cframe is converted to time slot frame, and the method adopting byte to interleave is assembled into OTU add byte of padding in described time slot frame after
kframe.
4. method according to claim 1, is characterized in that, to described ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe comprises:
By 2 ODU
cframe is mapped to 4 ODU
dframe, comprising:
By described 2 ODU
ceach ODU of Frame
ceach byte in Frame is divided into 4 parts, every part of 2 bits;
By described 2 ODU
cfirst ODU in Frame
c7 to the position, position 6 of the odd column byte of Frame, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into described 4 ODU respectively
d7 to the position, position 6 of a byte of Frame, 7 to the position, position 6 of even column byte, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into described 4 ODU respectively
d5 to the position, position 4 of the described byte of Frame;
By described 2 ODU
csecond ODU in Frame
c7 to the position, position 6 of the odd column byte of Frame, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into described 4 ODU respectively
d3 to the position, position 2 of the described byte of Frame, 7 to the position, position 6 of even column byte, 5 to position, position 4,3 to position, position 2 and 1 to position, position 0 put into described 4 ODU respectively
d1 to the position, position 0 of the described byte of Frame.
5. a time-slot cross system, is characterized in that, comprising:
Demapping interleaving block, for OTU
kframe carries out demapping and intertexture, obtains ODU
dframe, wherein, described demapping interleaving block comprises: de-mapping unit, for from OTU
kseparate output time slot frame in Frame, after removing the byte of padding in described time slot frame, obtain ODU
cframe; Interleave unit, for described ODU
cframe carries out 2 Bit Interleaves and obtains ODU
dframe; Described interleave unit is also for by 2 ODU
cframe is mapped to 4 ODU
dframe;
Repeat in work module, for the ODU will obtained after demapping and intertexture
dframe carries out Large Copacity time-slot cross;
Deinterleaving mapping block, for the ODU after Large Copacity time-slot cross
dframe carries out deinterleaving and mapping obtains OTU
kframe.
6. system according to claim 5, is characterized in that, described deinterleaving mapping block comprises:
Deinterleaving unit, for described ODU after Large Copacity time-slot cross
dframe carries out 2 than deinterleave, obtains ODU
cframe;
Map unit, for the ODU will obtained after deinterleaving
cframe is converted to time slot frame, and the method adopting byte to interleave is assembled into OTU add byte of padding in described time slot frame after
kframe.
7. the system according to claim 5 or 6, is characterized in that, also comprises:
Spending process module, for monitoring and maintenance management described de-mapping unit and described repeat in work module.
8. system according to claim 6, is characterized in that, also comprises:
Spending process module, for monitoring and maintenance management described map unit.
9. system according to claim 7, is characterized in that, described de-mapping unit, described interleave unit, described repeat in work module, described spending process module are realized by field programmable gate array chip.
10. system according to claim 8, is characterized in that, described deinterleaving unit, described map unit are realized by field programmable gate array chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209621.XA CN101702637B (en) | 2009-10-30 | 2009-10-30 | Time slot cross method and system |
| PCT/CN2010/073480 WO2010145455A1 (en) | 2009-10-30 | 2010-06-02 | Method and system for time slot cross |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209621.XA CN101702637B (en) | 2009-10-30 | 2009-10-30 | Time slot cross method and system |
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| CN101702637A CN101702637A (en) | 2010-05-05 |
| CN101702637B true CN101702637B (en) | 2015-01-28 |
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| CN101702637B (en) * | 2009-10-30 | 2015-01-28 | 中兴通讯股份有限公司 | Time slot cross method and system |
| CN101848066B (en) | 2010-06-08 | 2014-08-13 | 中兴通讯股份有限公司 | De-mapping method and device of optical transmission unit frame |
| CN109728968B (en) * | 2017-10-31 | 2022-01-14 | 华为技术有限公司 | Method, related equipment and system for obtaining target transmission path |
Citations (4)
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| EP0936771A2 (en) * | 1998-02-13 | 1999-08-18 | Lucent Technologies Inc. | Optical signal translator unit |
| CN1791278A (en) * | 2004-12-14 | 2006-06-21 | 华为技术有限公司 | Synchronous optical network and optical transmission network uniform dispatching system and its method |
| CN1859434A (en) * | 2005-12-29 | 2006-11-08 | 华为技术有限公司 | Multiple service device and its signal processing method based on primary group |
| CN101389146A (en) * | 2007-09-13 | 2009-03-18 | 华为技术有限公司 | Method and apparatus for synchronous crossed scheduling of optical transmission network |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1842221A (en) * | 2005-03-31 | 2006-10-04 | 华为技术有限公司 | Service signal dispatching method and device in optical transport network |
| CN101030827B (en) * | 2006-03-03 | 2011-04-20 | 华为技术有限公司 | Method and apparatus for mapping DTM to OTN |
| CN101170550B (en) * | 2007-11-22 | 2010-05-26 | 中兴通讯股份有限公司 | A transparent transmission method for 10000M Ethernet signals in optical transmission network |
| CN101702637B (en) * | 2009-10-30 | 2015-01-28 | 中兴通讯股份有限公司 | Time slot cross method and system |
-
2009
- 2009-10-30 CN CN200910209621.XA patent/CN101702637B/en not_active Expired - Fee Related
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0936771A2 (en) * | 1998-02-13 | 1999-08-18 | Lucent Technologies Inc. | Optical signal translator unit |
| CN1791278A (en) * | 2004-12-14 | 2006-06-21 | 华为技术有限公司 | Synchronous optical network and optical transmission network uniform dispatching system and its method |
| CN1859434A (en) * | 2005-12-29 | 2006-11-08 | 华为技术有限公司 | Multiple service device and its signal processing method based on primary group |
| CN101389146A (en) * | 2007-09-13 | 2009-03-18 | 华为技术有限公司 | Method and apparatus for synchronous crossed scheduling of optical transmission network |
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| CN101702637A (en) | 2010-05-05 |
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