CN101699390B - Self-correction precursor 0/1 predicting unit for floating-point adder - Google Patents

Abstract

The invention relates to a self-correction precursor 0/1 predicting method for a floating-point adder, which adopts the combination method of a multiple-input logical gate and parallel computation to realize an output result as a final correct result, and the output result has no need to be corrected by depending on an adder; the parallel computation is adopted, for example, the operand bit wide is increased, and the critical path length can not be influenced. When the floating-point add is computed, the displacement time and index regulating information needed by the normalization of a computation result is synchronously predicted, a predicting result is not output by the adder but is generated by the predicting unit and is a corrected value which has no need to be further corrected, and the critical path of the predicting unit can not be lengthened along with lengthening the bit wide of an operand.

Description

Be used for floating-point adder from leading 0/1 predicting unit of error correction

Technical field

The present invention relates to a kind of leading 0/1 Forecasting Methodology, be specifically related to a kind of be used for floating-point adder from leading 0/1 Forecasting Methodology of error correction.

Background technology

Document " " Parallel error detection forleading zero anticipation " .Journal of Computer Science andTechnology; v 21; n 6, p 901-906, November 2006. for G.Zhang; W.Hu, Z.Qi " has proposed a kind of parallel totalizer carry signal that do not rely on and just can realize leading 0, the 1 predicting unit error correcting technique of error correction and be achieved.Its main thought is to utilize " positive tree " and " negative tree " that the result of " positive encoding " and " negative encoding " is compressed, at last through or logic export correct result.Its distinctive tree-shaped pressure texture makes its " encoding " signal just finally arrive output terminal through a series of logic gates, and the tree structure of this classification, its critical path depth is by its progression decision, and progression is determined by the operand bit wide.For the bigger operand of bit wide, the technological shortage advantage of this kind.

Document " O.Mauro, P.Francesco; S.Simone; V.Giuseppe, " Analysisand implementation of a novel leading zero anticipation algorithmfor floating-point arithmetic units ", IEEE Transactions onCircuits and Systems II:Express Briefs; V 54; N 8, p 685-689, August2007. " the middle Forecasting Methodology that proposes; a bit error might appear in its result, need utilize the output of totalizer most significant digit to come further error correction.

Leading 0/1 predicting unit in the document " IEEE Transactions on Very LargeScale Integration (VLSI) Systems; v 16; n 7, p 837-850, July 2008. for D.Giorgos, G.Kostas, M.Christos; N.Dimitris, " Low-power leading-zero counting and anticipation logic forhigh-speed floating point units " "; Predict a kind of result as output, and utilize " decision logic " that result's correctness is judged.In case " decision logic " finds that the output result is wrong, just must be to exporting displacement that the result carries out the 1-2 position to obtain correct result.Under the wrong situation of prediction, certainly will influence output result's speed.

Leading 0,1 predicting unit of typical case is following; Leading 0 predicting unit is meant and is used for 0 on the high position of specified data up to the unit that first that part of data length of 1 occurs that it comprises LZA (Leading Zero Anticipation: leading 0 prediction) with LZC (Leading ZeroCounting: leading 0 counts) two parts; Leading 1 predicting unit is meant and is used for 1 on the high position of specified data up to the unit that first that part of data length of 0 occurs that it comprises LOA (LeadingOne Anticipation: leading 1 prediction) with LOC (Leading One Counting: leading 1 counts) two parts.

For a definite binary number, if it contains the leading 0 of k position, then these data can be expressed as 0 ^k1x ^*Form, wherein index k represents leading 0 number, x represents 0 or 1 arbitrary number, and * represents after the x 0 or the x of position arbitrarily.Similarly, for a definite binary number, if it contains the leading 1 of k position, then these data can be expressed as 1 ^k0x ^*Form, wherein index k represents leading 1 number, x represents 0 or 1 arbitrary number, and * represents after the x 0 or the x of position arbitrarily.Therefore detect leading 0 and comprised, comprised confirming in other words 1 the conversion of leading k position 0 on the k+1 position to the confirming of first non-zero number word bit.Similarly leading 1 prediction also be to data for the first time from 1 convert into adjacent 0 position confirm the same.

Common two number additions can be classified as three kinds of situation: two positive number additions, two negative additions, a positive number and a negative addition.In floating-point adder; Because the figure place of two operands need be passed through and just can be carried out computing to bit shift; So when two positive number additions or two negative additions, can not produce leading 0 or leading 1, so need not leading 0 or leading 1 judging to result's this moment.And have only when the operand of two contrary signs is done addition, just might produce a large amount of leading 0,1.This so-called effectively subtraction (effective subtraction).

Leading 0 appears at when carrying out effective subtraction (comprising that jack per line two operands subtract each other and contrary sign two operand additions) operation, when subtraction result is positive; Leading 1 appears at when carrying out effective subtraction, and subtraction result is for negative the time.Leading 0 predicting unit is through input signal A and B to floating-point adder, and each after displacement, arrangement, negate is carried out logical operation, again through operation result being handled the final purpose that realizes prediction leading 0.Its required logical operation comprises:

$T=A\⊕B---\left(1\right)$

G＝A·B (2)

Z＝A·B (3)

When the form of the beginning section of logic operation result is: (here, symbol T, G, the Z of beginning field on each represents T=1, G=1 or Z=1 on this position respectively during T*GZ*; And wherein first * representative has the T of most significant digit to have a number arbitrarily to repeat to occur more than or equal to 0 T at the back; Second * represents arbitrary fields), occur leading 0.Suppose that there is the n position first and the unmatched position of T*GZ* form before occurring; So A/B with in will have n perhaps (n-1) individual leading 0 occur; This depends on the form of this position (n+1 position) that do not match: if T, the result is uncertain, see it is whether carry signal is arranged on the n+1 position; If but G then has n-1 position leading 0.Similarly for the result with the beginning of T*ZG* form, will produce leading 1.Suppose that there is the n position the unmatched position of first and T*ZG* form before occurring, so A/B with in will have n perhaps (n-1) individual leading 1 occur, this depends on the form of this position (n+1 position) that do not match: if T then need investigate the carry signal on the n+1 position; If Z then has n-1 position leading 1.In addition, as a supplement, for non-effective subtraction, when the result with Z* at the first bruss, also can occur leading 0.Similarly, when the result with G* at the first bruss, can occur leading 1.

In the normalization operation of floating number, the operation of confirming to leading 0 also can appear.At this moment, can regard a floating number as and a numeral 0 is done plus and minus calculation, the result starts with Z*.Therefore, if leading 0 predicting unit is used for the normalization operation of subtraction and floating number simultaneously, then must respectively corresponding two kinds of operations, predict the outcome to leading 0 and to distinguish.Could produce leadingly 0 with T* beginning for the subtraction result, for the floating number normalization operation, its result should start with Z* could produce leading 0.But for the normalization operation of floating number, its low level can not produce carry and make the generation error that predicts the outcome to a high position, need not to do in addition correction so it predicts the outcome.

(1) generally leading 0,1 position confirms

Whether for any one data is that required definite primary first derivative (is counted from the high position of data; After leading 0 first 1 or guide 1 after first 0), can be through confirming in the logical calculated to it and three bit data adjacent with its left and right sides.Definition of data indicating bit mark f thus _i, adopt the initial order of high order end here:

f ₀＝T ₀T ₁ (4)

f _i＝T _i-1(G _iZ _i+1+Z _iG _I+1)+T _i-1(Z _iZ _i+1+G _iG _I+1) (5)

F when the i position _iValue is 1, and not have more high-order value be 1 o'clock, and guide's numerical digit of then being asked is put and just is on i position or the i+1 position.

If leading 0,1 prediction realizes that respectively predicting unit only needs i position and i+1 position are calculated so.For leading 0 predicting unit, have:

$f_i^{\mathrm{zeros}}=T_i\⊕\stackrel{\‾}{Z_{i+1}},i\≥0---\left(6\right)$

F when the i position _iValue is 1, and not have more high-order value be 1 o'clock, then asked leading 0 after first 1 just appear on i position or the i+1 position.

Similarly, have for leading 1 prediction:

$f_i^{\mathrm{ones}}=T_i\⊕\stackrel{\‾}{G_{i+1}},i\≥0---\left(7\right)$

Equally, as the f of i position _iValue is 1, and does not have more high-order f _iValue be 1 o'clock, then asked leading 1 after first 0 just appear on i position or the i+1 position.Thus, if with leading 0,1 predicting unit separately, will simplify many for prediction algorithm so.Leading 0 for only predicting, can be with asking for f _iSimplified formula be:

f _i＝T _i·Z _i+1，i≥0 (8)

In like manner, leading 1 for only considering prediction, can formula be become:

f _i＝T _i·G _i+1，i≥0 (9)

(2) coding of leading 0 number statistics

The method that two kinds of leading 0 numbers of basic statistics are arranged all is through to f _iThe field of forming is handled, and confirms leading 0 number.One of which is exactly directly the number of first 1 front 0 to be handled, and another one just is to use classification tree to handle.In the method for directly setting up dull field, should at first find out the position at first 1 place, set up monotonic segment through following relational expression:

$F_i=\underset{j=0}{\overset{i}{\mathrm{\Σ}}}{f}_j---\left(10\right)$

L _i＝F _i-1·f _i (11)

In case field is set up, then the position of i and i+1 just can draw.

(3) error correction in leading 0,1 prediction

Aforesaid leading 0 predicting unit is coarse: possibly produce one error during counting.Typical leading 0,1 predicting unit is eliminated this error when being shifted.One faster method be when carrying out normalization shift, to carry out error correction.Promptly when accurate displacement, the result is adjusted, this has with regard to a high position that requires shift unit and judges whether to exist leading 0 ability.Also have a kind of circuit faster to realize this function in addition, it has used the PREDICTIVE CONTROL signal.If the LZA prediction needs to move the n position, but being checked through the n position is 0, then produces the PREDICTIVE CONTROL signal, makes and finally moves the n+1 position, otherwise, then finally move the n position and get final product.

Having proposed error correcting in the document can realize through the carry signal to prediction bits equally.For bit preamble i, the mistake indication can be expressed as:

$e_i=L_i{T}_{i+1}(C_{i+1}\⊕(T_i+\left(\stackrel{\‾}{A_i\⊕T_{i-1}}\right)))---\left(12\right)$

C _I+1It is the carry signal of i+1 position; A _iBe to add numerical digit.Then global error is judged signal:

$e=\underset{i}{\mathrm{\Σ}}{e}_i---\left(13\right)$

Also have document to introduce the error indication signal of other a kind of equivalence:

$e_i=L_i(T_{i-1}\⊕A_i\⊕\stackrel{\‾}{C_i})---\left(14\right)$

C wherein _iIt is the carry signal of i position.It is thus clear that above-mentioned two kinds of methods all need produce corrected signal by the totalizer carry signal.

Summary of the invention

The objective of the invention is to overcome the shortcoming of above-mentioned prior art; Provide a kind of can be when calculating floating add; Result of calculation standardized handle the required shift count that carries out and the index adjustment information is made synchronous prediction; And predict the outcome and do not rely on totalizer output and only produce by predicting unit; The right value that predicts the outcome and further revise for need not, the critical path of predicting unit are can be because of the lengthening of the bit wide of operand not elongated be used for floating-point adder from leading 0/1 predicting unit of error correction.

For achieving the above object, the technical scheme that the present invention adopts is:

1) adopts leading 0 predicting unit and the discrete way of leading 1 predicting unit, then have following two formulas to come computational data indicating bit mark f respectively _i:

f _i＝T _i·Z _i+1，i≥0 (15)

f _i＝T _i·G _i+1，i≥0 (16)

Wherein, Formula (15) is asked for formula for prediction field among the LZA, and formula (16) is asked for formula for prediction field among the LOA, and what the LZA of two separations and LOA obtained predicts the outcome; Be used to from totalizer and the most significant digit carry select: if most significant digit produces carry; Explain and for just, then need predict leading 0, select predicting the outcome of LZA; If most significant digit does not produce carry, explain and be negative, then need predict leading 1, select predicting the outcome of LOA;

2) leading 0, the 1 prediction error correction unit of high speed

No matter for LAZ or LOA, have only in the prediction field, T*GZ* or T*ZG* section follow hard on T at the back; Just need the n-1 of output be revised; In order to judge whether to revise to output, need make judgement to the n position in the prediction field, utilize the output L of LZC and LOC _iThe T signal is handled, and is judged, have through result:

$F_i=\underset{j=0}{\overset{i}{\mathrm{\Σ}}}{f}_i---\left(21\right)$

L _i＝F _i-1·f _i (22)

Wherein, for leading 0 prediction, have:

f _j＝T _j·Z _j+1，j≥0

Have for leading 1 prediction:

f _j＝T _j·G _j+1，j≥0

F _iBe f _jFrom the 0th step-by-step or operation to the i position;

F _iHave following characteristics:

There is a definite n, makes for the F of i＜n arbitrarily _iBe 0, all the other F _iBe 1, any f for j＜n is promptly arranged _j=0, adopt " big end order " here, F _iWord string as a result for LZA/LOA output;

L _iHave following characteristics:

N for confirming has L _n=1, all the other L _i=0, for LZC/LOC not by the output of error correction;

Ask the method for judging enable signal EN;

en _i＝L _i·T _i+1 (23)

EN＝∑en _i (24)

$T_{i+1}=A_{i+1}\⊕B_{i+1},$ A and B are two addends, and EN is en _iStep-by-step or result, EN is as the enable signal that whether need revise judgement to predicting the outcome;

N for confirming has L _n=1, at this moment have only T _N+1=1 o'clock, just need whether need revise and judge, be i.e. en the result _nJust possibly need in=1 o'clock to revise, EN is the single enable signal that en is compressed into;

If EN=0 need not to revise the output result, also just need not to judge whether to revise;

If during EN=1, need whether revise the result and judge, judge whether and to do correction to output n-1 that the n+1 position of promptly known prediction field is T, predicts so whether the n+1 position of field exists carry signal C _n, if T _n=1, then only need to judge carry signal C _nValue, for this reason, introduce a new internal signal K, it is defined as:

K ₀＝0 (25)

K _i＝T _i-1G _i，i≥1 (26)

If K _m=1, m＞n, and K _i≠ 1 (n＜i＜m), as long as then there is T _i≠ 1 (n＜i＜m) just can judge C _nValue must be 0, K handles as follows to field:

For leading 0 predicted portions, utilize LZC to produce signal F field K handled:

$F_i=\underset{j=0}{\overset{i}{\mathrm{\Σ}}}{f}_i---\left(27\right)$

K′ _i＝K _i·F _i，i≥0 (28)

With method the T signal is handled:

T _i′＝T _i·F _i，i≥0 (29)

More than two formulas be to be used for to K and T signal the 1st to carry out zero clearing to the n position and handle, then K ' is 0 field after the zero clearing of n position to the K field, and K ' is handled, with K ' all zero clearings later on from the m position, 0 all puts 1 to the m-1 position:

$Q_i=\stackrel{\‾}{\underset{j=0}{\overset{i}{\mathrm{\Σ}}}{K^{\′}}_j}---\left(30\right)$

T ', Q signal are carried out step-by-step and operation, promptly obtain to contain aiming field, and remainder are put 0 field entirely:

d _i＝T _i′·Q _i，i≥0 (31)

D＝EN·∑d _i (32)

If D=1 then can not produce carry signal C _n, need revise for leading 0 prediction, be about to n and replace n-1 as prediction output result; For leading 1 prediction, need not to revise accordingly.

The method that the present invention adopts many input logic gates and parallel computation to combine has realized that the output result is final correct result, needn't rely on the totalizer result and revise; Adopted parallel computation, increased, can not influence critical path depth like the operand bit wide.

Description of drawings

Fig. 1 is one-piece construction figure of the present invention;

Fig. 2 is leading 0 error correction logic structural drawing.

Embodiment

Below in conjunction with accompanying drawing the present invention is done further explain.

Referring to Fig. 1, be used for floating-point adder from leading 0/1 predicting unit of error correction, for the add operation of two certain number, can handle and to draw T, G, Z signal through it being carried out step-by-step, T, G, three signals of Z are handled just can be realized leading 0,1 prediction again.Owing to adopt leading 0,1 predicting unit way of combining, must make hardware configuration complicated, critical path is elongated, is unfavorable for raising speed.So adopt in the design of the present invention leading 0 predicting unit and the discrete way of leading 1 predicting unit, then have following two formulas to calculate f respectively _i:

f _i＝T _i·Z _i+1，i≥0 (15)

f _i＝T _i·G _i+1，i≥0 (16)

Wherein, formula (15) is asked for formula for prediction field among the LZA, and formula (16) is asked for formula for prediction field among the LOA.What the LZA of two separations and LOA obtained predicts the outcome, can be used to from totalizer and the most significant digit carry select:, explain and for just, then need predicted leading 0 that selection LZA predicts the outcome if most significant digit produces carry; If most significant digit does not produce carry, explain and be negative, then need predict leading 1, select predicting the outcome of LOA.

(1) predicated error produces the analysis of causes

At first analyzing, LZA produces reasons of error.For the prediction of LZA,, predict that then the form that field begins must be T*GZ* if exist leadingly 0 among the result.Suppose that T*GZ* has the n position, and C _iIt is the carry signal of i position.Work as C _N-1, should C be worked as in the additive operation result n-1 position that moves to left at=1 o'clock _N-1=0 o'clock, should be with the additive operation result n position that moves to left.Following surface analysis C _N-1The value of signal.It is thus clear that, and then begin field and have only following two kinds of situation:

$T*\mathrm{GZ}*\left\{\begin{array}{c}\mathrm{GX}*\\ \mathrm{TX}*\end{array}\right.$

If behind the T*GZ* is G, then must produce carry to last position (n-1 position); If be T behind the T*GZ*, then to see whether have carry signal to pass over thereafter and T position summation itself to last (n-1 position) generation carry.Thus, the value that draws final shift signal is answered condition:

, should satisfy final shift signal when getting n:

T _n·C _n＝1 (17)

, should satisfy final shift signal when getting n-1:

G _n+T _n·C _n＝1 (18)

For the prediction of LOA,, predict that then the form that field begins must be T*ZG* if exist leadingly 1 among the result.Same hypothesis T*ZG* has the n position, and C _iIt is the carry signal of i position.Work as C _N-1, should C be worked as in the additive operation result n position that moves to left at=1 o'clock _N-1=0 o'clock, should be with the additive operation result n-1 position that moves to left.Next still analyze C _N-1The value of signal.Be not difficult to find out, and then begin field and have only two kinds of situation as follows:

$T*\mathrm{ZG}*\left\{\begin{array}{c}\mathrm{ZX}*\\ \mathrm{TX}*\end{array}\right.$

If behind the T*ZG* is Z, then must can not produce carry to last position (n-1 position); If be T behind the T*ZG*, then to see whether have carry signal to pass over thereafter and T position summation itself to last (n-1 position) generation carry.Thus, the value that draws final shift signal is answered condition:

, should satisfy final shift signal when getting n:

T _n·C _n＝1 (19)

, should satisfy final shift signal when getting n-1:

Z _n+T _n·C _n＝1 (20)

In sum, under random case, G is got in the n+1 position of prediction field in LZA _n, T _nProbability is identical, and C _nWhen the probability of value 1,0 was also identical, the probability that shift signal is got n-1 was 75%, and similarly for LOA, Z is got in the n+1 position of prediction field _n, T _nProbability is identical, and C _nWhen the probability of value 1,0 was also identical, the probability that shift signal is got n-1 was 75%, thus select the output of n-1 here as predicting unit, and pass through T _n, C _nRevise predicting the outcome.

Because this kind amendment scheme need utilize totalizer carry signal C _nRevise predicting the outcome, must let leading 0,1 predicting unit wait for totalizer output result in the use, be unfavorable for that speed improves, so following the present invention proposes a kind of scheme of corrected signal being judged in leading 0,1 predicting unit inside.

(2) proposition of leading 0, the 1 prediction error correction unit of high speed

By last, no matter for LAZ or LOA, to have only in the prediction field, T*GZ* or T*ZG* section follow hard on T at the back, just need the n-1 of output be revised.Then need revise output, need make judgement the n position in the prediction field in order to judge whether.Utilize the output L of LZC and LOC _iThe T signal is handled, and is judged, have through result:

$F_i=\underset{j=0}{\overset{i}{\mathrm{\Σ}}}{f}_j---\left(21\right)$

L _i＝F _i-1·f _i (22)

Ask the method for judging enable signal EN;

en _i＝L _i·T _i+1 (23)

EN＝∑en _i (24)

When EN=1, need whether revise the result and judge; When EN=0 need not to revise the output result, also just need not to judge whether to revise.

If need judge whether and need do correction to output n-1, the n+1 position of promptly known prediction field is T, and key is whether the n+1 position of predicting field exists carry signal C _nIf T _n=1, then only need to judge carry signal C _nValue.For this reason, the present invention introduces a new internal signal K, and it is defined as:

K ₀＝0 (25)

K _i＝T _i-1G _i，i≥1 (26)

If K _m=1, m＞n, and K _i≠ 1 (n＜i＜m), as long as then there is T _i≠ 1 (n＜i＜m) just can judge C _nValue must be 0.Can handle as follows field K:

For leading 0 predicted portions, utilize LZC to produce signal F field K handled:

$F_i=\underset{j=0}{\overset{i}{\mathrm{\Σ}}}{f}_i---\left(27\right)$

K′ _i＝K _i·F _i，i≥0 (28)

With method the T signal is handled:

T _i′＝T _i·F _i，i≥0 (29)

More than two formulas be to be used for to K and T signal the 1st to carry out zero clearing to the n position and handle.Then K ' is 0 field after the zero clearing of n position to the K field.Next K ' is handled, with K ' zero clearings later on all from the m position, 0 all puts 1 to the m-1 position:

$Q_i=\stackrel{\‾}{\underset{j=0}{\overset{i}{\mathrm{\Σ}}}{K^{\′}}_j}---\left(30\right)$

So, T ', Q signal are carried out step-by-step and operation, promptly obtain to contain aiming field, and remainder are put 0 field entirely:

d _i＝T _i′·Q _i，i≥0 (31)

D＝EN·∑d _i (32)

If D=1 then can not produce carry signal C _n, need revise for leading 0 prediction; For leading 1 prediction, need not to revise accordingly.

The present invention design from leading 0, the 1 predicting unit one-piece construction of error correction shown in accompanying drawing 1.When leading 0,1 predicting unit is worked, at first ask for by the value of the T of operand, G, Z, and it is sent into LZA, LOA respectively, asks K logic and error correction unit through " asking for T, G, Z logic ".By the error correction unit consequential signal L, the F that T, K and LZC or LOC produce handled again, obtain error correction information the output result of LZC or LOC is revised, to obtain correct displacement information.Select corresponding leading 0 or leading 1 to predict the outcome through the totalizer carry signal, it is sent into index adjustment unit and shift unit to the floating-point adder result processing of standardizing.

With the corresponding error correction processing unit of leading 0 predicting unit is example, error correcting unit inner structure is explained, shown in accompanying drawing 2.Wherein L, F signal be all from the LZC parts, and T, K signal are from separately generation logic." summation " is meant with many inputs of input signal utilization or door step-by-step summation (being that the logical "or" operation is carried out in step-by-step), to obtain EN signal and D signal.Product is represented the logical operation, and the error correction logic with shift is through the error correction shift signal original leading 0 prediction to be wished that the n-1 of output is modified to n, and the character string as a result that is about to leading 0 predicting unit generation moves to left one.Accordingly, for the error correction unit of leading 1 predicting unit, the negate of D input signal can realize the error correction to leading 1 predicting unit.

Claims (1)

1. be used for floating-point adder from leading 0/1 Forecasting Methodology of error correction, it is characterized in that:

1) adopts leading 0 predicting unit and the discrete way of leading 1 predicting unit, then have following two formulas to come computational data indicating bit mark f respectively _i:

Wherein, Formula (15) is that the prediction field is asked for formula among the LZA (leading 0 prediction is represented in the abbreviation of Leading Zero Anticipation), and formula (16) is the LOA (abbreviation of Leading One Anticipation; Represent leading 1 prediction) in the prediction field ask for formula, wherein if T _i=1, be illustrated under the situation of not considering the low level carry, two binary operations count two binary numbers on the i position and be 1, and do not produce carry to a high position, promptly the value of last two the binary operation numbers in i position is 1,0 or 0,1; If Z _i=1, be illustrated under the situation of not considering the low level carry, two binary operations count two numbers on the i position and be 0, and do not produce carry to a high position, promptly the value of last two the binary operation numbers in i position is 0; If G _i=1, be illustrated under the situation of not considering the low level carry, two binary operations count two numbers on the i position and be 0; And produce carry to a high position; The value that is last two the binary operation numbers in i position is 1, and therefore on the i position, the situation of two binary operation numerical value can only make T _i, Z _i, G _iThe value of 1 parameter in three parameters is 1; And the value that makes a parameter at least is 1; What the LZA of two separations and LOA obtained predicts the outcome, be used to from totalizer and the most significant digit carry select: if most significant digit produces carry, explain and for just; Then need to predict that to leading 0 selection LZA predicts the outcome; If most significant digit does not produce carry, explain and be negative, then need predict leading 1, select predicting the outcome of LOA;

2) leading 0, the 1 prediction error correction unit of high speed

Because on the i position, the situation of two binary operation numerical value can only let T _i, Z _i, G _iThe value of 1 parameter in three parameters is 1, and to make the value of a parameter at least be 1, therefore is this characteristic of parameter tags of 1 for this position use value---T on the i position even _iValue be 1, then this moment Z _i, G _iValue be 0, therefore on the i position of prediction field, write T, all values is that 1 parameter constitutes on its corresponding position and predicts field; No matter for LZA or LOA; Have only in the prediction field, T*GZ* or T*ZG* section follow hard on T at the back, just need the n-1 of output be revised; Here T* representes that T has m T, wherein m>=0 at the back; Z* representes that Z has m Z, wherein m>=0 at the back; G* representes that G has m G at the back; M>=0 wherein; In order to judge whether to revise to output, need make judgement to the n position in the prediction field, utilize the LZC (abbreviation of Leading Zero Count; Represent leading 0 counting) with the LOC output L of (abbreviation of Leading One Count representes that leading 1 counts) _iThe T signal is handled, and is judged, have through result:

Wherein, for leading 0 prediction, have:

Have for leading 1 prediction:

F _iBe f _jFrom the 0th step-by-step or operation to the i position;

F _iHave following characteristics:

There is a definite n, makes for the F of i＜n arbitrarily _iBe 0, all the other F _iBe 1, any f for j＜n is promptly arranged _j=0, adopt " big end order " here, F _iWord string as a result for LZA/LOA output;

L _iHave following characteristics:

N for confirming has L _n=1, all the other L _i=0, for LZC/LOC not by the output of error correction;

Ask the method for judging enable signal EN;

en _i＝L _i·T _i+1 (23)

EN＝∑en _i (24)

A and B are two addends, and EN is en _iStep-by-step or result, EN is as the enable signal that whether need revise judgement to predicting the outcome;

N for confirming has L _n=1, at this moment have only T _N+1=1 o'clock, just need whether need revise and judge, be i.e. en the result _nJust possibly need in=1 o'clock to revise, EN is the single enable signal that en is compressed into;

If EN=0 need not to revise the output result, also just need not to judge whether to revise;

If during EN=1, need whether revise the result and judge, judge whether and to do correction to output n-1 that the n+1 position of promptly known prediction field is T, predicts so whether the n+1 position of field exists carry signal C _n, if T _n=1, then only need to judge carry signal C _nValue, for this reason, introduce a new internal signal K, it is defined as:

K ₀＝0 (25)

K _i＝T _i-1G _i，i≥1 (26)

If K _m=1, m＞n, and K _i≠ 1 (n＜i＜m), as long as then there is T _i≠ 1 (n＜i＜m) just can judge C _nValue must be 0, K handles as follows to field:

For leading 0 predicted portions, utilize LZC to produce signal F field K handled:

K′ _i＝K _i·F _i，i≥0 (28)

With method the T signal is handled:

More than two formulas be to be used for to K and signal the 1st to carry out zero clearing to the n position and handle; Then K ' is 0 field after the zero clearing of n position to the K field; K ' is handled; With K ' zero clearings later on all from the m position, 0 all puts 1 to the m-1 position:

T ', Q signal are carried out step-by-step and operation, promptly obtain to contain aiming field, and remainder are put 0 field entirely:

d _i＝T′ _i·Q _i，i≥0 (31)

D＝EN·∑d _i (32)

If D=1 then can not produce carry signal C _n, need revise for leading 0 prediction, be about to n and replace n-1 as prediction output result; For leading 1 prediction, need not to revise accordingly.

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