CN101697146B - Chip instruction and data pushing device of embedded processor - Google Patents
Chip instruction and data pushing device of embedded processor Download PDFInfo
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- CN101697146B CN101697146B CN200910218674.8A CN200910218674A CN101697146B CN 101697146 B CN101697146 B CN 101697146B CN 200910218674 A CN200910218674 A CN 200910218674A CN 101697146 B CN101697146 B CN 101697146B
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Abstract
The invention discloses a chip instruction and data pushing device of an embedded processor, which is used for solving the technical problem of high data flow in a bus of the prior art. The invention adopts the technical scheme that a pushing address storing and generating unit and a pushing time controlling unit are additionally arranged on a two-level mixed Cache terminal; an instruction pushing Buffer is additionally arranged on a one level instruction Cache terminal; and a data pushing Buffer is additionally arranged on a one-level data Cache terminal. Because of the pushing address storing and generating unit and the pushing time controlling unit, the instruction and data scheduling initiative is transferred from a high-level memory system to a low-level memory system; and because the low-level memory system can effectively dispatch accesses, the problem of access conflict of the one-level Cache is solved, and the one-level Cache is not required to send a large amount of access requests, and the data flow on a bus is reduced. The increase of the instruction pushing Buffer and the data pushing Buffer solves the problem of Cache pollution caused by pushing.
Description
Technical field
The present invention relates to a kind of instruction and data pusher, particularly flush bonding processor chip instruction and data push device.
Background technology
Document 2 " patent No. is the United States Patent (USP) of 7246205B2 " discloses the device of a kind of Cache of propelling movement, uses when this device can also can decide by the watch-dog credit value by the monitor system performance parameter to push the Cache operation.With reference to Fig. 5.This device is based on Cache hierarchical structure in the sheet of Harvard structure, comprise command unit, Load/Store unit, one-level instruction Cache, one-level Data Cache, disappearance formation, disappearance formation/write back formation, secondary mixed C ache, both there be not prefetching device not have pusher yet, in common processor, be widely used, for example Cortex-48 of AMD Opteron, ARM etc.But in this structure, because the hit rate of one-level Cache is lower, it is lower that the performance of entire process device and the processor that the device of looking ahead or pushing is arranged are compared performance.
With reference to Fig. 6.Document 3 " Improving Direct-Mapped Cache Performance by the Addition of a SmallFully-Associative Cache and Prefetch Buffers, 17
ThAnnual International Symposium on ComputerArchitecture, PP364-373,1990, ISBN:0-8186-2047-1 " a kind of prefetching device disclosed; and this device can make high-level storage system (one-level Cache) prefetched instruction and data from the low level storage system; improve the hit rate of one-level Cache, performance of processors is got a promotion.But this device causes the accessing operation of too much the carrying out of high-rise storage system to the low level storage system.In the storage system of Harvard structure, the conflict that this problem will cause too much one-level instruction and data Cache to visit secondary mixed C ache simultaneously reduces the ageing of data pre-fetching, and has increased the flow of data transmission on the bus.The ageing reduction of looking ahead causes the loss of processor performance, may offset the performance boost of looking ahead and bringing when this loss is serious.Fig. 6 has provided being used to of proposing in the document and has deposited the structure that the stream buffer of prefetch data is connected with Cache, and this structure can be eliminated the Cache pollution problem.But parallel together inquiry that be all provisional capitals when accessed of push buffer herein, and have only top line to be inquired about unlike stream buffer.The calculating of address is finished by the totalizer among the Stream Buffer in the document 3 in addition.
Summary of the invention
In order to overcome the big deficiency of data traffic on the prior art bus, the invention provides a kind of flush bonding processor chip instruction and data push device, utilize the free time of bus between one-level Cache and the second-level cache to push instruction and data in proper order to one-level Cache.Can improve hit rate, the raising system performance of one-level Cache as looking ahead, the influence that overcoming looks ahead brings, effectively reduce the possibility that one-level data and instruction Cache visit second-level cache simultaneously, improve the ageing of data pre-fetching, and can effectively reduce the flow of data on the bus.
The technical solution adopted for the present invention to solve the technical problems: a kind of flush bonding processor chip instruction and data push device, comprise command unit, the Load/Store unit, one-level instruction Cache, the one-level Data Cache, the formation of instruction disappearance, the formation of data disappearance, data write back formation and secondary mixed C ache, it is characterized in that: comprise that also pushing the address preserves and generation unit, propelling movement control module on opportunity, instruction pushes Buffer and data push Buffer, preserve described propelling movement address and generation unit comprises that instruction pushes address register, the data forward pushes address register and data back pushes address register, during the command unit instruction fetch address is sent to instruction simultaneously and push Buffer and one-level instruction Cache, when instruction propelling movement Buffer and one-level instruction Cache lack, the address is sent to secondary mixed C ache, and secondary mixed C ache passes to required instruction one-level instruction Cache and pushes address register with disappearance address update instruction; During Load/Store unit storage/access data the address sent to simultaneously data push Buffer and one-level Data Cache, when data push Buffer and one-level Data Cache all lack, the address is sent to secondary mixed C ache, the high priority data of being read is passed to the one-level Data Cache to secondary mixed C ache and more new data forward propelling movement address register and data back push address register simultaneously with the disappearance address, when bus was idle, secondary mixed C ache pushed instruction and data according to the address that pushes in address preservation and the generation unit respectively to instruction propelling movement Buffer and data push Buffer.
The invention has the beneficial effects as follows: preserve and generation unit owing to increased the propelling movement address at secondary mixed C ache end, propelling movement control module on opportunity, make the initiative of instruction and data scheduling transfer to the low level storage system by high-level storage system, because the low level storage system can better effectively be dispatched visit, solved the access conflict problem of one-level Cache, and do not need one-level Cache to send a large amount of request of access yet, reduced the flow of data on the bus.Instruction pushes the increase of Buffer and data push Buffer can eliminate the Cache pollution problem that propelling movement brings.
Below in conjunction with drawings and Examples the present invention is elaborated.
Description of drawings
Fig. 1 is the structured flowchart of flush bonding processor chip instruction of the present invention and data push device.
Fig. 2 pushes the address to preserve and the generation unit detail drawing among Fig. 1.
Fig. 3 pushes control module detail drawing on opportunity among Fig. 1.
Fig. 4 is the detail of construction that pushes Buffer among Fig. 1.
Fig. 5 is that prior art is based on Cache hierarchical chart in the sheet of Harvard structure.
Fig. 6 is Stream Buffer and a cache johning knot composition in the document 3.
Embodiment
With reference to Fig. 1～4, the present invention has adopted the pusher of instruction and data, comprise command unit, Load/Store unit, one-level instruction Cache, one-level Data Cache, disappearance formation, disappearance formation/write back formation, secondary mixed C ache, push the address preservation and generation unit, propelling movement control module on opportunity, instruction push Buffer and data push Buffer, preserve described propelling movement address and generation unit comprises that instruction pushes address register, the data forward pushes address register and data back propelling movement address register.Push address preservation and generation unit and be used to preserve and calculate the instruction of next needs propelling movement or the address of data.
It is as follows to have increased flowing to of these whole signals in device back:
When command unit needs reading command, simultaneously the address is sent to instruction and push Buffer and one-level instruction Cache.These two devices check whether hit respectively, and carry out data according to the replacement algorithm of introducing later and replace.If they all do not hit, one-level instruction Cache disappearance takes place so, the address is sent to secondary mixed C ache, secondary mixed C ache will carry out following process (data disappearance priority processing) simultaneously: 1, according to address read secondary mixed C ache, and the instruction of being read passed to one-level instruction Cache; 2, push address register with disappearance address update instruction.Each clock period all according to the address of instruction propelling movement address register, pushes instruction under the control of control module on the opportunity of propelling movement later on, till instruction propelling movement Buffer is full.
When the Load/Store unit need read and write data, the address is sent in data push Buffer and the one-level Data Cache simultaneously.These two devices check whether hit respectively, and carry out data according to the replacement algorithm of introducing later and replace.If they all do not hit, one-level Data Cache disappearance takes place so, the address is sent to secondary mixed C ache, and secondary mixed C ache will carry out following process simultaneously: 1 according to address read secondary mixed C ache, and the high priority data of being read is passed to the one-level Data Cache; More new data forward propelling movement address register and data back push address register simultaneously in 2 usefulness disappearance address.Later on each clock period all at first pushes address in the address register according to the data forward, propelling data under the control of control module on the opportunity of propelling movement, and it is full to push Buffer up to forward data; According to the address in the data back propelling movement address register, propelling data under the control of control module on the opportunity of propelling movement pushes Buffer completely up to reverse data then.
Instruction pushes address register: structure such as Fig. 2 (a), the address of the dos command line DOS that this register holds next one will push, if one-level instruction Cache does not lack, the instruction of every propelling movement delegation, the address adds 1, if one-level instruction Cache lacks, the value of this register adds 1 for the row address of disappearance instruction.
The data forward pushes address register: structure such as Fig. 2 (b), the row address that this register holds next one will push according to address increase mode, if the one-level Data Cache does not lack, every propelling movement data line, this address adds 1, if the one-level Data Cache lacks, the value of this register is that the row address of missing data adds 1.
Data back pushes address register: structure such as Fig. 2 (c), the row address that this register holds next one will push according to address minimizing mode, if the one-level Data Cache does not lack, every propelling movement data line, this address decrement, if the one-level Data Cache lacks, the value of this register is that the row address of missing data subtracts 1.
The effect of propelling movement control module on opportunity is the opportunity that the decision instruction and data pushes.Because the propelling movement of instruction and data must be able to not influence the request of normal instruction and data, so must guaranteeing to push, this unit occurs in bus in the time of the free time, and one-level instruction this moment Cache is to the request of reading of secondary mixed C ache, and the one-level Data Cache is not to the read-write requests of secondary mixed C ache.The concrete opportunity that pushes is as follows:
(a) when finding that increasing data push Buffer according to the address does not have the disappearance formation of full and one-level instruction Cache and one-level Data Cache for empty, the formation that writes back of one-level Data Cache also is that the address that pushes in the address register according to the data forward pushes under the situation of sky.
(b) if find that then reducing data push Buffer according to the address does not have the disappearance formation of full and one-level instruction Cache and one-level Data Cache for empty, the formation that writes back of one-level Data Cache also is that the address that pushes in the address register according to data back pushes under the situation of sky.
(c) if last discovery instructs propelling movement Buffer not expire and the disappearance formation of one-level instruction Cache and one-level Data Cache is a sky, the formation that writes back of one-level Data Cache also is under the situation of sky, according to instructing the address that pushes in the address register to push.
Just can guarantee that by such judgement the propelling movement of data is to carry out when bus is idle between one-level instruction Cache and one-level Data Cache and secondary mixed C ache with priority, and the priority that pushes is following to be increased propelling data, secondly is to reduce propelling data according to the address according to the address at first, is to push instruction at last.
For fear of the Cache pollution problem that brings by propelling movement, increase instruction at one-level instruction Cache end and pushed Buffer, increased data push Buffer at one-level Data Cache end.Data push Buffer logically has been divided into two parts again, and a part is deposited according to address increase mode and pushed next data, and another part is deposited according to address minimizing mode and pushed next data.Push structure such as Fig. 3 of Buffer, each row comprises three parts:
Label: the row address of storing this line data.
Significance bit: show whether this line data is effective.
Data: store the data that Cache is capable.
After having increased instruction propelling movement Buffer and data push Buffer, visit one-level Cache and the corresponding Buffer of propelling movement that processor core visit one-level Cache need walk abreast.If they have one to hit then in telling the fortune, just calculate in all losing one's life and lack.Be to push the label of Buffer in capable with the row address of data and all to compare simultaneously when processor access pushes Buffer in addition, to determine desired data or to instruct whether in propelling movement Buffer.It is as follows to push Buffer and corresponding C ache replacement policy:
If ● the instruction of being got (data) pushes among the Buffer in instruction (data) and hits, and the words in losing one's life in cache: the Block that hits that instruction (data) pushes among the Buffer replaces into cache, and removes this Block piece that pushes among the Buffer;
If ● the instruction of being got (data) is hit the words of also hitting in cache in pushing Buffer: it is invalid to put the Block that hits in pushing Buffer;
If ● the instruction of being got (data) lacks in pushing Buffer, the words that also lack in cache: all row that push among the Buffer are eliminated, (both sides, front and back) begin to push behind the disappearance address, the Block of disappearance should be skipped in this place, because this piece is that one-level cache is to the normal request block of secondary cache;
If ● the instruction of being got (data) lacks the words of hitting in cache in pushing Buffer: push data no change among the Buffer.
The workflow of flush bonding processor chip instruction and data push device is as follows:
(a) whether bus is idle between detection one-level Cache and the secondary mixed C ache; Whether the disappearance formation that detects one-level instruction Cache is empty; Whether the formation that writes back that detects the one-level Data Cache is empty.If above three conditions all satisfy, forward step (b) to, otherwise re-execute step (a).
Whether (b) detect forward data propelling movement Buffer expires.If not full, forward step (c) to, otherwise forward step (d) to.
(c) according to the address in the forward data propelling movement address register, from secondary mixed C ache, fetch data, and the data push of getting is pushed among the Buffer to forward data.Forward step (a) then to.
Whether (d) detect reverse data propelling movement Buffer expires.If not full, forward step (e) to, otherwise forward step (f) to.
(e) according to the address in the reverse data propelling movement address register, from secondary mixed C ache, fetch data, and the data push of getting is pushed among the Buffer to reverse data.Forward step (a) then to.
Whether (f) detect instruction propelling movement Buffer expires.If not full, forward step (g) to, otherwise forward step (a) to.
According to the address in the instruction propelling movement address register, from secondary mixed C ache, fetch data, and the data push of getting is pushed among the Buffer to instruction.Forward step (a) then to.
Owing to use the device that pushes, can increase the hit rate of one-level instruction Cache and one-level Data Cache, this just can reduce one-level instruction Cache and the one-level Data Cache request of access to secondary mixed C ache, increased the time of bus free time, that is to say that more time can be used for the propelling movement of data and instruction.
Claims (1)
1. flush bonding processor chip instruction and data push device, comprise command unit, get/deposit receipt unit, the one-level instruction cache, the one-level data cache, the formation of instruction disappearance, the formation of data disappearance, data write back formation and secondary hybrid cache, it is characterized in that: comprise that also pushing the address preserves and generation unit, propelling movement control module on opportunity, instruction pushes impact damper and data push impact damper, preserve described propelling movement address and generation unit comprises that instruction pushes address register, the data forward pushes address register and data back pushes address register, during the command unit instruction fetch address is sent to instruction simultaneously and push impact damper and one-level instruction cache, when instruction propelling movement impact damper and one-level instruction cache all lack, the address is sent to the secondary hybrid cache, and the secondary hybrid cache passes to required instruction the one-level instruction cache and pushes address register with disappearance address update instruction; Get/address is sent to data push impact damper and one-level data cache simultaneously during deposit receipt unit storage/access data, when data push impact damper and one-level data cache all lack, the address is sent to the secondary hybrid cache, the high priority data of being read is passed to the one-level data cache to the secondary hybrid cache and more new data forward propelling movement address register and data back push address register simultaneously with the disappearance address, when bus was idle, the secondary hybrid cache pushed instruction and data according to the address that pushes in address preservation and the generation unit respectively to instruction propelling movement impact damper and data push impact damper;
Data push is as follows opportunity:
There is not the disappearance formation of full and one-level instruction cache and one-level data cache for empty when increase the data push impact damper according to the address, the one-level data cache write back formation also when empty, the address that pushes in the address register according to the data forward pushes;
When finding that reducing the data push impact damper according to the address does not have the disappearance formation of full and one-level instruction cache and one-level data cache for empty, the one-level data cache write back formation also when empty, the address that pushes in the address register according to data back pushes;
When finding that instruction pushes full and disappearance formation one-level instruction cache and one-level data cache of impact damper with ing be empty, the one-level data cache write back formation also when empty, according to instructing the address in the propelling movement address register to push.
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| CN106201913A (en) * | 2015-04-23 | 2016-12-07 | 上海芯豪微电子有限公司 | A kind of processor system pushed based on instruction and method |
| CN113934653B (en) * | 2021-09-15 | 2023-08-18 | 合肥大唐存储科技有限公司 | Cache implementation method and device of embedded system |
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