CN101689401A - Nano-vacuum-tubes and their application in storage devices - Google Patents

Nano-vacuum-tubes and their application in storage devices Download PDF

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Publication number
CN101689401A
CN101689401A CN200780053672A CN200780053672A CN101689401A CN 101689401 A CN101689401 A CN 101689401A CN 200780053672 A CN200780053672 A CN 200780053672A CN 200780053672 A CN200780053672 A CN 200780053672A CN 101689401 A CN101689401 A CN 101689401A
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member according
substrate
groove
conductors
electron emitting
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D·R·谢泼德
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Kyosemi Corp
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Kyosemi Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/005—Arrangements for writing information into, or reading information out from, a digital store with combined beam-and individual cell access
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/02—Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

Abstract

The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.

Description

Nano-vacuum-tubes and its application in memory storage
Technical field
[0001] the present invention relates to the information stores array, and relate in particular to the storage array that forms by matrix such as the non-linear electric installation of diode or triode.
Background technology
[0002] the diode array memory storage is one of simple form of data storage device.Yet the problem that the diode array memory storage exists is when the size raising of array, and the quantity that is connected to the not addressing diode between the column or row of not addressing of the given selected row or column of array and array also becomes very many.Although the leakage current of the diode of addressing is very not little to the influence of device operation by on selected row or column any one, by several thousand not the accumulation of the diode of addressing leak electricity and can become quite big.The leakage current of this total can become enough big so that output voltage or electric current or electric charge change, thereby makes the threshold value that is used for distinguishing between 1 attitude of the diode location of institute's addressing and 0 attitude thicken and cause misreading the diode location of institute's addressing.In addition, when array is scaled when being more and more littler geometry, semiconductor structure becomes a limiting factor, and this is because the layer of semiconductor material must keep enough thick in to control reverse leakage current; Yet, for further this thickness of ratio of reduction means is also had to reduce to adapt to so scaled.
[0003] in the diode array memory storage, be listed as one of addressing by selecting to run through the delegation of array and running through one of array, described selected row or column is intersected at institute rheme place.Another array dimension that the negative electrode that array dimension that if row is the anode of storage diode to be connected and row are storage diode connects, then realize to the selection of row and by the selection of selection low-voltage realization, thereby the diode that is positioned at the place, point of crossing of selected row and selected row is a forward bias row by applying high voltage.Unselected row and column presents the diode that makes at the infall of unselected row and unselected row and has zero offset, reverse bias or very little forward biased voltage; Usually, the source electrode of unselected row and column is high impedance or floats, thereby do not cause or cause significant leakage current.If the binary condition of the position of institute's addressing by whether existing current path to determine-exist the low impedance current path then represent a logic state, if there is no (does not perhaps have current path or is the high impedance current path) then to represent another logic state.Can read this position at output by following operation: the electric current that measure to flow into selected line, alignment or this both part of whole array or this array (or flow into), or by measuring, or by extracting and measure at selected line, alignment or this residual charge on both at selected line, alignment or this voltage on both.In the situation of current measurement, the reading of big electric current indicates in the position of institute's addressing and has nonlinear conductor.In the situation of voltage measurement, the convergence that is applied to the voltage of selected row and selected row indicates in the position of institute's addressing and has nonlinear conductor, with in the situation of charge-extraction, less residual charge indicates in the position of institute's addressing and has nonlinear conductor.
[0004] must be noted that, the diode that it is unexpected connection that common selected row has many its addressing, and these diodes experience small forward bias usually and provide small forward current to unselected row.Similarly, the diode that it is unexpected connection that selected row have many its addressing usually, and these diodes experience small forward bias usually and suck small forward current from unselected row.The size of this electric current is determined by the current path that the leakage current owing to the accumulation of the many back-biased diodes that connect unselected row and unselected row is present in the array.Minimize in order to make to leak, these diodes are made with a plurality of semiconductor material layers usually, and the some of them layer is made thicker depletion region with the knot that enlarges device and reduces leakage current.When array hour, the leakage current of accumulation is not a problem.But when array was very big, the leakage current of accumulation can become enough big so that the electric current that flows in the diode of selected row and the selected not addressing that lists can become suitable with the electric current that should flow in the diode (if it exists) of institute's addressing.Because the electric current that leaks in this mode is to be stored in the function of the data in the array and reading arbitrary function that this leakage rate can be different when giving the location, so be difficult to prediction or compensate this leakage.The binary condition of the position of the very difficult institute's addressing that maybe can not determine the reason of current path and bring thus when this feasible leakage current when accumulation becomes excessive.In most of the cases, array can be divided into a plurality of subarrays, but when each subarray becomes big, this problem be arranged equally.
Summary of the invention
[0005] the present invention helps reducing the ratio of the device in the diode array memory storage and reducing cost.Generally speaking, this is by adopting the device based on field emission body, diode or triode for example, but not the diode of based semiconductor is realized.Technology according to the present invention has the technology manufacturing step still less than based semiconductor material, obtains economic advantages thus.Contemplated field emission body is similar to the classical vacuum tube device that is called diode, and it is in one direction than two electrodes (diode) non-linear device of the easier conducting electric current of another direction.The invention provides all types of diode arrays or comprise the enhancing of array of other non-linear conducting elements of memory storage, programmable logical unit, array of display, sensor array and many other devices.The present invention also comprises the method that is used to make field emission body at these or other purpose in semiconductor production line.
[0006] in an embodiment, the invention is characterized in a kind of member, this member is included in more than first and second conductors (for example lead) that overlap that each place, point of crossing limits bank bit, and a plurality of non-linear electron emitting devices, wherein each device is disposed in the place, point of crossing between these more than first and second conductors.Each of this non-linear electron emitting device can be cold emission device or field emission apparatus.In an embodiment, each device comprises cavity, and it can comprise vacuum, at least a inert gas, or at least a phosphor material.
[0007] embodiments of the invention can comprise following feature.This member can comprise the addressing circuit of selecting described more than first and second conductors conductor in each in the two.This addressing circuit can comprise first array of non-linear electron emitting device.This member can comprise output detection circuit, and whether its detection exists a device in the position by the selected bank bit of this addressing circuit.This output detection circuit can comprise second array of non-linear electron emitting device.Each bank bit comprises the material layer that can show at least two discrete impedance level, and this material can comprise at least a meltable material, non-meltable material, magnetic material and/or such as the phase-change material of chalcogenide.These more than first and second conductors are disposed in encapsulation separation, industrial standard, and this encapsulation can have or be removable form factor.This encapsulation can also additionally comprise at least one logical unit, for example controller.This encapsulation can be included in more than third and fourth the overlapping conductor (for example lead) that each place, point of crossing limits bank bit.These more than first and second conductors can be disposed in display device or the programmable logic array.These more than first and second conductors can be disposed on the substrate, and these a plurality of non-linear electron emitting devices can be in emitting electrons on the direction of this substrate.Each of these a plurality of non-linear electron emitting devices can comprise the emitter tip.The emitter tip of at least one of these a plurality of non-linear electron emitting devices can be melted, and therefore causes this non-linear electron emitting device inoperative.
[0008] in yet another aspect, the present invention includes a kind of method, this method comprises by following steps and is forming a plurality of non-linear electron emitting devices on the substrate: form more than first groove in the top surface at this substrate, on whole this substrate, form emitter layer of tip material (wherein the first of this layer be disposed on this more than first groove and the second portion of this layer is disposed in this more than first groove), and the first that removes this emitter layer of tip material.This first that removes this emitter layer of tip material comprises complanation.Forming this more than first groove can may further comprise the steps: form mask layer on whole this substrate, remove the part of this mask layer in more than first zone, and etch away the substrate in this more than first zone.In different embodiment, form this top surface that this more than first groove can comprise impression, embossing or this substrate of injection moulding.In other embodiment, this method is included in the top surface of this substrate and forms more than second groove, and after removing this first of this emitter layer of tip material, this more than second groove all do not have the emitter tip materials basically.The degree of depth of this more than second groove can be less than the degree of depth of this more than first groove.
Description of drawings
[0009] Fig. 1 illustrates the substrate with three layers of topographic profile;
[0010] Fig. 2 has illustrated by the substrate after the bottom metal deposition of conformal coating;
[0011] substrate after Fig. 3 has illustrated the deposition initial film to pile up;
[0012] Fig. 4 has illustrated the substrate after first complanation;
[0013] Fig. 5 has illustrated the substrate after the etching;
[0014] Fig. 6 has illustrated the substrate behind the deposition filling material material;
[0015] Fig. 7 has illustrated the substrate after second complanation;
[0016] Fig. 8 has illustrated deposition top metal and carry out substrate behind the patterning by photoetching process;
[0017] Fig. 9 illustrated to be used for the dielectric undercutting and the wet-chemical chamber that removes after substrate;
[0018] Figure 10 has illustrated the substrate behind the sealing nano-vacuum-tubes;
[0019] Figure 11 has illustrated the substrate after the passivation;
[0020] Figure 12 has illustrated to be used for a kind of possible circuit of diode decoding storage.
Embodiment
[0021] usually, diode storage array comprises two groups of wirings, arranges in a plane that vertically (row) and another group are flatly another floor plan (OK) for one group.The point place that intersects in arbitrary given row and column wiring is addressable data bit.Interlaced simply and do not connect the electric pathway (or having high impedance path) of this row and column at place, this point of crossing if connect up, then this is restricted in two logic states one, and if have the Low ESR electric pathway, then be another logic state.For can being addressed separately, these data bit (do not have electric current to flow through row/row junction arrival row from the row of for example energising, and another row/row junction of flowing through subsequently arrives second row, give working except desired row thus), use diode or some other nonlinear conductors to form connection between row and columns (this can make electric current flow to row but not be back to it from row can make position of another electricity that works) such as triode.For the purpose of this discussion, should think that lacking conductive path is 0 and to have conductive path (diode or other devices) be 1.
[0022] in the diode array memory storage, come position of addressing by row selecting to run through a row of this array and run through this array, wherein said selected row and column is in this place, position intersection.Another array dimension that the negative electrode that array dimension that if row is the anode of storage diode to be connected and row are storage diode connects, then realize being forward bias so that be positioned at the diode at the place, point of crossing of selected row and selected row to the selection of row and by selecting the selection of low-voltage realization to row by applying high voltage.Unselected row and column will present the diode that makes at the infall of unselected row and unselected row and obtain zero offset, reverse bias or very little forward biased voltage; Usually, the source electrode of unselected row and column is high impedance or floats, thereby do not cause or cause significant leakage current.If the binary condition of the position of institute's addressing by whether existing current path to determine-exist the low impedance current path then represent a logic state, if there is no (does not perhaps have current path or is the high impedance current path) then to represent another logic state.Electric current by measure flowing into selected line, alignment or this both part of whole array or this array (or flow into) or by measuring at selected line, alignment or the voltage on both can read this position in output place.In the situation of current measurement, big current indication indicates in the position of institute's addressing and has current path.In the situation of voltage measurement, the convergence that is applied to the voltage of selected row or selected row indicates in the position of institute's addressing and has current path.Specifically referring to United States Patent (USP) 5,673,218, this patent is in the middle of this is included in the present invention by reference for the detailed description of the embodiment of operation diode array memory storage.In addition, for based on the description of the diode array memory storage of electric charge referring to U.S. Provisional Patent Application 60/787,247.
[0023] in an embodiment, the present invention makes by the technology that employing has the substrate surface topographic profile of a plurality of depths of features.The specific explanations of this technology is disclosed in United States Patent (USP) 6,586,327, and it comprises in the present invention by reference.Specifically, as shown in Figure 1, for preferred embodiment of the present invention, substrate 100 comprises three layers topographic profile; That is to say that this topographic profile also comprises a plurality of features except that the surface, each feature has one of three different possible degree of depth.The most shallow feature 101 will produce the through hole that connects metal layer at top and bottom metal layers.Inferior dark feature 102 will produce the bottom metal conductor and comprise by the top metal conductor across on the bottom metal conductor and do not have the situation that connects.The darkest feature 103 will produce field emission apparatus (for example micron order or nano level two-electrode vacuum tube).
[0024] Fig. 2 has illustrated the substrate 100 behind the conformal deposited bottom metal material 110.Should be noted that in each feature of topographic profile,, reduced the width of the opening of this feature by coating material on the sidewall of those features.
[0025] substrate 100 after Fig. 3 shows deposited film and piles up, it comprises that bottom metal 110 is as its initiation layer (noting can providing a material thin-layer to adhere to or as unshowned material transition restraining barrier herein to help lend some impetus to, for example one of known many other materials of the those of ordinary skill of titanium or field of manufacturing semiconductor devices) before bottom layer 110 or arbitrary independent layer.In this membrane stack is such as chromium (Cr) or nickel (Ni) or sapphire (Al 2O 3) spacer material 112, its opposing back plasma etching or reactive ion etching (RIE).In order to prevent to cause to be difficult to carry out the formation of the alloy of back processing step, can between bottom metal 110 and corrosion-resistant material 112, deposit cushioned material layer.It is most advanced and sophisticated and can be to be convenient to the electronics emission better such as the corrosion resistant metal of nickel (Ni) or some materials with low work function that material layer 113 can be selected as being used to form field emission body, or this material layer can be a series of materials, the material of for example thin low work function such as germanium (Ge) then is thicker nickel dam (enough thick in filling sedimentary deposit 112 formed spaces).
[0026] Fig. 4 has illustrated the substrate 100 after the complanation.Bottom metal layers 110, spacer material 112 and emitter tip materials 113 all are exposed to the place that the plane of complanation cuts off this membrane stack.It should be noted that the material of corrosion-resistant material 112 protection under it, but but the bottom metal material 110 of the side that is exposed to this corrosion-resistant material of etching will be exposed under the etching that next will carry out and will remove this material.
[0027] Fig. 5 has illustrated the result of this etch step.No matter where corrosion-resistant material 112 is present in, material 110 thereunder is with protected direction-sense (anisotropy) etching of avoiding.But the etch material that exposes is etched away and stays opening 120, but has wherein removed those etch material.Notice that substrate 100 is less than be etched with etch material but (or being etched slowlyer).This can be by making a kind of material (for example PMMA or other plastics) substrate or on substrate, be coated with application layer (Al for example before at deposition first film (110) 2O 3) realize that wherein this substrate optionally is not etched when etching other materials 110.
[0028] another kind of possible combination of materials is that tungsten (W) is used for bottom metal 110, aluminium oxide (Al 2O 3) be used for spacer material 112, and aluminium (Al) is used for emitter tip materials 113.Can be used for etching W and its etching PMMA substrate 100 more lentamente based on the RIE etching of fluorine.The wet etching of spacer material 112 removes and can realize by the wet etching that is immersed in the hydrofluorite (HF).The degree of depth of feature and the thickness of film make the degree of depth of the most shallow feature 101 should be more shallow slightly than the thickness of bottom metal 110.The feature 102 of intermediate depth should add that half of thickness of spacer material 112 is more shallow slightly to 3/4ths than the thickness of bottom metal 110.The degree of depth of the darkest feature is the thickness of bottom metal 110, spacer material 112, the function of the shape of the width of dark feature and desired field emission body, but this degree of depth should equal the desired length of field emission body axle usually adds that bottom metal 110 adds the thickness of spacer material 112, and the width of the darkest feature desired width that should equal this emission axon usually add the thickness of bottom metal 110 twice, add the twice of the thickness of spacer material 112.The THICKNESS CONTROL field emission body gap of spacer material 112.Notice, the size and dimension of field emission body can be when being filled in the pit 103 when spacer material this material crowd around and the space that forms is determined from the opposite side of pit 103.Similarly the space form mechanism be the those of ordinary skill in semiconductor manufacturing (especially DRAM makes) field known and its be associated with " keyhole (keyhole) " effect, " bird's eye " effect etc.
[0029] Fig. 6 illustrates the substrate 100 that has deposited behind the non-conductive filling material material 114.This material helps the structure upper support top metal wires in the step and help the sealed vacuum chamber in the back, and helps potentially to prevent that material is discharged into gas in the emission body cavity from substrate 100.
[0030] Fig. 7 shows second planarization steps substrate 100 afterwards.This complanation must be exposed to the bottom metal 110 at the most shallow feature place so that the electrical connection between bottom metal 110 and the top metal (also will be deposited).This complanation also must expose to the contact of field emission body 130 at the darkest feature place, so that the electrical connection between field emission body 130 and the top metal.
[0031] Fig. 8 has illustrated to form top metal alignment 116 substrate 100 afterwards.These alignments 116 are by deposition top metal material (for example W or Mo, only lift a few and be example) and carry out patterning (as adopting photoetching or imprint lithography composition and etching, or other technologies finish, and these those of ordinary skill for field of semiconductor manufacture are known) form.
[0032] Fig. 9 illustrated the spacer undercutting and remove after substrate 100.This undercutting is carried out by wet etching, but may carry out by angled plasma etching or RIE etching.The top metal alignment is supported by the substrate and the filling material material 114 at point 132 places, and wherein alignment is fixed against these materials.Alignment also supports and is electrically connected to this bottom metal row 131 by the bottom metal row 131 at 134 places, position of the most shallow feature 101.On the other hand, across on bottom metal row 131, wherein there is the gap in top metal row 116 owing to removing spacer material 112 at 133 places, position.At last, bottom metal row 131 form at the some place of the darkest feature cup shell 135 and with field emission body 130 complementations, this field emission body 130 is suspended on these cup shells by its connection to the bottom of top metal row 116.As seeing from accompanying drawing, the gap of these field emission bodies is determined by the thickness of spacer material usually.In this structure, field emission body 130 is to substrate 100 emitting electrons.
[0033] as shown in figure 10, in order to realize the embodiment of a vacuum tube structure, the dielectric confining bed 140 of deposition in such as the non-conformal deposition process of electron beam vacuum evaporation.The non-conformal nature of this deposition process causes closed material partly to be filled in the sidepiece 136 of nano-vacuum-tubes and is not filled in gap between field emission body 130 and the cup shell 135; The depositing operation of this high vacuum also is created in the vacuum that obtains in the field emission body of sealing and the cup shell, is used to form real vacuum tube.In order to strengthen confining bed 140 and to protect this device better, on entire substrate, deposited passivation layer 141 as shown in figure 11.Should notice packing material 114 is how to help the sealed vacuum chamber and help potentially to prevent that material is discharged into gas in the emission body cavity from substrate 100.
[0034] Figure 12 show can be constructed according to the invention as United States Patent (USP) 5,673, the memory circuit 200 of disclosed diode decoding in 218.Memory circuit 200 comprises a plurality of non-linear electron emitting devices 210, and it is in the existence of the position of bank bit or do not exist and represent 1 or 0 respectively.The storage bit position is limited by the point of crossing of two groups of conductors that overlap mutually (for example lead).This conductor can comprise the semiconductor of metal for example or doping or be made up of these basically.Each of a plurality of non-linear electron emitting devices 210 can be aforesaid diode or as triode to be discussed below.Memory circuit 200 can comprise addressing circuit, and it selects to store bit position by the wiring that is chosen in the specific location intersection.Such addressing circuit itself can comprise the array such as the non-linear electron emitting device of diode or triode.Memory circuit 200 can also comprise output detection circuit, and it detects non-linear electron emitting device and whether is present in position by the selected bank bit of addressing circuit.Such output detection circuit can comprise the array such as the non-linear electron emitting device of diode or triode.
[0035] as a kind of variation, expectation comes with this desired gas (for example argon gas) sealed vacuum pipe by the environment deposit confining bed at the gas of expecting.For example sputtering chamber can have the low-pressure air current of argon gas during the sputter dielectric, and this causes collecting in field emission body and the cup-shaped cavity argon gas.
[0036] in some cases, nano-vacuum-tubes described herein is called the cold-cathode field emitter.Can adopt various materials to make according to nano-vacuum-tubes of the present invention.Many these materials together with they etching combination and select to be for the those of ordinary skill institute well-known of these different field and to know.Other materials of not inventing as yet also are available for use according to the present invention.Emission is subjected to distance between (except that others) most advanced and sophisticated radius, this tip (negative electrode) and the relative terminal (anode) and the work function of this tip materials influences from the electronics at field emission body tip.Confirmed that many materials can be used for efficiently an emission, they comprise adamas (the CVD deposition), zirconium carbide (ZrC), aluminium nitride and other (LaB for example 6).These and other material is selected to be because their low work function, low or negative electron affinity and they can be suitable for existing technology.Especially when considering the situation of wet etching, a bit be a problem after this.For example, if coating material is joined in the technology, usually it just deposited as thin layer before deposition emitter tip materials.During the RIE etching, this coating material on emitter tip materials protection (shield) its basal surface, but also select this coating to be because it has the ability of opposing in order to the wet etch step of removing spacer material.Another problem that will consider is to be added in the coating of the high work function material on the anode surface to reduce reverse leakage current.This anode coating can just deposit as thin layer after deposition bottom metal material.During the RIE etching, the anode coating material will be to have the ability of opposing in order to the wet etch step of removing spacer material because of it but also select this coating owing to emitter utmost point coating protected (shield).
[0037] in addition bigger bit density, can make the present invention among 757 the 3-D according to United States Patent (USP) 6,956, this patent is in the middle of this is included in the present invention by reference.
[0038] make the gate field emitter also within the scope of the invention, this field emission body is similar transistorized triode.These can utilize through-hole structure to form and can be used to realize the function and the design of other storeies and circuit around field emission body.Being connected all of bottom metal and top metal can be entering the field emission body structure by decussate texture 133 vertical separated modes from the same side, as (in case in this case as long as this top metal is arranged to and is away from these three terminal structures variations and will be supported by substrate) like that of being realized during across bottom metal at the situation next top metal that does not have to connect; This field emission body of parcel on all sides except the side that top and bottom metal enter, the top metal that is connected in bottom metal (through hole 134) around this field emission body with the 3rd terminal (grid) that is formed into device and the anode (first terminal) that keeps the 3rd terminal electricity to be isolated from being connected in field emission body and the top and the bottom metal of negative electrode (second terminal).
[0039] the present invention can be applied to make programmable, ROM (read-only memory) (ROM), disposable programmable ROM (read-only memory) (OTPROM) and read/writable memory device (MRWM) repeatedly.OTPROM can realize that the selection of many materials wherein openly still has many materials to be invented in the prior art by the material that just deposited melting or non-melt before deposition field emission body metal.OTPROM can also realize by the position that writes data to institute's addressing with the high voltage that is enough to cause generation electric arc between tip 130 and cup-shaped cavity 135; Such electric arc can cause most advanced and sophisticated fusing (prior art can be discerned not only and to be emitter tip materials that is fit to but also molten metal under electric arc easily) and such destructiveness fusing will cause most advanced and sophisticated and whole non-linear device inoperative (promptly from that bit position elimination non-linear device).MRWM can realize that the selection of many materials wherein is open in the prior art and still have many materials to be invented by comprising the material that can change its resistivity or electric conductivity (being impedance) between two or more states.The MRWM material can be used as the extra play that just deposited and is included in the structure before the top metal material, obtain the MRWM layer between top metal and emitter tip thus.Comprise such as phase-change material (referring to the United States Patent (USP) 4 of Ovshinsky, 646, No. 266), the material of organic material (referring to No. 6,236,587, the United States Patent (USP) of Gudesen), magnetic ram (MRAM) unit be (referring to the United States Patent (USP) 5 of Gallagher, 640, No. 343) or molecular transistors or switch (referring to No. 6,559,468, the United States Patent (USP) of Kuekes and the United States Patent (USP) 6 of Heath, 459, No. 095) the storage unit of material also for being fit to.The patent documentation of Ovshinsky, Gudesen, Gallagher, Kuekes and Heath is included among the present invention by quoting in full at this.These and other materials are those of ordinary skill institute's well-known of these different field and know.Other materials that do not invent as yet also are available for use according to the present invention.
[0040] the present invention also is suitable for as the manufacturing technology based on topographic profile lithographic, as Shepard at United States Patent (USP) 6,586, disclosed in No. 327, this patent is in the middle of this is included in the present invention by reference, and the description of above preferred embodiment can further be passed through to form the top metal row conductor as the initial topographic profile of disclosed basis in this patent, rather than photoetching technique is enhanced.In addition, the described herein substrate that has topographic profile on it can form by conventional lithography and etching, electron beam lithography and etching, nano-imprint lithography and etching or electron beam abrasion, in case and at least one substrate is available (having the topographic profile of making by one of preceding method or any other method on this substrate), other substrates that have topographic profile on it can pass through formation such as embossing, impression (UV or heat), injection moulding.The distortion that top metal forms comprises: adopt imprint lithography with form the desired pattern that is positioned at groove wherein of top metal, to the removing of residual layer remove, the deposition of top metal material and inlay polishing to form the top metal pattern and other removing of any residual impression anticorrosive additive material is removed, this those of ordinary skill for the nano-imprint lithography field can be known.
[0041] the present invention can be applied to the other field except storer and information-storing device.The present invention can be used to realize programmable logic array (PLA), programmable logic device (PLD) (PLD) or display.Under the situation of display equipment, the cup shell 135 that is formed in the emitter characteristic can be coated with fluorescent material, or substitutes the field emission body in the sealing of vacuum lower seal, wherein collects fluorescence gas and make.Substrate can also be by making such as the transparent material of mouldable glass or plastics and bottom metal can be made by transparent material or other transparent conductors known to a person of ordinary skill in the art such as tin indium oxide (ITO).Alternately, the light that allows to be produced transmits and walks around the top metal conducting bridge that supports the field emission body tip.The gas with various of selecting because of its fluorescence color can be collected into different bit positions to realize color monitor.
[0042] device of being constructed according to the present invention can be applied to such a field: storage digital text, digital book, digital music, DAB, Digital photographic (wherein one or more digital stills can be stored as and comprise continuous digital picture), digital video and rendering of digital maps (wherein can store one or more numerical maps), their combination in any in addition.These devices can be embedded into or for removable or removable and exchange in device.They can be with the form factor of any kind of industrial standard that comprises compact flash card, secure digital storage card, multimedia storage card, pcmcia card, memory stick, with to comprise ball grid array, dual-in-line package (DIP ' s), SOICs, PLCC, any in a greater variety of integrated circuit encapsulation of TQFP ' s and analog, and encapsulate with the encapsulation of Custom Design.These encapsulation can only comprise storage chip, a plurality of storage chip, together with one or more storage chips of controller or other logical units or such as other memory storages of PLD ' s, PLA ' s, microcontroller, microprocessor, control chip or chipset or other customizations or preferred circuit.For example, in the encapsulation of holding a plurality of storage chips, this encapsulation can be included in more than third and fourth conductors (for example lead) that overlap that each place, point of crossing limits bank bit.
[0043] in order to illustrate and to describe, more than shown example and its modification to the preferred embodiments of the present invention.This not purport for being exhaustive or to limit the invention to disclosed clear and definite form.According to above instruction many modifications and variations is possible.Protection scope of the present invention is not intended to be subject to this specific descriptions, but is defined by the appended claims.

Claims (33)

1. member comprises:
More than first conductor;
With more than second conductor that this more than first conductor overlaps, wherein each place, point of crossing between these more than first and second conductors limits a bank bit; With
A plurality of non-linear electron emitting devices, wherein each device is disposed in the place, point of crossing between these more than first and second conductors.
2. member according to claim 1, wherein each of this non-linear electron emitting device is the cold emission device.
3. member according to claim 1, wherein each of this non-linear electron emitting device is a field emission apparatus.
4. member according to claim 1, wherein each of this non-linear electron emitting device comprises cavity.
5. member according to claim 1, wherein this cavity comprises vacuum.
6. member according to claim 5, wherein this cavity comprises at least a inert gas.
7. member according to claim 5, wherein this cavity comprises at least a phosphor material.
8. member according to claim 1 also comprises at least one the addressing circuit that is connected in these more than first and second conductors, and this addressing circuit is selected in these more than first and second conductors.
9. member according to claim 8, wherein this addressing circuit comprises first array of non-linear electron emitting device.
10. member according to claim 8, also comprise at least one the output detection circuit that is connected in these more than first and second conductors, this output detection circuit detects whether there is non-linear electronics emitting diode by the selected bank bit of this addressing circuit place.
11. member according to claim 10, wherein this output detection circuit comprises second array of non-linear electron emitting device.
12. member according to claim 1 also comprises the material layer that can show at least two discrete impedance level at each bank bit place.
13. member according to claim 12, wherein this material comprises at least a melting or non-melt material.
14. member according to claim 12, wherein this material comprises at least a phase-change material or magnetic material.
15. member according to claim 14, wherein this material comprises chalcogenide.
16. member according to claim 1, wherein these more than first and second conductors are disposed in the encapsulation of separation.
17. member according to claim 16, wherein this encapsulation has removable form factor.
18. member according to claim 16, wherein this encapsulation comprises at least one logical unit.
19. member according to claim 18, wherein this at least one logical unit comprises controller.
20. member according to claim 16 also comprises:
More than the 3rd conductor; With
With more than the 4th conductor that more than the 3rd conductor overlaps, wherein each place, point of crossing between this more than third and fourth conductor limits bank bit.
21. member according to claim 1, wherein these more than first and second conductors are disposed in the display equipment.
22. member according to claim 1, wherein these more than first and second conductors are disposed in the programmable logic array.
23. member according to claim 1, wherein these more than first and second conductors are disposed on the substrate, and these a plurality of non-linear electronics emitting diodes are in emitting electrons on the direction of this substrate.
24. member according to claim 1, wherein each in these a plurality of non-linear electron emitting devices comprises the emitter tip.
25. member according to claim 24, wherein the described emitter tip of at least one in these a plurality of non-linear electron emitting devices is melted, and causes this non-linear electron emitting device inoperative.
26. a method comprises:
On substrate, form a plurality of non-linear electron emitting devices by following steps:
In the top surface of this substrate, form more than first groove;
Form the emitter layer of tip material on whole this substrate, wherein the first of this layer is disposed in above this more than first groove and the second portion of this layer is disposed in this more than first groove; And
Remove this first of this emitter layer of tip material.
27. method according to claim 26, the described first that wherein removes this emitter layer of tip material comprises complanation.
28. method according to claim 26 wherein forms this more than first groove and may further comprise the steps:
On whole this substrate, form mask layer;
Remove the part of this mask layer in more than first zone; And
Etch away the substrate in this more than first zone.
29. method according to claim 26 wherein forms this more than first groove and comprises the top surface that impresses this substrate.
30. method according to claim 26 wherein forms the top surface that this more than first groove comprises this substrate of embossing.
31. method according to claim 26 wherein forms the top surface that this more than first groove comprises this substrate of injection moulding.
32. method according to claim 26, also be included in and form more than second groove in the top surface of this substrate, wherein after removing this first of this emitter layer of tip material, each of this more than second groove does not have the emitter tip materials basically.
33. method according to claim 32, wherein the degree of depth of this more than second groove is less than the degree of depth of this more than first groove.
CN200780053672A 2007-05-07 2007-05-07 Nano-vacuum-tubes and their application in storage devices Pending CN101689401A (en)

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