CN101685390B - Method for changing number of line pipe tiers in line pipes of electronic system and electronic system thereof - Google Patents
Method for changing number of line pipe tiers in line pipes of electronic system and electronic system thereof Download PDFInfo
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Abstract
The invention relates to a method for changing number of line pipe tiers in line pipes of electronic system and an electronic system thereof, in particular to a method for correcting the line pipes in the electronic system. The method comprises providing a line pipe with a serial line pipe tier of the primary number; using the line pipe with the serial line pipe tier of the primary number to carry out operation of the electronic system in a primary mode; changing the line pipe tier of the primary number into a line pipe tier of the secondary number, wherein the secondary number is different from the first number; and using the line pipe with the line pipe tier of the secondary number in a secondary mode. Each line pipe tier in the line pipe is used for outputting data in each period of a clock signal to the next line pipe tier.
Description
Technical field
The present invention relates to change a line construction of an electronic system, relate in particular to a number that in the line construction of an electronic system, changes the pipeline level.
Background technology
Along with in constantly the now electronic system of soaring rate of growth is used, never stopped for the demand of more efficient microprocessor usefulness.One is used for promoting the design example of a processor efficiency such as the utilization of instruction pipeline (instruction pipeline) is arisen at the historic moment then.Fig. 9 shows the typical instructions pipeline that is used for a CPU (central processing unit) (central processing unit, CPU) according to correlation technique.The processor inside of pipeline is organized into a plurality of levels (stage), wherein each level by tissue continuously with is connected bunchiness so that in a clock period, the estimated and preparation in next clock signal of the logic of each level can supply to move on to next pipeline level.For example, general 4 a level pipelines pipeline 900 as shown in Figure 9 comprises four levels: read (fetch), decoding (decode), carry out (execute) and write back (write-back).Each manufactured microprocessor nearly all uses two-layer at least pipeline now, and many designs comprise the many pipelines such as 7,10 even 31 layers.This structure of this processor allows bulk treatment time showing to be shortened, so can to increase efficiently the usefulness of a processor.
The usefulness of one processor measures by the ability of its process computer instruction in the unit interval.To arbitrary processor, carrying out the required time of the given instruction set of a task (and like this one can measure efficiency index) can be analyzed as follows:
Wherein icount is total instruction count (present task is fixed) of this task, ccount is the total clock cycle counting (this processor is fixed) of this task, and IPC represents the instruction number (instructions per cycle) of per clock period, is the executable instruction average of the every clock of this given processor.Concerning a pipeline processor, a shorter pipeline can cause a higher IPC because of the adverse effect of pipeline bubble (pipelinebubbling) and line branches (pipeline branching).When same frequency is carried out same task, there is a processor of high IPC value that higher performance is arranged.In other words, there is a processor of high IPC value and still can keep same performance in the lower frequency execution.
According to correlation technique, the processor of making now is designed to be suitable for the line construction of fixing of general " best circumstance " of this processor expection purpose.In case a pipeline layer progression is implemented the line construction design into this pipeline, this manufactured processor only can come reduce power consumption by changing frequency and voltage when needed.Therefore this processor is easy to suffer to be difficult between power and the usefulness awkward situation of trade-off: power consumption clock speed direct and processor is proportional, if therefore this clock speed is reduced, this usefulness reduces to scale.The problem of processor is to be that these parameters (changing this frequency or this voltage) can not reach based on the optimum balance between the high-effect and low power consumption of application demand at present.
Summary of the invention
Therefore one of purpose of the present invention is to provide a kind of method and electronic system that line construction is promoted treatment effeciency and lowered power demand of revising.
An example embodiment of the present invention discloses a kind of method that is used for revising the pipeline in the electronic system, and the method comprises: the pipeline that the series connection pipeline level with one first quantity is provided; This pipeline that has a pipeline level of this first quantity by utilization in a first mode carries out the operation of this electronic system; The pipeline level that changes this first quantity becomes the series connection pipeline level of one second quantity, and wherein this second quantity is different from this first quantity; And this pipeline that has a pipeline level of the second quantity by utilization in one second pattern carries out the operation of this electronic system; Wherein each the pipeline level in this pipeline is used for exporting next pipeline layer level of data in each clock period of a clock signal.
According to another example embodiment of the present invention, an electronic system comprises: a pipeline has the series connection pipeline level of one first quantity; One pipeline control module, the pipeline level that is used for changing this first quantity in this pipeline becomes the series connection pipeline level of one second quantity, and this second quantity is different from this first quantity; An and logic engine (logic engine), the pipeline that is used in a first mode having by utilization the pipeline level of this first quantity carries out the operation of this electronic system, and the pipeline that is used in one second pattern having by utilization the pipeline level of this second quantity carries out the operation of this electronic system; Wherein each the pipeline level in this pipeline is used for exporting next pipeline layer level of data in each clock period of a clock signal.
Description of drawings
Fig. 1 shows the example according to the relation between usefulness of the present invention, pipeline level and frequency.
Fig. 2 is the schematic diagram according to an electronic system of an example embodiment of the present invention.
Fig. 3 illustrates the process flow diagram according to the method for a kind of pipeline distortion (morphing) of an example embodiment of the present invention.
Fig. 4 illustrates the fusion (fusing) and division (splitting) pipeline level according to method shown in Figure 3.
Fig. 5 illustrates pipeline level shown in Figure 2, and wherein these pipeline levels are merged by the input trigger (input flip flop) of difference bypass or these levels of non-bypass or divide.
Fig. 6 illustrates and utilizes clock phasing (clock phasing) to merge or divide these pipeline levels shown in Figure 2.
Fig. 7 illustrates and utilizes latch (latch) to merge or divide these pipeline levels shown in Figure 2.
Fig. 8 shows the latch circuit of the input that is used to these pipeline levels in the control chart 7.
Fig. 9 shows a typical instructions pipeline that is used for a CPU (central processing unit) according to correlation technique.
Figure 10 shows these pipeline levels of Fig. 5, wherein should can be fed into a door brake style clock (gated clock) signal by the input trigger of bypass.
[main element symbol description]
| 200、290 | Electronic system |
| 201 | Input |
| 202 | |
| 210 | Logic engine |
| 220 | Pipeline |
| 221-229 | The pipeline level |
| 230 | |
| 240 | The pipeline control module |
| 250 | Frequency control unit |
| 260 | Operating frequency |
| 270 | Voltage control unit |
| 280 | |
| 500 | |
| 510 | |
| 520、841、842 | |
| 1000 | The AND door |
[0022]
| CLK | Input clock signal |
| CLK’ | Lower clock frequency |
| D | Pipeline level output signal |
| BYPASS_EN | Select signal |
| Q | One output of pipeline level |
| S1 to S8, P1 to P3 | The pipeline level |
| CLK_S1、CLK_S2、CLK_S3、CLK_S4、CLK_S5、CLK_S6、CLK_S7、CLK_S8 | Clock signal |
| S1_HPL, S2_HPL to S8_HPL, 811 | The high pass latch |
| S1_LPL, S2_LPL to S8_LPL, 812 | The low pass latch |
| Vdd | High voltage |
| Gnd | Ground voltage |
| SEL | Control signal |
Embodiment
According to correlation technique, available processor is not enough to keep treatment efficiency when reducing power consumption now, when increasing usefulness for those tasks, also can't keep (that is, do not increase) power consumption.This is because in arbitrary specific frequency, owing to having the adverse effect of pipeline foam and branch one than long lines, one can cause a higher IPC in comparison than the short tube line.In the same old way, one can cause low IPC than long lines, and therefore the operating frequency of this pipeline must be increased to keep identical usefulness.Yet using than long lines has a benefit to be that generally speaking an operating frequency than long lines can be promoted to than a height that comes than the short tube line that must carry out same operation.So may need very dynamical system generally speaking to need one than long lines.
Please refer to Fig. 1, Fig. 1 shows an example of the relation between usefulness, the pipeline number of plies and the frequency.Dotted line among Fig. 1 shows that the speed that changes for the specific clock period (for example: clock frequency) and under the condition take MHz as unit, in the equivalent usefulness level of one 7 layers of pipeline, one 5 layers of pipeline and one 3 layers of pipeline.Suppose that one 7 layers of pipeline reach 0.5, one 5 layer of pipeline of an average IPC value and reach an average IPC value 0.6, and one 3 layers of pipeline reach an average IPC value 0.8.As mentioned above, the usefulness of a previous defined processor can be proportional with the product of this operating frequency and this average IPC.As can be seen from Figure 1, operate in the usefulness level 107 of 7 layers of pipeline of 360MHz equal with the usefulness level 105 of 5 layers of pipeline that operate in 300MHz.Similarly, usefulness level 115 with 113 respectively 5 layers with 3 layers of pipeline in identical, and usefulness level 120 and 130 also show in the pipeline design of level each separately on an equal basis.In usefulness level 107, can reach the IPC value that improves this processor by move to one 5 layers of processor from one 7 layers of processor, and in this process, reach the needed clock frequency of equivalent usefulness level and be reduced to 300MHz from 360MHz.When keeping usefulness level 115 level 113 equivalent with it, this identical change can be finished by moving to one 3 layers of processor from one 5 layers of processor and clock frequency being reduced to 150MHz from 200MHz.In other words, when still keeping this same performance, operate the power consumption that this processor can effectively reduce this electronic system at a higher IPC.What the power consumption of this electronic system was lowered is former because the operating frequency of this system can be lowered when keeping this same performance 107 (or 105).
On the other hand, along with the increase of pipeline layer number of stages, this processor can improve this processor efficiency compared to clock frequency and the internal pipeline level of this logic engine of increase in the situation of lower pipeline layer number of stages.Yet, what need balance is, more multi-line level and upper frequency not only can cause reducing the instruction number (Zhao Yin is in pipeline design problem such as foam or branch) of per unit clock period, also can cause higher power consumption (switching and relevant loss owing to the voltage that is increased).
The processor of prior art is not enough to its line construction is adjusted to the demand that is suitable for processing application.Different processing tasks can change performance requirements: simple application (for example audio frequency play or Document Editing) can be in a short tube line structure full blast, more harsh task (for example video compress or video playback) is then more favourable in than long lines one.On the other hand, for more not harsh task, preferably operate to alleviate power consumption at lower frequency, but the processor of prior art is so done when carrying out more harsh task, to cause lower and be difficult to the usefulness of making us accepting.
These characteristics that its pipeline layer number of stages of a processor of the present invention deformable when carrying out a large amount of different task (namely revise or adapt to) and clock speed (frequency) thereof make this processor are adjusted to the configuration that is fit to the most immediately for immediately application to be processed or task.It is also to be noted that, although describe for example be used in calculation element person and a line construction thereof of a processor in the example that next is suggested, the application of this processor is not the restriction to scope of the present invention.That is to say, the pipeline distortion that the present invention describes can be applied to arbitrary logic engine or utilize the treatment element of a line construction, and the equal spirit according to the invention and should belong to scope of the present invention of these applicating adn implementing examples.For example, the processor of other form such as CPU (central processing unit) (CPU), painting processor (graphics processor), digital signal processor (DSP), integration processor (integrated processor) and flush bonding processor (embedded processor) all can be applicable to enforcement of the present invention.In addition, other logic engine such as special IC (ASIC) or inner programmable gate array (FPGA) with line construction also can benefit and utilize the present invention from the present invention.
Fig. 2 is the schematic diagram according to an electronic system 200 of an example embodiment of the present invention.Electronic system 200 has an input 201 and and exports 202, wherein inputs 201 and is used for receive data for processing, and export 202 data that are used for transmitting after the final processing.In addition, electronic system 200 comprises pipeline 220, a deformation control unit 230, a pipeline control module 240, the frequency control unit 250 that a logic engine 210, has pipeline level 221-229 and a voltage control unit 270 of optionally implementing.Another system 290 that optionally implements is connected to electronic system 200.
Deformation control unit 230 control tube line traffic control unit 240 are out of shape (for example changing) this pipeline layer progression, and are coupled to pipeline control module 240 and frequency control unit 250.Pipeline control module 240 is coupled to logic engine 210 and pipeline 220, and is used for changing the different pipeline layer progression of pipeline layer progression to one in (i.e. distortion) pipeline 220.To describe in detail as follow-up, the distortion of pipeline level can be the number that increases or reduce pipeline level 221-229.Frequency control unit 250 is coupled to deformation control unit 230 and logic engine 210 and pipeline 220, and the clock frequency of control pipeline 220 and logic engine 210.No matter how many pipeline levels are included, next level of the exportable data of each level in each clock period in pipeline 220.
One incident method is suggested in addition for a pipeline that is used for being out of shape in (correction) electronic system 200 (a for example calculation element).Fig. 3 illustrates the process flow diagram according to the method for a kind of pipeline distortion of an example embodiment of the present invention, and it comprises following step:
Step 301: the pipeline 220 that logic engine 210 utilization has the pipeline level (for example: as shown in Figure 2 utilize nine pipeline level 221-229) of this first quantity operates.
Step 302: in system 200 or determine change and/or the required frequency of this logic engine of pipeline layer number of stages at the logic engine 210 of another system 290.To explain as follow-up, owing to the performance requirements of the application of being undertaken by system 200 or carrying out, this decision may occur.(for example: vision operation may need the usefulness higher than voice applications.) logic engine 210 in electronic system 200 or another system 290 sends the sequence that (issue) be comprised of a succession of control operation (its can referred to as control sequence) to deformation control unit 230.
Step 303: receiving from logic engine 210 or another system 290 and after being loaded with the indicator signal that (carry) change pipeline layer number of stages and frequency, deformation control unit 230 sending control signals to pipeline control module 240 and frequency control unit 250 begins to change respectively pipeline layer progression and operating frequency 260.
Step 304: pipeline control module 240 is adjusted pipeline layer progression in the pipeline 220 according to this control sequence.In one first embodiment, this pipeline layer progression is increased, and in one second embodiment, this pipeline layer progression is reduced.
Step 305: frequency control unit 250 is adjusted clock frequency 260 according to this control sequence.Especially, if the number of levels in the pipeline 220 is reduced, then as shown in Figure 1, can keep same performance by the operating frequency 260 that reduces this system.Thus, the power consumption of system 200 is reduced.On the other hand, if required more high-effect can't reaching than the short tube line by one, then this number of levels and this operating frequency all can side by side be increased.
Step 306: (hold by oneself's counting or friendship) after above-mentioned pipeline distortion is done, this processor (for example logic engine 210) can continue its execution.The pipeline level N1-N3 that next operation of this electronic system utilizes this second quantity (new quantity) carries out with corresponding operating frequency 260.
Further be explained as follows.At first, in the step 301, electronic system 200 normally operates and logic engine 210 utilizations have the pipeline 220 of this first quantity pipeline level (for example, nine pipeline level 221-229) to operate.For example: at a calculation element, this processor may just be play one video/movie file, finishes playing with this video file.Next, system 200 in step 302 (or another system 290) determines change and/or the logic engine 220 needed frequencies of pipeline layer number of stages in the pipeline 220, and above-mentioned decision is for example based on one or more factor that is deformed control module 230 and determines.This decision can utilize hardware, software or some correlation combiner to finish, and be used in the factor of its analysis can be by being assigned with the change of the task type that gives calculation element 200, specific performance requirements or its operating environment ... wait and be triggered.In present example, a combination of the task that the ending up being of this video file is assigned with (for example: Video processing or decoding no longer need) and performance requirements.Decision from step 302, electronic system 200 (or in another system 290) is sent the sequence that a succession of control operation forms, it can be the forms such as an instruction sequence, control register renewal, and may be implemented in a hardware state machine or its some correlation combiner.Optionally, in the pipeline distortion was carried out, deformation control unit 230 can be pointed out a time-out in commission or need postpone generation logic engine 210; Or select a ground, this processor (for example logic engine 210) can be finished its present instruction before time-out.During this processed, deformation control unit 230 to pipeline control module 240 and/or frequency control unit 250, indicated latter two element to begin this pipeline deformation process at step 303 sending control signal.In addition, but also sending control signal is to voltage control unit 270 for deformation control unit 230, and its details will be explained as follows.Pipeline control module 240 is adjusted the pipeline layer progression of pipeline 220 in step 304, and frequency control unit 250 is adjusted clock frequency 260 according to this control sequence in step 305.Note that but in deformation control unit 230 call-out step 304 or 305 one or both are whole, depend on that the usefulness of present action need is adjusted demand.Other should be noted, step 304 and 305 can be carried out simultaneously or one one be carried out first rearly.When this new clock frequency of this new pipeline level N1-N3 and/or logic engine 210 had been stablized, pipeline control module 240 can be sent with frequency control unit 250 and feed back to deformation control unit 230.Select a ground, deformation control unit 230 can be waited for predetermined time amount simply.After above-mentioned steps was finished, this processor (for example logic engine 210) can continue its execution in step 306, and the pipeline 220 that utilization has the pipeline level N1-N3 of this second quantity (new quantity) carries out the operation of electronic system 200.For example: the pipeline level of this second quantity can comprise three level N1-N3, and wherein this first level N1 comprises by fusion (fuse) old level 221,222 and 223 together; This second new level N2 comprises the old level 224,225 and 226 that is merged; And the 3rd level N3 comprise the old level 227,228 and 229 that is merged.Note that in each clock period of this operating frequency 260, the N1 transferring data is to N2, and in the same old way, in each clock period of this operating frequency 260, the N2 transferring data is to N3.So, this pipeline be deformed into comprise three level N1-N3 after, the whole identical function of originally carrying out in nine clock period of a higher operating frequency 260 by nine level 221-229 is satisfied by these three level N1-N3 and is carried out in three clock period of low operating frequency 260.
Note that in the said method, electronic system 200 need to not shut down for the new hierarchical structure that utilizes pipeline 220 or restart.In addition, in step 302, this logic engine may not can be required to postpone its operation; This can decide on specific enforcement of the present invention.More generally, logic engine 210 or processor be used in this process flow diagram with describe for illustrate just; Logic engine 210 can be a CPU (central processing unit), a digital signal processor (DSP), or utilize arbitrary flogic system of a line construction.This pipeline deformation method of the present invention affects all operations were of a flogic system or the execution of instruction, and looks each specific operation or instruction and do not change this line construction.That is to say, the present invention can be used to change pipeline layer number of stages in the pipeline, for different usefulness need or the different application of the system 200 of power dissipation modes for having.
Finishing to play in the example of a video file, deformation control unit 230 determines that low usefulness will correspondingly be accepted by pipeline control module 240 and frequency control unit 250 under present given operating conditions and signal.Deformation control unit 230 order pipeline control modules 240 reduce pipeline layer number of stages in the pipeline 220 and (for example: lower power consumption) as above illustrated according to Fig. 1 reach preferably the power economic benefits.In case (for example: the pipeline 220 with three level N1-N3) reached and therefore the usefulness of this pipeline be increased effectively, clock frequency 260 can be slowed down to reduce power consumption and be kept simultaneously usefulness originally a lower-level pipeline.In addition, along with an extra power is saved step, when in present condition, still keeping an acceptable usefulness level, can be reduced for logic engine 210 and the service voltage of line construction 220.Thus, pipeline control module 240 control pipelines 220 lower other number of levels, and frequency control unit 250 reduces the operating frequency 260 of the clock signal that drives pipeline 220, and voltage control unit 270 reduces the voltage swing of the service voltage of pipeline 220.This one can't from obtaining in the prior art, also can't be obtained under not using according to pipeline distortion of the present invention via the method that dynamically switches to a lower-level pipeline and save power.
Pipeline distortion among the present invention changes the number of the pipeline level 221-229 in the line construction 220 of logic engine 210.Change as shown in Figure 4 can be increase or the minimizing of pipeline layer number of stages.Change in order to reach this, the pipeline distortion of one embodiment of the invention comprises division one pipeline level P1 to a plurality of adjacent pipe line level S1-S4, or merges on the contrary and a plurality ofly become a single Fused pipeline level P2 in abutting connection with pipeline level S4-S7.Fig. 4 shows that one 8 layers of pipeline that comprise pipeline level S1 to S8 are deformed into as comprising 3 layers of pipeline level of pipeline level P1 to P3.Select a ground, these 3 layers of pipelines that comprise pipeline level P1 to P3 can be deformed into as comprising one 8 layers of pipeline of pipeline level S1 to S8 conversely speaking.In example shown in Figure 4, being fused in abutting connection with pipeline level S1 to S4 is that a quilt merges pipeline P1; Be one 8 layers of pipeline if be that these 3 layers of pipelines are deformed on the contrary among Fig. 4, pipeline level P2 must be split into and be adjacency pipeline level S5 to S8.It should be noted that the pipeline layer number of stages among Fig. 4 only is to be used for one of illustration purpose optionally to select, is not limitation of the present invention.Also it should be noted that in the pipeline deformation process, it might be according to this control signal from this deformation control unit, with fusion and both combinations of division of pipeline level this pipeline of recombinating.Yet also considerable is that basic pipeline layer progression is the maximal value of the pipeline layer progression in the implementation-specific line mode that can be present in a design; That is to say, the pipeline distortion can not split into the pipeline layer level as surpassing the pipeline level of the basic pipeline layer number of stages in the design.In the example of Fig. 2, basic pipeline layer number of stages is 8, and so, pipeline level P1 to P3 can not be split into as surpassing 8 pipeline levels.In addition, the ad hoc arrangement that is presented at the pipeline level in the first mode when the example of Fig. 4 merges the ad hoc arrangement that becomes the pipeline level in the second pattern, these are arranged to arbitrarily, and above-mentioned is presented for purposes of illustration choosing at random only, should not be considered as limitation of the scope of the invention.For instance, this first mode or the second pattern may not be the pattern that fully divided of whole pipeline levels (for example among Fig. 4 shown in the pipeline level S1-S8) yet; This first and second pattern all can be pipeline level S1-S8 different merged arrangement and this pipeline deformation operation becomes another from an arrangement distortion, decides with the arrangement of deformation control unit 230 on being fit to electronic system 200.
About pipeline level real fusion and division, one first embodiment of the present invention is suggested following and illustrates such as Fig. 5, the input trigger that wherein the pipeline level can be by these levels of bypass or non-bypass respectively and merged or divide.
In the present embodiment, each of pipeline level S1-S8 comprises one group of logic 500, as shown in Figure 5.Logic 500 comprises an input trigger 510, and input trigger 510 has two inputs, respectively from this pipeline level output signal D and an input clock signal CLK.In addition, each of pipeline level S1-S8 comprises a multiplexer (multiplexer, MUX) 520, multiplexer 520 have the pipeline level output signal D that is connected directly to the front one first input, be connected to the output of input trigger 510 one second input, be coupled to one of signal BYPASS_EN that pipeline control module 230 provides select signal, with an output Q who is connected to this pipeline level.According to this BYPASS_EN signal wire, the output that multiplexer 520 can be after the positive and negative running of this input trigger or directly select one this foreline level output signal D of bypass input trigger 510.
When the pipeline level is merged, for example merge pipeline level S1-S4 and become Fused pipeline level P1 among Fig. 4,240 pairs of pipeline control modules estimate Fused in the middle of the pipeline level all the other except the first level all activated (activate) in abutting connection with the BYPASS_EN signal wire of pipeline level.That is to say, in this example at level S2, S3 and S4, the BYPASS_EN signal wire of this activation triggers the input that multiplexer 520 in those levels (S2-S4) is selected bypass input trigger 510, and the result of pipeline level output signal D directly is passed to its output Q.On effect, a string pipeline level that is merged of the BYPASS_EN signal formation that this optionally activates: one is merged the pipeline level.Going here and there at this, nowadays these data-signals in abutting connection with between the pipeline level S2-S4 of bypass input trigger directly are connected and need not wait for clock signal clk.For these in the pipeline level first, its BYPASS_EN signal that leads to logic 500 should be zero forever so that in the clock signal clk the next clock period trigger the at present input of (fusion) pipeline level from previous pipeline level.
Optionally, as shown in figure 10, by come according to this BYPASS_EN signal gate (gating) (for example: forbidding) lead among this level S2-S4 by the clock signal clk of bypass input trigger 510, power consumption can be reduced again, wherein above-mentioned gate optionally arranges in addition gate of a logic gate before each input trigger 510, or a logic gate that shares optionally is set to a group input trigger 510 together gate.As shown in figure 10, an AND door 1000 is used in order to be come this CLK signal of gate by the trigger 510 of bypass, and the trigger 510 that this measure will be further be used by time control (clocking) not comes reduce power consumption.Since this Clock gating or forbidding concept have been known to the same trade, omit its detailed description at this.
On the other hand, will be divided when merging the pipeline level, this pipeline control module 240 is restrained (de-activate) and is led to and before merged this BYPASS_EN signal wire of pipeline level by these of bypass.The BYPASS_EN signal wire of this supression triggers these multiplexers 520 and selects input by input trigger 510, and the result of pipeline level output signal D is not directly led to its output Q.On effect, by activation input trigger 510, Fused pipeline level is separated once again before.Optionally, if the clock signal clk that leads to all the input trigger 510 in the pipeline level before by gate or forbidding, then signal CLK is resumed, to trigger according to normal running.
Inspecting this first embodiment of the present invention, other related application can be more clear understandable with enforcement, and should be within the scope of the invention involved.
According to one second example embodiment of the present invention, the pipeline distortion is merged by the pipeline level and the pipeline layer level divides to reach, and by this, each pipeline level is by having the clock of a special use that quite concerns to control with logic engine 210.This second example embodiment of the present invention merges a plurality of in abutting connection with the pipeline level, wherein this fusion be by time control will by this clock signal merge in the pipeline level first and by time control these in the pipeline level except each all basic pipeline level in abutting connection with the first level of pipeline level, and adopt the phase-delayed versions of this clock signal but not its original phase version.
Please recall Fig. 4, it illustrates one 8 layers of pipeline distortion becomes one 3 layers of pipeline; In the lump with reference to figure 6, it shows one second embodiment that utilizes clock phased (clock phasing) among the present invention simultaneously.In the example of Fig. 4, the pipeline level S1-S4 in the first mode is integrated into pipeline level P1 in the second pattern, and in the same old way, pipeline level S5-S7 is integrated into pipeline level P2, and S8 becomes pipeline level P3.According to the second embodiment of the present invention, pipeline control module 240 is applied to S1, S5 and S8 with this clock signal, this be because these pipeline levels for each group will be Fused in the pipeline level first; These clock signals are labeled as CLK_S1, CLK_S5 and the CLK_S8 among Fig. 6.Pipeline level S2-S4 and S6-S7 are then by the version institute time control of the in the same manner phase delay of this clock signal.For the pipeline level P1 in the second pattern, be provided to respectively clock signal clk _ S2, the CLK_S3 of pipeline level S2, S3 and S4 and CLK_S4 will with respect to clock signal clk _ S1 by 90 ° of phase delays, 180 ° with 270 °.Similarly, for the pipeline level P2 in the second pattern, be provided to respectively clock signal clk _ S6 of pipeline level S6 and S7 and CLK_S7 will with respect to clock signal clk _ S5 by 120 ° of phase delays with 240 °.The result of the second embodiment of the present invention is that new, a lower clock rate C LK ' can be obtained, and identical with CLK_S1, CLK_S5 and CLK_S8 in the example of Fig. 6.In this example, this derivative clock period in fact in (substantially) and the second pattern clock period of the longest Fused pipeline level identical; In this example, this derivative clock period comprises clock period from the pipeline level S1-S4 of this first mode for this.So, in each clock period of the clock signal (CLK_S1 among Fig. 6, CLK_S5 and CLK_S8) of this non-phase delay, led to next pipeline layer level from the data of each mixed pipeline level P1, P2 and P3.Shown that the clock signal of leading to these adjoining course pipeline levels is the phase-delayed versions of this clock signal although note that present example, this only is in order to illustrate explanation, and is not limitation of the present invention.
When the pipeline level that merges is split into as adjacency pipeline level, occured once similar but reverse process.That is to say, the phase delayed clock signal that is used to consist of a Fused pipeline level be resumed become with this pipeline clock signal (for example: this non-phase delayed clock signal) identical.So, each clock period of this clock signal can be caused from the data of these each in the pipeline level and be led to next adjacent pipe line level.It is also to be noted that, if these any one in the pipeline level be a Fused pipeline level (namely, comprise and surpass a basic pipeline level), except each the first level in abutting connection with the pipeline level, these basic pipeline levels can be come by time control by the phase-delayed versions of this clock signal.
From this example and after understanding the present invention and all embodiment thereof, other variation that this clock signal and clock frequency thereof are done should become clear understandable for a person skilled in the art, and these methods also should belong to scope of the present invention.
One the 3rd embodiment of the present invention further is suggested, and wherein each the pipeline level in the pipeline is by utilizing latch to implement.Please refer to Fig. 7, it is the example according to the 3rd embodiment of the present invention.Among Fig. 7, pipeline level S1 to S8 implements with latch, each pipeline level comprises two latchs: a high pass latch (is denoted as S1_HPL universally, S2_HPL ..., S8_HPL), (be denoted as universally S1_LPL with a low pass latch, S2_LPL ..., S8_LPL).
One embodiment of the Circuit display third embodiment of the present invention of Fig. 8.Among Fig. 8, the function of pipeline control module 240 is identical with the function of pipeline control module of corresponding label among Fig. 2 in fact, wherein logic engine 210 also in fact with Fig. 2 in logic engine 210 be same unit.In the present embodiment, each latch (or every a group of the latch of pipeline) is coupled to a multiplexer (MUX) 841, this multiplexer has the input that is coupled to respectively this clock signal clk and a reverse clock signal clk _ INV, and have in addition one the 3rd input, be coupled to one " height " voltage Vdd or a ground voltage Gnd both one of.Each multiplexer 841 also has and is coupled to one of pipeline control module 240 and selects signal SEL, and has in addition an output, lead to a high pass latch 811 in the logic engine 210 or a low pass latch 812 both one of.By this above-mentioned circuit, pipeline control module 240 is by utilizing this control signal SEL to control multiplexer 841,842, with control each latch 811,812 behavior becomes a high pass latch or a low pass latch or transparent latch (transparentlatch).Please note among Fig. 8, for various high pass latchs of each configuration and the combination in the low pass latch combinations, being illustrated at this is that a demonstration embodiment illustrates.
At this embodiment, recall the example of Fig. 7, pipeline control module 240 becomes a high pass latch by first latch among configuration (configuring) pipeline level S1-S4 in the second pattern, become a low pass latch by another latch among the configuration pipeline level S1-S4, and become transparent latch by configuring these in abutting connection with whole other latchs in the pipeline level, merge in the first mode in abutting connection with pipeline level S1-S4 and become pipeline level P1 in the second pattern.In this example, one " mid point " latch is chosen as this low pass latch, this low pass latch before with three transparent latch are all arranged afterwards, but this is not the requirement to the third embodiment of the present invention.The pipeline level S5-S7 that same processing is continued to be applied in the first mode equally is created in Fused pipeline level P2 in this second pattern, and wherein this high pass latch and low pass latch are all being followed two transparent latchs in this example.By reconfiguring the latch of pipeline level S1-S7, each comprises a single high pass latch and a single low pass latch and zero or more transparent latch Fused pipeline level P1 and P2.Note that shown in the example of S8 in the first mode and the pipeline level P3 in the second pattern not have other latch can supply to be configured as transparent latch; This also drops in the category of the present invention.
If this pipeline deformation sequence needs a Fused pipeline level to be divided, as previously described same program occurs as follows: these that divide are configured in abutting connection with the latch in the pipeline level, so that the comprising a single high pass latch and a single low pass latch and arbitrary other in abutting connection with the pipeline level and be configured to transparent latch of each division.After inspecting above-mentioned disclosure, it is clear understandable that this fission process should become for a person skilled in the art, therefore for the sake of brevity, the further describing then of process of division pipeline level omitted.
One of benefit of the present invention is, the line construction that an electronic system can need to be out of shape himself according to different application or other system is to comprise the pipeline level of different numbers.How many levels one pipeline clock signal and pipeline supply voltage also can according to having change in the pipeline, with the reduce power consumption demand or increase required usefulness.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (8)
1. a pipeline that is used for controlling an electronic system is with the method for the quantity that changes its pipeline level, and the method includes:
One pipeline is provided, this pipeline utilizes the series connection pipeline level of the first quantity to operate in first mode, and the series connection pipeline level of this first quantity becomes the series connection pipeline level of one second quantity in the change pipeline, this second quantity is different from this first quantity, in the second pattern, utilize the series connection pipeline level of the second quantity to operate, wherein the pipeline of all in first mode level is basic pipeline level, and each the pipeline level in the second pattern is that the basic pipeline level of basic pipeline level or the two or more adjacency from first mode merges;
Apply a clock signal to each pipeline level; And
One pipeline control module is provided, thereby be used for the control pipeline and generate the output data, wherein for the pipeline level of utilizing two or more basic levels, the pipeline level that this clock signal time control first is basic, and a plurality of versions with the phase delay that one after the other increases that this pipeline control module generates this clock signal, so that all of its neighbor basic pipeline level of time control except this first basic pipeline level respectively; And
Each cycle in this clock signal is exported data to next pipeline level from each pipeline level.
2. the method for claim 1, wherein this pipeline is an instruction pipeline of a processing unit, and the operation of electronic system is a plurality of instructions of this processing unit.
3. the method for claim 1 also comprises the quantity that reduces the pipeline level in the pipeline, for the application of the electronic system that is used for having low usefulness demand.
4. the method for claim 1 also comprises the quantity that increases the pipeline level in the pipeline, for the application for the electronic system with higher performance demand.
5. the electronic system that can revise line construction includes:
One pipeline, in first mode, utilize the series connection pipeline level of the first quantity to operate, and the series connection pipeline level of this first quantity becomes the series connection pipeline level of one second quantity in the change pipeline, this second quantity is different from this first quantity, in the second pattern, utilize the series connection pipeline level of the second quantity to operate, wherein the pipeline of all in first mode level is basic pipeline level, and each the pipeline level in the second pattern is that the basic pipeline level of basic pipeline level or the two or more adjacency from first mode merges;
Be applied to a clock signal of each pipeline level; And
One pipeline control module, be used for controlling pipeline and generate the output data, wherein for the pipeline level of utilizing two or more basic pipeline levels, the pipeline level that this clock signal time control first is basic, and this pipeline control module generates a plurality of versions with the phase delay that one after the other increases of this clock signal, so that all of its neighbor basic pipeline level of time control except this first basic pipeline level respectively
Wherein each pipeline level arrives next pipeline level in each cycle output data of this clock signal.
6. electronic system as claimed in claim 5, wherein this pipeline is the instruction pipeline of a processing unit, and the operation of electronic system is a plurality of instructions of this processing unit.
7. electronic system as claimed in claim 5 also comprises a pipeline deformation control unit, is used for controlling the quantity that this pipeline control module reduces the pipeline level in the pipeline, for the application of the electronic system that is used for having low usefulness demand.
8. electronic system as claimed in claim 5 also comprises a pipeline deformation control unit, is used for controlling the quantity that this pipeline control module increases the pipeline level in the pipeline, for the application for the electronic system with higher performance demand.
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| CN1950782A (en) * | 2004-05-04 | 2007-04-18 | 国际商业机器公司 | Synchronous pipeline with normally transparent pipeline stages |
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| CN1950782A (en) * | 2004-05-04 | 2007-04-18 | 国际商业机器公司 | Synchronous pipeline with normally transparent pipeline stages |
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| JP特开平9-319578A 1997.12.12 |
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