CN101681192A - Signal processor and signal processing system - Google Patents
Signal processor and signal processing system Download PDFInfo
- Publication number
- CN101681192A CN101681192A CN200880015375A CN200880015375A CN101681192A CN 101681192 A CN101681192 A CN 101681192A CN 200880015375 A CN200880015375 A CN 200880015375A CN 200880015375 A CN200880015375 A CN 200880015375A CN 101681192 A CN101681192 A CN 101681192A
- Authority
- CN
- China
- Prior art keywords
- signal processing
- signal processor
- treatment capacity
- clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A signal processor comprises a signal processing section for performing the signal processing of signal data to output the result data, a power supply section for supplying power to the signal processing section, a clock supply section for supplying a clock to the signal processing section, a processing amount predicting section for predicting the amount of the processing in the signal processingsection on the basis of the signal data and outputting the prediction value of the processing amount, a processing amount observing section for observing the processing amount of the signal processingperformed by the signal processing section and outputting the completion value of the processing, and a control value determining section for determining the voltage of the power supply and the frequency of the clock which are supplied to the signal processing section according to the prediction value of the processing amount, the completion value of the processing, and elapse information indicating the elapsed time from the start of the signal processing. The power supply section supplies the power supply of the voltage determined by the control value determining section to the signal processing section. The clock supply section supplies the frequency of the clock determined by the control value determining section to the signal processing section. This signal processor makes it possibleto control both of processing capability and low power consumption while assuring the real time property to complete the processing specified within a predetermined time.
Description
Technical field
The present invention relates to guarantee in response to treatment capacity the signal processing apparatus and the signal processing system of processing in real time.
Background technology
Carry out power control in response in treatment capacity so that reduce the low power consumption control of power consumption, provide in response to the technology (for example referring to patent documentation 1) that will carry out clock control in the last task executions condition of carrying out of OS (operating system).Figure 11 shows the sequential chart of the economize on electricity control of each task of describing in patent documentation 1.Sequential chart shown in Figure 11 is indicated the mode of operation of each task executions state, performance setting state and CPU.
Simultaneously, provide the instruction code of incorporating CPU into by the control mark that will be used to provide/stop voltage or clock to realize the technology (for example referring to patent documentation 2) of low-power consumption.In related technology, control providing/stopping of clock in response to the instruction of according to instruction code (being the cycle of CPU) and in turn carrying out.But not having to use can be when monitoring the entire process amount by the prediction or the quantity of observing the quantity of all instructions or the data of handling, guarantee should be at the fixed time in the power consumption control of finishing of realization processing.
Patent documentation 1:JP-A-8-76874
Patent documentation 2:JP-A-2002-169790
Summary of the invention
The problem to be solved in the present invention
The above-mentioned low power consumption control that provides by reference patent documentation 1 is in response to the self-adaptation mode of operation control by the OS managerial role to be the treatment capacity of unit.But because carry out real-time task management, system performance is because external factor or internal factor change, and related control lacks quick response, because this is controlled corresponding to the OS management method.Therefore, in related control, do not guarantee in preset time, to realize finishing of performed task (processing).
In the above-mentioned low power consumption control that provides by reference patent documentation 2, can be to use described control on the periodic basis of unit in instruction with CPU.But, can not carry out the power consumption control of finishing that can guarantee to realize in should be at the fixed time the processing of whole command quantities or deal with data amount.
The purpose of this invention is to provide a kind of signal processing apparatus and signal processing system, when it can realize the true-time operation of finishing of designated treatment in guaranteeing at the fixed time, control and treatment ability and low-power consumption.
Be used to solve the means of described problem
According to an aspect of the present invention, provide a kind of signal processing apparatus, having comprised: signal processor is used for input signal data is carried out signal Processing, with the output result data; Power supply provides device, and being used for provides power supply to described signal processor; Clock provides device, and being used for provides clock to described signal processor; The treatment capacity fallout predictor is used for predicting according to described signal data the treatment capacity of described signal processor, with output treatment capacity predicted value; The treatment capacity viewer is used to observe the treatment capacity by the signal Processing of described signal processor execution, with the output value of finishing dealing with; And controlling value determining section, be used for according to treatment capacity predicted value from described treatment capacity fallout predictor output, from the value of finishing dealing with of described treatment capacity viewer output with indicate from the process information that begins institute's elapsed time of the signal Processing of described signal processor, determine to be provided the power source voltage that device is provided to described signal processor and will be provided device to provide to the frequency of the clock of described signal processor by described clock by described power supply, wherein, described power supply provides the power supply that device is adapted to be provides its voltage to be determined by the controlling value determining section to described signal processor, and described clock provides device to provide its frequency by the definite clock of controlling value determining section to described signal processor.
According to another aspect of the present invention, provide a kind of signal processing apparatus, having comprised: signal processor is used for input signal data is carried out signal Processing, with the output result data; Power supply provides device, and being used for provides power supply to described signal processor; Clock provides device, and being used for provides clock to described signal processor; The treatment capacity viewer is used to observe the treatment capacity by the signal Processing of described signal processor execution, with the output value of finishing dealing with; And, the controlling value determining section, be used for according to input treatment capacity designated value, from the value of finishing dealing with of described treatment capacity viewer output with indicate from the process information that begins institute's elapsed time of the signal Processing of described signal processor, come to determine to be provided the power source voltage that device is provided to described signal processor and will be provided device to be provided to the frequency of the clock of described signal processor by described clock by described power supply, wherein, the power supply that described power supply provides device to provide its voltage to be determined by described controlling value determining section to described signal processor, and described clock provides device to provide its frequency by the definite clock of described controlling value determining section to described signal processor.
According to another aspect of the present invention, provide a kind of signal processing system, comprised described signal processing apparatus and treatment capacity designated equipment, described treatment capacity designated equipment is used for exporting the treatment capacity designated value that is imported into described signal processing apparatus.
Benefit of the present invention
According to signal processing apparatus of the present invention and signal processing system, can be in guaranteeing at the fixed time control and treatment ability and low-power consumption in the true-time operation of finishing of realization designated treatment.
Description of drawings
Fig. 1 is the block scheme that the signal processing apparatus of the first embodiment of the present invention is shown.
Fig. 2 show when when carry out handling at the uniform velocity smoothly up to till the target elapsed time ' ta ' after the described processing of beginning, respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) power consumption.
Fig. 3 shows when handling when not carrying out smoothly respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) example of power consumption (wherein (late) stage is late used the example of high speed processing).
Fig. 4 shows when handling when not carrying out smoothly respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) example of power consumption (wherein using the example of high speed processing in the stage of centre).
Fig. 5 shows when handling when not carrying out smoothly respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) example of power consumption (wherein the stage is in early days used the example of high speed processing).
Fig. 6 shows the block scheme of the signal processing apparatus of the second embodiment of the present invention.
Fig. 7 shows the block scheme that signal generates equipment, and this signal generating apparatus output will be imported into signal data and the treatment capacity designated value in the described signal processing apparatus.
Fig. 8 shows the block scheme of the signal processing apparatus of the third embodiment of the present invention.
Fig. 9 shows the system that constitutes by broadcasting station and portable terminal.
Figure 10 shows the block scheme of the portable terminal of the signal processing apparatus that is equipped with the 3rd embodiment.
Figure 11 shows the sequential chart of the economize on electricity control of each task of describing in patent documentation 1.
The explanation of drawing reference numeral
100 signal processors
101 treatment capacity fallout predictors
103 treatment capacity viewers
105,205,305 controlling value determining sections
106 timers
Embodiment
Hereinafter with reference to accompanying drawing embodiments of the invention are described.
(first embodiment)
Fig. 1 shows the block scheme of the signal processing apparatus of the first embodiment of the present invention.As shown in fig. 1, the signal processing apparatus of first embodiment comprises that signal processor 100, treatment capacity fallout predictor 101, treatment capacity viewer 103, controlling value determining section 105, timer 106, power supply provide device 111 and clock that device 113 is provided.
100 pairs of signal datas 151 from the external unit input of signal processor carry out signal Processing, and output result data 153.Provide device 111 to provide power supply from power supply, and provide device 113 to provide clock to signal processor 100 from clock to signal processor 100.In signal processor 100, provide the frequency of the clock that device 113 provides to change processing power and power consumption signal Processing in response to the power source voltage that provides device 111 to provide from power supply with from clock.
Treatment capacity fallout predictor 101 is predicted treatment capacity in signal processor 100 according to described input signal data 151, exports treatment capacity predicted value 102 then.The treatment capacity of the signal Processing that treatment capacity viewer 103 observation signal processors 100 have been carried out, output value of finishing dealing with 104 then.Timer 106 counting begins institute's elapsed time from the processing undertaken by signal processor 100, exports the process information 107 that is used to indicate the elapsed time of being counted then.
Controlling value determining section 105 is according to treatment capacity predicted value 102, the value of finishing dealing with 104 and process information 107 definite power source voltage that provide device 111 to provide to signal processor 100 by power supply, and output is used to indicate the setting value 108 of determined voltage then.Similarly, controlling value determining section 105 determines to be provided by clock the frequency of the clock that device 113 provides to signal processor 100 according to treatment capacity predicted value 102, the value of finishing dealing with 104 with through information 107, and output is used to indicate the setting value 109 of determined clock frequency then.In this case, when supply voltage becomes big and clock frequency when uprising, the power consumption in signal processor 100 increases a lot.
The example 1-4 of the control that the signal processing apparatus of present embodiment is carried out is described hereinafter with reference to Fig. 2-5.Fig. 2-5 shows respectively with respect to (a) the residue treatment capacity PA in signal processor 100 in elapsed time ' t ' and (b) variation of the power consumption PC in signal processor 100.At this, reference symbol ' ta ' expression that invests the horizontal ordinate among Fig. 2-5 is used to guarantee the target elapsed time of processing in real time.
(example 1)
Hereinafter with reference to Fig. 2 illustrated example 1.Invest the treatment capacity of the processing that the reference number 501 of the horizontal ordinate among Fig. 2 (a) indicates to carry out.Fig. 2 show when when carry out handling at the uniform velocity smoothly up to till the target elapsed time ' ta ' after the described processing of beginning, respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) power consumption.As shown in Figure 2, when when carry out handling at the uniform velocity smoothly, the handling capacity of signal processor 100 (throughput) does not change.Therefore, reduce the residue treatment capacity smoothly, and power consumption is constant.As a result, in this case, we can say, finish processing with the power consumption of minimum up to target elapsed time " ta ".
(example 2)
Come illustrated example 2 hereinafter with reference to Fig. 3.Fig. 2 shows the situation that processing is carried out smoothly, but can consider to handle not by predetermined situation of carrying out.As cause the factor of handling the such situation carry out unsmoothly, there be the complicated of the data of handling and in the signal processing apparatus of present embodiment and the relation between the miscellaneous part (for example the assurance of the standby of shared storage etc.) or the like.Fig. 3 shows when handling when not carrying out smoothly respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) example of power consumption (wherein the stage is late used the example of high speed processing).
As shown in Fig. 3 (a), in the present embodiment, when predicting that processing is not carried out smoothly and can not finishing during to the target elapsed time ' ta ' when handling such situation, controlling value determining section 105 is come the processing power of enhancing signal processor 100 by following manner: by the residue treatment capacity estimated according to the amount of finishing dealing with that draws from the value of finishing dealing with 104, from treatment capacity predicted value 102 and the value of finishing dealing with 104 and by the elapsed time of indicating through information 107, in increase supply voltage and the clock frequency at least any one.
The straight line of reference number 602 indications in Fig. 3 (a) shows the prediction processing amount when signal processor 100 is carried out signal Processing with the performance of maximum.In the example shown in (a) of Fig. 3, when unless controlling value determining section 105 is determined to carry out signal Processing (at the time point shown in (a) of Fig. 3) with the maximum performance of signal processor 100, otherwise in the time of can not finishing the residue processing to the target elapsed time ' ta ', this controlling value determining section 105 changes setting value 108,109, so that the handling property of maximum signal processor 100.As a result, processing can be finished during to the target elapsed time ' ta ', therefore, true-time operation can be guaranteed.In this case, controlling value determining section 105 is from calculating the excess time up to target elapsed time ' ta ' through the elapsed time of information 107 indications, then when by will the value of finishing dealing with 104 values that obtain with treatment capacity predicted value 102 additions that in excess time, produce during less than whole treatment capacity of signal data 151, can not finish the residue processing when determining signal processor 100 to the target elapsed time ' ta '.
In this case, when signal processor 100 was carried out signal Processing with maximum performance, it is higher than common state that voltage becomes, and clock frequency becomes higher than common state.Therefore, power consumption is increased greater than common processing.As a result, shown in the solid line in Fig. 3 (b), at the time point of the handling property of maximum signal processor 100, the power consumption that needs when the control of the handling property of using signal processor 100 is increased.
In the example shown in (a) of Fig. 3, in the performance of the time point maximum signal processor 100 of indicating by reference number 603.In this case, controlling value determining section 105 can be positioned at by the time point application controls before the time point of reference number 603 indications, to increase the performance of signal processor 100.Dot-and-dash line indication treatment capacity at this moment by reference number 604 indications.When being positioned at when using such control, do not exist the performance of signal processor 100 should be increased needs to maximum by the time point before the time point of reference number 603 indication.As a result, as indicated, make the increase of power consumption and increase little than the power consumption that when the performance with signal processor 100 increases to maximum, produces at the dot-and-dash line as shown in (b) of Fig. 3.
(example 3)
Come illustrated example 3 hereinafter with reference to Fig. 4.Fig. 4 shows when handling when not carrying out smoothly respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) example of power consumption (wherein using the example of high speed processing in the interstage).As shown in Fig. 4 (a), in the present embodiment, when predicting processing when not carrying out and handling situation that the target elapsed time ' ta ' can not finish smoothly, controlling value determining section 105 is according to coming finishing of prediction processing by the treatment capacity predicted value 102 at the time point place of 701 indications of the reference number shown in Fig. 4 (a).In the present embodiment, when controlling value determining section 105 is determined signal processors 100 ' ta ' can not be finished remaining processing to the target elapsed time, controlling value determining section 105 is come the handling property of maximum signal processor 100 by supply voltage and clock frequency are increased to maximum.Then, controlling value determining section 105 the target elapsed time ' ta ' before, by the time point of the reference number shown in Fig. 4 (a) 704 indication, reduce supply voltage and clock frequency, so that described processing should be finished at target elapsed time ' ta ', and controlling value determining section 105 makes the handling property of signal processor 100 return to typical values.
In the example shown in (a) of Fig. 4, the handling property of signal processor 100 is being maintained at its maximum rating from the time point by reference number 701 indications to the time period of the time point of being indicated by reference number 704.In this case, handling property can be increased highlyer than the handling property that is set to the time point of indicating by reference number 701.But, by the time point of reference number 704 indication and after by the time point of reference number 704 indications the handling property of setting signal processor 100 finish so that handle in the time of should arriving the target elapsed time ' ta '.And, when being determined to the target elapsed time ' ta ', controlling value determining section 105 can not finish when handling, even after time point, also can increase the handling property of signal processor 100 again by reference number 704 indications.
(example 4)
At last, come illustrated example 4 hereinafter with reference to Fig. 5.Fig. 5 shows when handling when not carrying out smoothly respectively with respect to (a) the residue treatment capacity in elapsed time ' t ' and (b) example of power consumption (wherein the stage is used the example of high speed processing in early days).As shown in Fig. 5 (a), in the present embodiment, when predicting big and signal processor 100 when being set to situation about can not finish when handling the target elapsed time ' ta ' under the condition of common handling property in treatment capacity, the handling property of the time point maximum signal processor 100 that controlling value determining section 105 begins in the processing by reference number 801 indication, and signal processor 100 begins to handle.Then, controlling value determining section 105 reduces supply voltage and clock frequency at target elapsed time ' ta ' time point before, that indicated by the reference number shown in Fig. 4 (a) 802, finish so that handle in the time of to arrive the target elapsed time ' ta ', and controlling value determining section 105 makes the handling property of signal processor 100 return to typical values.
As mentioned above, according to the signal processing apparatus of present embodiment, can dynamically change supply voltage and the clock frequency that is provided to signal processor 100, the processing power of coming control signal processor 100 by estimated value and disposition in response to treatment capacity.Therefore, can realize using enough low power consumption control in the processing in real time in response to treatment capacity.
(second embodiment)
Fig. 6 shows the block scheme of the signal processing apparatus of the second embodiment of the present invention.The difference of the signal processing apparatus of the signal processing apparatus of second embodiment and first embodiment is that treatment capacity fallout predictor 101 is not provided, and replaces controlling value determining section 105 and controlling value determining section 205 is provided.Residue aspect except this aspect and among first embodiment those are similar, and to Fig. 1 in those common composed components added identical reference number.
Controlling value determining section 205 is according to treatment capacity designated value 201, the value of finishing dealing with 104 and process information 107 from the outside input, definite supply voltage that provides device 111 to provide by power supply, the setting value 108 of the determined voltage of output indication then to signal processor 100.Treatment capacity designated value 201 is the information of importing with from the signal data 151 of outside input, and the treatment capacity of indicator signal data 151.
As shown in Figure 7, signal generator 251 input signal datas 151 and the treatment capacity designated value 201 that for example provide from signal processing apparatus outside at present embodiment.Signal generator 251 corresponding to for example CD Player, DVD player, memory card reader, be used for server that comes via network the streaming distributing data etc.When signal generator 251 during corresponding to CD Player, the data processing amount of every section music of treatment capacity designated value 201 indications.In this case, with respect to the voice data of every section music, treatment capacity designated value 201 is recorded on the CD respectively.Treatment capacity designated value 201 is affixed to needs processed continuously data, such as music data or moving image data.
As mentioned above, in the signal processing apparatus of present embodiment, do not need to be provided at the treatment capacity fallout predictor 101 that comprises in the signal generation equipment of first embodiment.Therefore, can simplified structure, and can reduce power consumption.
(the 3rd embodiment)
Fig. 8 shows the block scheme of the signal processing apparatus of the third embodiment of the present invention.The difference of the signal processing apparatus of the signal processing apparatus of the 3rd embodiment and first embodiment has provided controlling value determining section 305 and has substituted controlling value determining section 105.Residue aspect except this aspect and among first embodiment those are similar.In Fig. 6, to Fig. 1 in those common composed components added identical reference number.
Controlling value determining section 305 is according to treatment capacity predicted value 102, the treatment capacity designated value of importing from the outside 201, the value of finishing dealing with 104 and process information 107 definite supply voltages that provide device 111 to provide to signal processor 100 by power supply, the setting value 108 of the determined voltage of output indication then.Treatment capacity designated value 201 has been described in a second embodiment.
The application example of signal processing apparatus in the above-described embodiments is described hereinafter with reference to Fig. 9.Fig. 9 shows the system that constitutes by broadcasting station 1501 and portable terminal 1503.Broadcasting station 1501 and portable terminal 1503 carry out (hold) with MPEG as the digital television broadcasting of mobile image encoding/decoding system etc.Broadcasting station 1501 comprises the signal generator 251 shown in Fig. 7.Portable terminal 1503 corresponding to the electronic equipment of function with receiving digital television broadcast, have the cell phone of related function etc.Portable terminal 1503 inside comprise the signal processing apparatus of the foregoing description.
Figure 10 shows the block scheme of the portable terminal 1503 of the signal processing apparatus that comprises the 3rd embodiment.As shown in Figure 10, except antenna and front-end processor 1002, portable terminal also comprises the signal processing apparatus of the 3rd embodiment.In Figure 10, the internal configurations that offers the signal processor 100 of signal processing apparatus is illustrated as mpeg decoder.In the portable terminal shown in Figure 10 1503, from stream signal extraction moving image data stream and the treatment capacity designated value 201 that receives by front-end processor 1002, then, moving image data stream is input to signal processor 100, and treatment capacity designated value 201 is input to controlling value determining section 105.
Sometimes, can not correctly receive broadcast wave, and cause to receive and disturb according to the surrounding environment of portable terminal 1503.Such as specific correction process such as the image interpolation macro block (MB) that receive to disturb that has been applied to causing of mobile image.Following form shows the treatment capacity predicted value 102 of the macro block of each type (non-coding and decoding, common, mistake).
[table 1]
| The type of macro block | Treatment capacity predicted value 102 (quantity in cycle) |
| Non-coding and decoding | ??100 |
| Usually | ??500 |
| Mistake | ??1000 |
In the above description, obtained treatment capacity predicted value 102 corresponding to the type of macro block.In this case, can be from the 104 output treatment capacity predicted values 102 of the variable-length converter the signal processor shown in Figure 10 100.
In signal processing apparatus according to the foregoing description, though when treatment capacity increase brokenly/when reducing, also dynamically use low power consumption control.Therefore, when should be carried out application such as mobile image and sound, figure, recreation etc. (its needs must at the fixed time in carry out the so real-time processing of designated treatment amount) by storage battery power supply and the electronic equipment that comprises large scale integrated circuit the time, this signal processing apparatus can be realized effect especially.
Describe the present invention in detail with reference to specific embodiment.But, for those skilled in the art, obviously under the situation that does not break away from the spirit and scope of the present invention, can use various changes and modification.
The Japanese patent application (patented claim 2007-124721 number) that the application submitted to based on May 9th, 2007, its content is comprised in this by reference.
Application on the industry
Signal processing apparatus according to the present invention is useful for the signal processing apparatus that can control disposal ability and low-power consumption in the real-time operation of finishing that guarantees realization designated treatment in the scheduled time.
Claims (8)
1. signal processing apparatus comprises:
Signal processor is used for input signal data is carried out signal Processing, with the output result data;
Power supply provides device, and being used for provides power supply to described signal processor;
Clock provides device, and being used for provides clock to described signal processor;
The treatment capacity fallout predictor is used for predicting according to described signal data the treatment capacity of described signal processor, with output treatment capacity predicted value;
The treatment capacity viewer is used to observe the treatment capacity by the signal Processing of described signal processor execution, with the output value of finishing dealing with; And,
The controlling value determining section, be used for according to from the treatment capacity predicted value of described treatment capacity fallout predictor output, from the value of finishing dealing with of described treatment capacity viewer output with indicate from the process information that begins institute's elapsed time of the signal Processing of described signal processor, determine to be provided the power source voltage that device is provided to described signal processor and will be provided device to provide to the frequency of the clock of described signal processor by described clock by described power supply
Wherein, described power supply provides the power supply that device is adapted to be provides its voltage to be determined by the controlling value determining section to described signal processor, and described clock provides the clock that device is adapted to be provides its frequency to be determined by the controlling value determining section to described signal processor.
2. signal processing apparatus comprises:
Signal processor is used for input signal data is carried out signal Processing, with the output result data;
Power supply provides device, and being used for provides power supply to described signal processor;
Clock provides device, and being used for provides clock to described signal processor;
The treatment capacity viewer is used to observe the treatment capacity by the signal Processing of described signal processor execution, with the output value of finishing dealing with; And,
The controlling value determining section, be used for according to input treatment capacity designated value, from the value of finishing dealing with of described treatment capacity viewer output with indicate from the process information that begins institute's elapsed time of the signal Processing of described signal processor, come to determine to be provided the power source voltage that device is provided to described signal processor and will be provided device to be provided to the frequency of the clock of described signal processor by described clock by described power supply
Wherein, described power supply provides the power supply that device is adapted to be provides its voltage to be determined by the controlling value determining section to described signal processor, and described clock provides the clock that device is adapted to be provides its frequency to be determined by the controlling value determining section to described signal processor.
3. according to the signal processing apparatus of claim 1 or 2,
Wherein, described signal processor is in response to the power source voltage that provides device to provide from described power supply and the frequency of the clock that device provides is provided from described clock, carry out signal Processing with the pattern of from a plurality of patterns, selecting, in described a plurality of patterns, the handling capacity of the signal Processing of time per unit is different separately, and
Wherein, described controlling value determining section:
From described through information calculations up to needed excess time in target elapsed time, be expected at the described target elapsed time to finish the signal Processing of the input signal data in described signal processor, and
When being scheduled to regularly, by value that the treatment capacity predicted value in the described value of finishing dealing with and the processing that will carry out in described excess time or the addition of treatment capacity designated value are obtained during less than total treatment capacity of signal data, determine that described signal processor can not finish signal Processing to described target during the elapsed time, and controlling described power supply provides device and described clock that device is provided so that described signal processor is carried out signal Processing with second pattern, and the handling capacity of the time per unit of described second pattern is greater than first pattern of selecting in the normal state.
4. according to the signal processing apparatus of claim 3,
Wherein, the described signal processor of just determining to carry out signal Processing with described second pattern when described controlling value determining section is when target has been finished described signal Processing during the elapsed time, described controlling value determining section is controlled described power supply provides device and described clock that device is provided, make described signal processor carry out signal Processing with three-mode, the handling capacity of the time per unit of described three-mode is less than described first pattern or described second pattern.
5. according to the signal processing apparatus of claim 1 or 2,
Wherein, described signal processor be adapted to be when described input signal data corresponding to the indication mobile image data the time, the described input signal data of decoding, and
Wherein, described controlling value determining section is adapted to be and controls described power supply in response to the type of indication frame of described mobile image or macro block and provide device and described clock that device is provided.
6. according to the signal processing apparatus of claim 1 or 2,
Wherein, described signal processor be adapted to be when described input signal data corresponding to by the data of variable length coding system compression the time, carry out the length-changeable decoding of described input signal data, and
Wherein, described controlling value determining section is adapted to be and controls described power supply in response to the variable quantity of data length and provide device and described clock that device is provided.
7. signal processing system comprises:
Signal processing apparatus according to claim 2; And
The treatment capacity designated equipment is used for exporting the treatment capacity designated value that is imported into described signal processing apparatus.
8. according to the signal processing system of claim 7,
Wherein, described treatment capacity designated equipment is adapted to be to read and is used to store the signal data that is imported into described signal processing apparatus and the recording medium of treatment capacity designated value, and exports described signal data and described treatment capacity designated value.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007124721A JP2008282150A (en) | 2007-05-09 | 2007-05-09 | Signal processor and signal processing system |
| JP124721/2007 | 2007-05-09 | ||
| PCT/JP2008/001003 WO2008139685A1 (en) | 2007-05-09 | 2008-04-16 | Signal processor and signal processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101681192A true CN101681192A (en) | 2010-03-24 |
Family
ID=40001911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200880015375A Pending CN101681192A (en) | 2007-05-09 | 2008-04-16 | Signal processor and signal processing system |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20100131791A1 (en) |
| JP (1) | JP2008282150A (en) |
| CN (1) | CN101681192A (en) |
| WO (1) | WO2008139685A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103345382A (en) * | 2013-07-15 | 2013-10-09 | 郑州师范学院 | CPU+GPU group nuclear supercomputer system and SIFT feature matching parallel computing method |
| CN104112032A (en) * | 2013-04-22 | 2014-10-22 | Nxp股份有限公司 | A Clock Control Circuit And Method |
| WO2015062504A1 (en) * | 2013-10-29 | 2015-05-07 | 华为终端有限公司 | Power consumption control method and terminal |
| CN107110672A (en) * | 2014-11-14 | 2017-08-29 | 夏普株式会社 | Signal processing apparatus, signal processing method and computer program |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010277350A (en) * | 2009-05-28 | 2010-12-09 | Toshiba Corp | Electronic device |
| JP5836585B2 (en) * | 2010-02-09 | 2015-12-24 | キヤノン株式会社 | Data processing apparatus, control method therefor, and program |
| JP2013527516A (en) * | 2010-03-26 | 2013-06-27 | バーチャルメトリックス・インコーポレイテッド | Fine-grained performance resource management for computer systems |
| US8782653B2 (en) | 2010-03-26 | 2014-07-15 | Virtualmetrix, Inc. | Fine grain performance resource management of computer systems |
| US8677071B2 (en) | 2010-03-26 | 2014-03-18 | Virtualmetrix, Inc. | Control of processor cache memory occupancy |
| KR102114453B1 (en) | 2013-07-19 | 2020-06-05 | 삼성전자주식회사 | Mobile device and control method thereof |
| US9450571B2 (en) * | 2014-06-03 | 2016-09-20 | Arm Limited | Data and clock signal voltages within an integrated circuit |
| TWI775109B (en) * | 2020-07-14 | 2022-08-21 | 宏碁股份有限公司 | Electronic apparatus and power management method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000122747A (en) * | 1998-10-12 | 2000-04-28 | Nec Corp | Device and method for controlling digital signal processing part |
| JP3880310B2 (en) * | 2000-12-01 | 2007-02-14 | シャープ株式会社 | Semiconductor integrated circuit |
| WO2002050645A1 (en) * | 2000-12-20 | 2002-06-27 | Hitachi, Ltd. | Electronic circuit of low power consumption, and power consumption reducing method |
| JP3864859B2 (en) * | 2002-06-24 | 2007-01-10 | 株式会社日立製作所 | Semiconductor device or program for reducing power consumption of the semiconductor device |
-
2007
- 2007-05-09 JP JP2007124721A patent/JP2008282150A/en not_active Withdrawn
-
2008
- 2008-04-16 CN CN200880015375A patent/CN101681192A/en active Pending
- 2008-04-16 US US12/595,994 patent/US20100131791A1/en not_active Abandoned
- 2008-04-16 WO PCT/JP2008/001003 patent/WO2008139685A1/en active Application Filing
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112032A (en) * | 2013-04-22 | 2014-10-22 | Nxp股份有限公司 | A Clock Control Circuit And Method |
| CN104112032B (en) * | 2013-04-22 | 2017-05-10 | Nxp股份有限公司 | A Clock Control Circuit And Method |
| CN103345382A (en) * | 2013-07-15 | 2013-10-09 | 郑州师范学院 | CPU+GPU group nuclear supercomputer system and SIFT feature matching parallel computing method |
| WO2015062504A1 (en) * | 2013-10-29 | 2015-05-07 | 华为终端有限公司 | Power consumption control method and terminal |
| CN107110672A (en) * | 2014-11-14 | 2017-08-29 | 夏普株式会社 | Signal processing apparatus, signal processing method and computer program |
| CN107110672B (en) * | 2014-11-14 | 2019-11-19 | 夏普株式会社 | Signal processing apparatus, signal processing method and computer program |
Also Published As
| Publication number | Publication date |
|---|---|
| US20100131791A1 (en) | 2010-05-27 |
| WO2008139685A1 (en) | 2008-11-20 |
| JP2008282150A (en) | 2008-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101681192A (en) | Signal processor and signal processing system | |
| EP1949203B1 (en) | Using historic load profiles to dynamically adjust operating frequency and available power to a handheld multimedia device processor core | |
| US7694160B2 (en) | Method and apparatus for optimizing power consumption in a multiprocessor environment | |
| CN101539799B (en) | System and method for selecting optimal processor performance level by using processor hardware feedback mechanism | |
| US9778731B2 (en) | Method for performing system power budgeting within electronic device, and associated apparatus | |
| KR20100026989A (en) | Energy-efficient multi-core processor | |
| EP1956465A2 (en) | Power aware software pipelining for hardware accelerators | |
| CN107610039A (en) | Image processing method and image processing apparatus | |
| US20110072420A1 (en) | Apparatus and method for controlling parallel programming | |
| EP2622894A1 (en) | System, apparatus and method for measuring the effectiveness of a workload predictor on a mobile device | |
| CN110245061B (en) | Computing device, power consumption prediction method thereof, and computer-readable storage medium | |
| CN107465929A (en) | DVFS control methods, system, processor and storage device based on HEVC | |
| EP1611498B1 (en) | Branch based activity monitoring | |
| CN110297743B (en) | Load testing method and device and storage medium | |
| CN103389413B (en) | A kind of real-time statistical method of spectral histogram | |
| US8555091B2 (en) | Dynamic power state determination of a graphics processing unit | |
| CN101542598B (en) | Data processor | |
| US20190094931A1 (en) | ENERGY HARVESTING and AMBIENT CONDITION TRACKING in IoT for ADAPTIVE SENSING and SELF-MODIFYING APPLICATIONS | |
| CN102067064A (en) | Data processing device with adjustable performance level and method of operating such device | |
| CN102804136B (en) | Sub-processor, Integrated Circuit Device, and Electronic Apparatus | |
| US20100262756A1 (en) | Method for writing to and erasing a non-volatile memory | |
| CN113692177B (en) | Control method, device and terminal for power consumption of refrigeration system of data center | |
| KR101574433B1 (en) | Method and Apparatus for Optimal Dynamic Voltage Scaling in Buffered Video Playback | |
| CN101454834A (en) | Contents reproducing device | |
| KR100813267B1 (en) | Method and apparatus to set transfer unit of data process system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20100324 |