CN101674073A - Self-adapting amplitude-limiting output intersymbol interference suppression circuit for differential voltage signal with low oscillation amplitude - Google Patents
Self-adapting amplitude-limiting output intersymbol interference suppression circuit for differential voltage signal with low oscillation amplitude Download PDFInfo
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Abstract
The invention discloses method and circuit for decreasing intersymbol interference by an amplitude-limiting output means, which aim at the problem that a differential voltage signal with high speed and low oscillation amplitude is easy to generate the intersymbol interference in the transmission process. By monitoring the magnitude of a differential model level of a differential output end, the output alternating current is controlled by feedback, thereby restricting the differential model level value of the differential output end within a specified level range, avoiding the influence of an oversize signal differential oscillation amplitude on a subsequent signal and realizing the purpose of decreasing the intersymbol interference. The circuit device comprises a head controlled current source, a current direction selector, a tail controlled current source, a common-mode level feedback control circuit and an output differential model level feedback control circuit. The output end of the circuit is connected with a transmission path and is connected to the load of a receiving end by the transmission path.
Description
Technical field
The invention belongs to high-speed-differential serial signal transmission field, be specifically related to the Method and circuits that a kind of technology of utilizing restriction to export the differential mode level suppresses intersymbol interference in the transmission of high-speed-differential serial signal.
Background technology
Low amplitude of oscillation differential voltage signal transmission (Low-Voltage Differential Signaling, LVDS) be (the Institute of Electrical and Electronics Engineers of IEEE-USA, IEEE) industry standard of formulating in 1996 is called IEEE 1596.3 again.
The differential swings of IEEE 1596.3 standard code LVDS signals is between 250mV to 400mV, but because the low-pass characteristic of transmission channel, in the consecutive identical signal of transmission, can cause the differential mode voltage amplitude of oscillation of output signal to present the trend that increases gradually, make the transfer station of subsequent symbol signal on the basis of bigger anti-phase differential mode level, this transmission to the subsequent symbol signal will cause adverse effect, may have a strong impact on the time width and the differential mode level of subsequent symbol signal, promptly produced intersymbol interference (Inter Symbol Interference, ISI).
Generally speaking, the technology of the elimination intersymbol interference ISI that adopts at the lvds driver end is preemphasis (Pre-Emphasis) technology.Pre-emphasis technique is promptly strengthened the high fdrequency component at signal saltus step edge by the hopping edge of signal for faster, to adapt to the low-pass effect of transmission channel.Pre-emphasis technique only exerts an influence to signal saltus step edge, the signal quality in the time of can't improving the transmission of consecutive identical code element, and pre-emphasis technique need flow through the transient current of transmission channel in signal saltus step edge increase simultaneously, is unfavorable for power consumption control.
Summary of the invention
In general, transmission channel all shows low-frequency filter characteristics, can make that the high fdrequency component in the signal that sends decays rapidly, and less to the influence of low frequency component, saltus step edge in the signal that i.e. decay sends, and make that constant signal passes through with less consumption continuously.Therefore when the signal saltus step of transmission during than horn of plenty, will hinder the saltus step of signal, limiting case is for sending " 01010101 ... 01010 " sequence, high fdrequency component in the transmitted stream signal is the abundantest at this moment, therefore decay is also serious, when showing as transmission " 010101 ... 01010 " sequence, the differential mode level of signal is less.Same, saltus step in the signal that sends more after a little while, the decay that signal is subjected to is less, limiting case is for sending long " 0 " or long " 1 " sequence, this moment, transmitted stream signal medium and low frequency component was the abundantest, therefore decay is also minimum, shows as when sending long " 0 " or long " 1 " sequence, and the differential mode level of signal presents the trend that becomes big.Based on this phenomenon, when the sequence that sends when be that " 1 " or long " 1 " are follow-up for long " 0 " is follow-up be " 0 ", after sending long " 0 " or long " 1 ", the differential mode of differential signal reaches very big value, the transmission that this has just had a strong impact on follow-up " 1 " or " 0 " makes the transmission table of this follow-up signal reveal very little differential mode level and symbol time width.
At the problems referred to above, the objective of the invention is to, for adapting to the low-pass characteristic of transmission channel, when the less and low-frequency component of the radio-frequency component of the signal that needs drive is more, the adaptive drive current that reduces, thereby make that the differential mode level of the differential signal of driver output remains in the suitable scope in the whole signals transmission, thereby reduced interference, reach the purpose that suppresses intersymbol interference the subsequent symbol signal.
The composition of the low-and high-frequency component in the adaptive monitoring output signal is that the size by monitoring output signal differential mode level realizes that the adaptive drive current that reduces is then realized by controlling first controlled current source.
As shown in Figure 1, output differential mode level feed-back control circuit 5 is the differential mode level that are used for monitoring the output differential signal, and generation feedback thus, be used to control the operating current of whole driver, thereby the differential mode level of restriction output signal, make and all enjoy identical initial condition when follow-up signal transmits at any time, thereby reach the purpose that reduces intersymbol interference.Owing to changed drive current dynamically, must make the common mode electrical level of output differential signal change, therefore regulate the operating current of tail current source by common mode electrical level feedback control circuit 4, form feedback, common mode electrical level is compensated.
Advantage of the present invention is:
1. just consider that at the lvds driver end size of differential mode level of output is to the influence of intersymbol interference, the method of use preemphasis is no longer simply come the signal for faster edge, but introduce adaptive control method, utilize differential mode level value FEEDBACK CONTROL drive current, thereby realize the purpose of amplitude limit output.
2. because intersymbol interference is suppressed to a great extent, can fundamentally improve the bandwidth of operation and the frequency of lvds driver.
3. the operating current of first current source is made up of two parts, shown in b part among Fig. 3, given static working current basic value, M0 provides by tube of current, variable partition is provided by tube of current M1, the electric current sum of M0 and M1 satisfies the transmission current needs under the maximum situations of output high fdrequency component, change after the M1 state, the electric current sum of M0 and M1 only satisfies output low frequency component needs more for a long time, thereby realize digital on-off mode control, simplified the design difficulty of a part differential mode level feed-back control circuit among Fig. 3.
4. the electric current of whole driver only just reaches maximum when the radio-frequency component that sends signal enriches, and is the strategy of taking to reduce drive current when low-frequency component enriches, and therefore can utilize electric current to the full extent, reduces the power consumption of whole driver.
5. for adapting to the dynamic change of operating current, adopt the common mode electrical level Sampling techniques of succinct resistance mode, and the method for feedback regulation tail current source operating current compensates the common mode electrical level of keeping output signal based on this, circuit form is simply effective.
Description of drawings
Fig. 1 has the LVDS drive circuit block diagram of adaptive amplitude-limiting output;
The LVDS driving circuit structure that Fig. 2 IEEE 1596.3 provides;
Fig. 3 has the circuit structure of the lvds driver of adaptive amplitude-limiting output;
Fig. 4 has the work wave of the lvds driver of adaptive amplitude-limiting output.
Embodiment
Below in conjunction with accompanying drawing, describe the structure and the course of work of self adaptation LVDS amplitude limit output driver disclosed by the invention in detail.
Figure 3 shows that codan between the adaptive amplitude-limiting output code that is used for low amplitude of oscillation differential voltage signal (LVDS) interface disclosed by the invention.Circuit among Fig. 3 comprises six parts, wherein transmission channel f and receiving terminal load g form peripheral circuit jointly, and first controlled current source b, output differential mode level feed-back control circuit a, sense of current selector d, tail controlled current source c, common mode electrical level feedback control circuit e form the lvds driver circuit jointly.
First controlled current source b is made up of two parts, tube of current M0 is the steady job mode, for output provides a fixing element task electric current I 0, tube of current M1 is exported the control of differential mode level feed-back control circuit a, adaptive operating current I1 is provided, and I0 and I1 sum provide drive current for output jointly.First controlled current source b power end, it is the source electrode of M0 and M1, connect power supply VDD, static control end Vb1, the i.e. grid of M0, connect a fixed bias level, the dynamic control end Vb2 of self adaptation, promptly the grid of M1 connects the output of output differential mode level feed-back control circuit a, current output terminal, i.e. the drain electrode of M0 and M1 is connected the input of sense of current selector.
Output differential mode level feed-back control circuit a is made up of three parts, operational amplifier OPa, resistance R 3, R4, R5, R6 form first differential mode voltage calculator, operational amplifier OPb, resistance R 7, R8, R9, R10 form second differential mode voltage calculator, these two Voltage Calculators are by the absolute calculation circuit of diode D0, D1 formation differential mode voltage, and comparator OPc constitutes differential mode voltage judgement comparator.Among the output differential mode level feed-back control circuit a, one end of resistance R 3 connects difference output end OUT-, the other end connects in-phase input end and the resistance R 4 of OPa, the other end ground connection of R4, one end of resistance R 5 connects difference output end OUT+, the other end connects inverting input and the resistance R 6 of OPa, the output of another termination OPa of R6 and the anode of diode D0; One end of resistance R 7 connects difference output end OUT-, the other end connects inverting input and the resistance R 8 of OPb, the other end ground connection of R8, one end of resistance R 9 connects difference output end OUT+, the other end connects in-phase input end and the resistance R 10 of OPb, the output of another termination OPb of R10 and the anode of diode D1; The negative pole of diode D0 links to each other with the negative pole of diode D1, and is connected to the inverting input of comparator OPc, and the in-phase input end of OPc meets a fixed reference level Vref2, and the output of OPc is connected to the control end Vb2 of first controlled current source b.
Sense of current selector d is made up of transistor M3, M4, M5, M6 and resistance R 0, R1, and transistor work and on off state are used to select the flow direction of output current, and the network that resistance R 1 and R2 constitute is used for obtaining in real time the common mode electrical level of output signal.Among the sense of current selector d, transistor M3, the current output terminal of the first controlled current source b of source termination of M4, M3, the grid of M5 is connected to the in-phase end IN+ of input differential signal, M4, the grid of M6 is connected to the end of oppisite phase IN-of input differential signal, the drain electrode of M3 connects the end of oppisite phase OUT-of difference output, the drain electrode of M5 and resistance R 1, the drain electrode of M4 connects the in-phase end OUT+ of difference output, the drain electrode of M6 and resistance R 2, the other end of the other end of resistance R 1 and resistance R 2 links to each other and is connected to the sampled level input of common mode electrical level feedback control circuit e as common mode sampled point output, and the source electrode of M5 and M6 links to each other and is connected to the current input terminal of tail controlled current source c.
Tail controlled current source c is made of transistor M2, and M2 serves as the common mode electrical level of tube of current control differential output signal.The source ground VSS of M2 wherein, the drain electrode of M2 connects the electric current outflow end of current reversal selector d, i.e. the source electrode of transistor M5 and M6, the grid of M2 connects the output of common mode electrical level feedback control circuit e.
Common mode electrical level feedback control circuit e is made of comparator OPd, the in-phase input end of OPd connects a fixed reference level Vref1, the inverting input of OPd connects the common mode sampled point of sense of current selector, be the tie point of resistance R 1 and R2, the output of OPd is connected to the grid of M2 among the tail controlled current source c as the output of common mode electrical level feedback control circuit e.
The end of transmission channel f connects the output OUT+ and the OUT-of sense of current selector respectively, and the other end connects receiving terminal load g.
The course of work of circuit can be divided into two kinds of situations and set forth, first kind for sending " 01010101 ... 01010 " sequence, second kind is " 1 " (long " 1 " is follow-up to be " 0 ") sequence for sending long " 0 " follow-up, the process of transmitting of random sequence can be split as and send long " 0 " follow-up certain combination for " 1 " (long " 1 " is follow-up to be " 0 ") sequence and transmission " 01010101 ... 01010 " sequence, so its course of work is between both of these case.
When sending " 01010101 ... 01010 " sequence, because output signal medium-high frequency composition is the abundantest, because the low-pass characteristic of transmission channel f, the decay of output signal is the most serious, the differential mode level that shows as the output differential signal is limited in the small range, this moment OUT+ and OUT-the absolute value of difference | the maximum of OUT+-OUT-| is less, promptly through among the output differential mode level feed-back control circuit a first, the second differential mode voltage calculator is tried to achieve differential mode voltage and through diode D0, signal level after the D1 rectification is less than fixed reference level Vref2, the output level of comparator OPc is a low value, starting current pipe M1 is difference output power supply with bigger electric current, and the difference output current reaches maximum I0+I1.At this moment, the differential level amplitude of oscillation of output is limited in the scope of IEEE 1596.3 standards.
Sending when long " 0 " is follow-up to be " 1 " (long " 1 " is follow-up to be " 0 ") sequence, is that example illustrates its course of work to send long " 0 " follow-up for " 1 " here.Because before sending " 1 " signal, contain abundant low-frequency component in length " 0 " signal that sends, if the electric current of differential output signal is not controlled, it is less that output signal is subjected to the decay of transmission channel so, its differential swings just will reach higher level value, and the differential mode level value that shows as the output differential signal is bigger.After having increased output differential mode level feed-back control circuit a, when the differential mode level value of exporting differential signal is big, this moment OUT+ and OUT-the absolute value of difference | OUT+-OUT-| is also bigger, surpassed given threshold level Vref2, promptly through among the output differential mode level feed-back control circuit a first, the second differential mode voltage calculator is tried to achieve differential mode voltage and through diode D0, signal level after the D1 rectification is greater than fixed reference level Vref2, this moment, the output level of comparator OPc was high value, regulating tube of current M1 is difference output power supply with the less current, difference output current I0+I1 is subject to a less value, thereby the differential level amplitude of oscillation of output is limited in the scope of IEEE 1596.3 standards.
The benefit of doing like this is, send random bit stream or regular " 01010101 ... 01010 " sequence no matter be, each symbol signal is before sending, the differential mode level of output signal all is controlled on the identical level value on the transmission channel, thereby make the transmission of each code element obtain identical initial condition, fundamentally reduced intersymbol interference ISI.
Owing to regulated the operating current of output differential signal dynamically, limited the undue increase of differential mode level, certainly will will influence the common mode electrical level value of output signal, therefore constitute the common mode electrical level compensation circuit by tail controlled current source c and common mode electrical level feedback control circuit e.Utilize the resistor network of resistance R 1 and R2 composition, obtain the common mode electrical level of output signal in real time, and compare with reference level Vref 1, the tube of current M2 among the tail controlled current source c is directly controlled in the output of comparator OPd, thus the common mode electrical level of control output signal.When the output common mode level was big, the output level of comparator OPd reduced, and reduced the conducting resistance of M2, reduced the common mode electrical level of output signal; When the output common mode level hour, the output level of comparator OPd raises, and increases the conducting resistance of M2, improves the common mode electrical level of output signal, and the common mode electrical level of output signal is stabilized on the level that needs the most at last.
Fig. 4 has provided and has used before and after the circuit disclosed by the invention, the difference of the signal of lvds driver output.As can be seen from the figure, because application of the present invention has effectively limited the increase of differential mode level, suppressed intersymbol interference.
Claims (1)
1, a kind of method comprises:
At the problem that occurs intersymbol interference in high speed low-swing difference signal (LVDS) transmission course easily, utilization limits the differential mode level of output differential signal, the influence of avoiding excessive signal differential voltage that follow-up signal is transmitted, thus intersymbol interference (ISI) reduced; It is characterized in that: in high speed low-swing difference signal (LVDS) drive circuit, use first controlled current source (1), and increase output differential mode level feed-back control circuit (5), the power end of first controlled current source (1) is connected to power vd D, output is connected to sense of current selector (2), control end links to each other with the output of output differential mode level feed-back control circuit (5), the differential level input of output differential mode level feed-back control circuit (5) is connected to the difference output end of whole drive circuit, the output of output differential mode level feed-back control circuit (5) links to each other with the control end of first controlled current source (1), the difference output end of sense of current selector (2) promptly is the differential signal output of whole driver, input with output differential mode level feed-back control circuit (5), the input of transmission channel (6) connects altogether, the common mode electrical level sampling output point of sense of current selector (2) links to each other with the common mode input of common mode level feed-back control circuit (4), the electric current outflow end of sense of current selector (2) links to each other with the input of tail controlled current flow source circuit (3), the common mode input of common mode electrical level feedback control circuit (4) links to each other with the common mode electrical level sampling output point of sense of current selector (2), the output of common mode electrical level feedback control circuit (2) is connected to the control end of tail controlled current flow source circuit (3), the input of tail controlled current flow source circuit (3) is connected to the electric current outflow end of sense of current selector (2), output is connected to ground VSS, control end links to each other with the output of common mode level feed-back control circuit (2), the input of transmission channel (6) is connected to the differential signal output of sense of current selector (2), and the output of transmission channel (6) links to each other with receiving terminal load (7).
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| CN104660246A (en) * | 2015-02-07 | 2015-05-27 | 中国科学技术大学先进技术研究院 | Receiver, differential receiver and analog front end circuit for high-speed serial interface |
| CN105703751A (en) * | 2014-11-26 | 2016-06-22 | 成都振芯科技股份有限公司 | MLVDS driver enabling constant differential output voltage |
| CN110086346A (en) * | 2018-01-25 | 2019-08-02 | 恩智浦有限公司 | Device and method for dual output resonance converter |
| CN110444140A (en) * | 2018-05-03 | 2019-11-12 | 联咏科技股份有限公司 | Integrated circuit and its anti-interference method |
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| US10804924B2 (en) | 2019-01-24 | 2020-10-13 | Media Tek Singapore Pte. Ltd. | Systems for reducing pattern-dependent inter-symbol interference and related methods |
| CN112542956A (en) * | 2020-12-08 | 2021-03-23 | 东南大学 | Wide dynamic range self-biased differential drive rectifier circuit |
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- 2009-06-09 CN CN200910043638A patent/CN101674073A/en active Pending
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| CN105703751A (en) * | 2014-11-26 | 2016-06-22 | 成都振芯科技股份有限公司 | MLVDS driver enabling constant differential output voltage |
| CN104660246A (en) * | 2015-02-07 | 2015-05-27 | 中国科学技术大学先进技术研究院 | Receiver, differential receiver and analog front end circuit for high-speed serial interface |
| CN104660246B (en) * | 2015-02-07 | 2019-05-07 | 中国科学技术大学先进技术研究院 | Receiver, differential receivers and analog front circuit for HSSI High-Speed Serial Interface |
| CN110086346A (en) * | 2018-01-25 | 2019-08-02 | 恩智浦有限公司 | Device and method for dual output resonance converter |
| CN110444140A (en) * | 2018-05-03 | 2019-11-12 | 联咏科技股份有限公司 | Integrated circuit and its anti-interference method |
| US10804924B2 (en) | 2019-01-24 | 2020-10-13 | Media Tek Singapore Pte. Ltd. | Systems for reducing pattern-dependent inter-symbol interference and related methods |
| TWI710219B (en) * | 2019-01-24 | 2020-11-11 | 新加坡商聯發科技（新加坡）私人有限公司 | Systems for reducing pattern-dependent inter-symbol interference and related methods |
| CN111628666A (en) * | 2019-02-28 | 2020-09-04 | 台达电子企业管理（上海）有限公司 | Control method of multilevel converter and multilevel converter |
| CN111628666B (en) * | 2019-02-28 | 2021-04-13 | 台达电子企业管理（上海）有限公司 | Control method of multilevel converter and multilevel converter |
| US11245341B2 (en) | 2019-02-28 | 2022-02-08 | Delta Electronics (Shanghai) Co., Ltd | Control method of multilevel converter and the multilevel converter |
| CN112542956A (en) * | 2020-12-08 | 2021-03-23 | 东南大学 | Wide dynamic range self-biased differential drive rectifier circuit |
| CN114487570A (en) * | 2022-04-02 | 2022-05-13 | 深圳中宝新材科技有限公司 | Method and system for removing interference of fusing current test level of gold bonding wire welding equipment |
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Open date: 20100317 |