CN101673767B - Semiconductor device with increased channel area and method for manufacturing the same - Google Patents
Semiconductor device with increased channel area and method for manufacturing the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region.
Description
The application's dividing an application that be the title submitted on March 27th, 2007 for No. the 200710086976.5th, the one Chinese patent application of " semiconductor device and manufacturing approach thereof " with channel area of increase.
Cross-reference to related applications
The present invention's requirement respectively on 03 31st, 2006 and korean patent application 10-2006-0029870 number of submission on December 08th, 2006 and the priority of 10-2006-0124736 case, is incorporated into for your guidance in full.
Technical field
The present invention relates to semiconductor device, more specifically relate to the semiconductor device and the manufacturing approach thereof of raceway groove (channel) area with increase.
Background technology
Generally for semiconductor device, because microminiaturization has reduced design rule, so the boron concentration in the channel region increases, and this causes electric field to increase.This situation is obvious especially in dynamic random access memory (DRAM) unit and plane N-channel metal-oxide semiconductor field effect transistor (NMOSFET).Therefore, often be difficult to obtain acceptable refreshing (refresh) time.
Because the extensive integrated cause of semiconductor device (for example DRAM), characteristic size is tending towards reducing, and doping content is tending towards increasing simultaneously.This increase causes the electric field of semiconductor device to increase, yet the increase of electric field also makes junction leakage increase.
In addition, because channel length and width often are restricted, therefore increase the ground using channel day by day and mix to satisfy required technical characterictic.As a result, electron mobility reduces probably, and the decline of this mobility makes and is difficult to obtain required current flow through raceway groove.
Figure 1A is the top view with semiconductor device of conventional planar formula NMOSFET, and Figure 1B illustrates in the semiconductor device shown in Figure 1A the profile along the plane that A-A ' cuts open.Shallow trench isolation is carried out on the zone of substrate 11 to form isolation structure 12 (for example, field oxide layer) from (STI) process, and gate oxide level 13 is formed on the active region 11A of the substrate 11 that is limited isolation structure 12.Plane grid PG is formed on the gate oxide level 13, and wherein each plane grid PG comprises gate electrode 14 and the hard mask 15 of grid, and the two piles up according to this order each other.In active region 11A, N-type source electrode and drain region S and D are formed on the both sides of each plane grid PG.
As previously mentioned, because plane grid PG is formed on the flat surfaces of active region 11A of substrate 11, so they often are called as the NMOSFET with planar channeling.Yet because extensive integrated cause, the planar ransistor structure usually is difficult to obtain required channel length and width, therefore, may not stop short (or narrow) channeling effect.
Recessed channel array transistor (RCAT) or FinFET are proposed and are used for overcoming above-mentioned restriction.Though the transistor arrangement of these suggestions can increase channel area through three surfaces of using active region, these structures maybe be because highly integrated and not enough so that channel area increases to a certain degree.
Summary of the invention
Particular of the present invention provides a kind of semiconductor device and manufacturing approach thereof that can maximize channel area.
According to an aspect of the present invention, a kind of semiconductor device is provided, it comprises: the three-dimensional active zone, and it comprises top surface, both side surface and basal surface; Gate insulator, it is formed on top surface, both side surface and the basal surface of said active region; And gate electrode, it is formed on the gate insulator of said active region.
According to a further aspect in the invention, a kind of manufacturing approach of semiconductor device is provided, comprises: in substrate, form groove, said groove limits the active region of substrate; The substrate of etched trench below is to be formed on first depression of the column that connects groove on the direction and provide support active region; Form the isolation structure of filling first depression and groove simultaneously; The some of etch substrate and isolation structure, expose with formation active region top surface, both side surface and basal surface second the depression; On top surface, both side surface and the basal surface of the active region that is exposed, form gate insulator; With on gate insulator, form gate electrode to be surrounded with source region.
In one embodiment, a kind of method of making semiconductor device comprises: on substrate, be formed with source region, said active region has the first, second, third and the 4th surface that limits the first, second, third and the 4th raceway groove.Form gate insulator to isolate the said first, second, third and the 4th surface around active region.The first, second, third and the 4th surface around gate insulator and active region forms gate electrode.Said gate electrode is used for being controlled at the electric current that flows in the first, second, third and the 4th raceway groove.The first, second, third and the 4th surface that is connected with source region is polygonal structure to limit basically.This polygonal corner can be circular.
1. 1 kinds of semiconductor device of project comprise: active region, and it limits at least four surfaces, and these four surfaces comprise the first, second, third and the 4th surface; Gate insulator, it surrounds four surfaces of said active region and forms; And gate electrode, it forms the annular on four surfaces that surround said gate insulator and said active region, and wherein said active region is supported by the column that between said gate electrode, supports said active region.
Project 2. is according to the semiconductor device of project 1, wherein: said gate electrode comprises two levels parts and is limited to two vertical parts between said two levels part.
Project 3. is according to the semiconductor device of project 2, wherein:
Said active region has major axis and minor axis; And
Said gate electrode on short-axis direction around the some of said active region.
4. 1 kinds of methods of making semiconductor device of project, this method comprises: in substrate, form first and second grooves; The substrate of said first and second beneath trenches of etching is to form first depression that connects said first and second grooves; Form the isolation structure of filling said first depression and said first and second grooves; The some of etch isolates structure, with formation be limited with source region the first, second, third and the 4th the surface second the depression; On the first, second, third and the 4th surface of said active region, form gate insulator; Form gate electrode with the first, second, third and the 4th surface around said active region.
Project 5. is according to the method for project 4, and wherein the substrate of said first and second beneath trenches of etching comprises to form first depression: the sidewall near said first and second grooves forms sept; With utilize said sept as etching mask, the substrate of the said beneath trenches of isotropic etching.
Project 6. is according to the method for project 5, and wherein the substrate of said first and second beneath trenches of isotropic etching comprises use hydrogen chloride (HCl) steam.
Project 7. is wherein implemented the isotropic etching to the substrate of said first and second beneath trenches: keep the vacuum degree in 2Torr to the 200Torr scope according to the method for project 6 under following condition; The HCl vapor flow rate of 100sccm to 1000sccm; 700 ℃ to 1000 ℃ temperature; With 30 seconds to 60 seconds process time.
Project 8. also comprises according to the method for project 5: before the substrate of said first and second beneath trenches of isotropic etching, under nitrogen atmosphere, implement heat treatment.
Project 9. is according to the method for project 8, and wherein said heat treatment is implemented in 800 ℃ to 1000 ℃ temperature range.
Project 10. wherein forms sidewall spacer and comprises according to the method for project 5: form nitride base layer above the structure that forms that after forming first depression, is obtained; With on this nitride base layer, implement etch-back process.
Project 16. is according to the method for project 15, and wherein said photoresist layer comprises the polymer-based material that is selected from cycloolefin-maleic anhydride (COMA) or acrylic acid ester.
Project 17. also is included between said mask and the said pad nitride layer and forms ARC according to the method for project 14.
18. 1 kinds of methods of making semiconductor device of project, this method comprises: on substrate, be formed with source region, this active region has the first, second, third and the 4th surface that limits the first, second, third and the 4th raceway groove; Surround said active region and form gate insulator, to isolate the said first, second, third and the 4th surface; Form annular grating electrode with the first, second, third and the 4th surface that surrounds said gate insulator and said active region, wherein said active region is supported by the column that between said gate electrode, supports said active region.
Project 19. is according to the method for project 18, and wherein said gate electrode is used to be controlled at the electric current that flows in the first, second, third and the 4th raceway groove.
Project 20. wherein connects the first, second, third and the 4th surface of said active region according to the method for project 18, is polygonal structure to limit basically.
Description of drawings
Figure 1A illustrates the top view of conventional planar type NMOSFET.
Figure 1B illustrates along the semiconductor device profile of the A-A ' line of Figure 1A.
Fig. 2 A illustrates the perspective view of semiconductor device according to one embodiment of the present invention.
Fig. 2 B illustrates the profile of semiconductor device according to one embodiment of the present invention.
Fig. 3 A to 3G is the profile of manufacturing approach that the semiconductor device of another embodiment of the present invention is shown.
Fig. 4 A illustrates the perspective view of semiconductor device according to another embodiment of the invention.
Fig. 4 B illustrates the sketch map that is positioned at the contact area between active region and the gate electrode (for example, the silica-based gate electrode of polycrystalline) according to another embodiment of the invention.
Fig. 4 C is the sketch map that the different directions that is formed on four raceway grooves in the active region according to another embodiment of the invention is shown.
Embodiment
Fig. 2 A illustrates the perspective view of semiconductor device according to one embodiment of the present invention, and Fig. 2 B illustrates the profile of semiconductor device according to one embodiment of the present invention.This semiconductor device structure shows to have major axis and minor axis.Active region 100 has four surfaces, comprises top surface 101, both side surface 102 and basal surface 103.Annular grating electrode 32 is formed on the surface of the active region 100 shown in Fig. 2 A.Gate electrode 32 comprises polysilicon.
Fig. 2 B shows along the profile of the cutting planes of minor axis and long axis direction.Reference numeral 21,26,28 and 31 is represented substrate, sept, isolation structure (for example, field oxide layer) and gate insulator (for example, oxide skin(coating)) respectively.The direction of raceway groove will specify with reference to figure 4C subsequently.According to this embodiment, because four surfaces of active region 100 are used as raceway groove, so the channel area of this semiconductor device can increase to than traditional RCAT and the bigger degree of FinFET.
Fig. 3 A to 3G is the profile of manufacturing approach that the semiconductor device of another embodiment of the present invention is shown.The profile in left side adopts along the cutting planes of the short-axis direction of active region 300 among Fig. 3 A to 3F, and the profile on right side adopts along the cutting planes of the long axis direction of active region 300.
With reference to figure 3A, on substrate 231, form pad oxide skin(coating) 232 and pad nitride layer 233.Substrate 231 comprises the silicon-based substrate that contains a certain amount of impurity.Pad oxide skin(coating) 232 forms the thickness of
to
approximately, and pad nitride layer 233 forms the thickness of
to
approximately.
Photoresist layer is coated on the pad nitride layer 233 and through photoetching process and is patterned to form STI mask 234.This photoresist layer comprises the polymer-based material that contains cycloolefin-maleic anhydride (COMA) or acrylic acid ester.See from the top, STI mask 234 form bar shaped or ' T ' shape.Though do not illustrate, before forming STI mask 234, form ARC, to prevent the scattering effect in photoetching process.This ARC comprises organic material, for example the SiON sill.
Use STI mask 234 as etching mask etching pad nitride layer 233 and pad oxide skin(coating) 232, and etch substrate 231 is to certain depth.As a result, be formed for the groove 235 of isolating.Consider follow-up wet etching and oxidation, the degree of depth of each groove is all being made an appointment with
to the scope of
.Groove 235 will be the zone that is used for isolation structure, and be limited with source region 300.
With reference to figure 3B, utilize oxygen plasma to remove STI mask 234.Forming sept 236 on the two side of groove 235 with on the stack pattern structure that comprises pad oxide skin(coating) 232 and pad nitride layer 233.Sept 236 through shown in Fig. 3 A form on the structure nitride layer (not shown) and carry out etch-back process above that and form.
With reference to figure 3C, use sept 236 to implement isotropic etching as etching mask.Hydrogen chloride (HCl) steam is used to implement this etching.The result of this isotropic etching is that the horizontal expansion below groove 235 of first depression, 237 (or horizontal tunnels) forms.When long axis direction is observed, first depression 237 is sunk from the bottom of each groove 235.
Keep-up pressure about 2Torr to 200Torr and the HCl steam is flowed with about 100sccm to 1000sccm implement isotropic etching, thereby adjustment etch-rate and profile.When using the HCl steam, under about 700 ℃ to 1000 ℃ temperature, implement isotropic etching and continue about 30 seconds to 60 seconds.
Before the isotropic etching that uses the HCl steam, to the nitrogen atmosphere of 1000 ℃ of temperature ranges, implement the preannealing processing at about 800 ℃.This preannealing is handled and is implemented to remove impurity.
With reference to figure 3D, the gap is filled insulating barrier and is filled first depression 237 and groove 235, and implements cmp to form isolation structure 238 (for example, field oxide layer).Said gap is filled insulating barrier and is comprised the oxide-base material.The STI chemical mechanical planarization process is known in the art, and this grinding stops at pad nitride layer 233 places.The gap is filled insulating barrier and is filled first depression 237 and groove 235 through depositing simultaneously.As replacement scheme, can on said gap filling insulating barrier, implement thermal oxidation and cave in 237, and can implement high-density plasma (HDP) subsequently and handle with filling groove 235 to fill first.
With reference to figure 3E, utilize phosphoric acid (H
3PO
4) solution optionally remove the pad nitride layer 233.Photoresist layer is coated on the residual pad oxide skin(coating) 232 and through photoetching process and is patterned to form photoresist pattern 239.Photoresist pattern 239 comprises polymeric material for example COMA or acrylic acid ester.Photoresist pattern 239 is not formed on the residual pad oxide skin(coating) 232 on the short-axis direction.
Those open areas 239A that is opened by photoresist pattern 239 forms the line style pattern.These zones are locations of follow-up grid to be formed.Therefore; Because the cause of open area 239A; Part active region 300 fills up oxide skin(coating) 232 with part and exposes into the line style pattern on the long axis direction, and the whole part of isolation structure 238, pad oxide skin(coating) 232 and active region 300 is exposed on the short-axis direction.Here, the whole zone of active region 300 is the active regions 300 that only are positioned on the short-axis direction.
Pad oxide skin(coating) 232 makes with photoresist, and pattern 239 is etched as etching mask.The isolation structure 238 that after 232 etchings of pad oxide skin(coating), is exposed is etched to be formed for forming second depression 240 of raceway groove.On short-axis direction, pad oxide skin(coating) 232 is etched with isolation structure 238.For downward etching, implement dry ecthing up to the bottom (seeing also Fig. 3 C) that arrives first depression 237, and extra enforcement wet etching is used for lateral etches.Therefore, utilize the etching of 239 pairs of pads of photoresist pattern oxide skin(coating) 232 and isolation structure 238 to allow formation second depression 240, the second depressions 240 to circularize around (or encirclement) active region 300.
With reference to figure 3F, remove the sept 236 in second depression 240.Because sept 236 comprises nitride based materials, therefore use H
3PO
4Solution removes.Photoresist pattern 239 is removed, and next, removes the pad oxide skin(coating) 232 on the active region 300 that remains on the short-axis direction.
After removing pad oxide skin(coating) 232, four sides 301,302,303 and 304 of raceway groove expose into a complete annulus 304.
With reference to figure 3G, form gate insulator 241 above the active region 300 that after removing pad oxide skin(coating) 232, is exposed.Gate insulator 241 comprises that oxide-base material and its form through implementing thermal oxidation or deposition process.More specifically, implement heat treatment so that gate insulator 241 on active region 300 surfaces that expose with the homogeneous grown in thickness.
Polysilicon layer as transistor gate is formed on the gate insulator 241, till filling second depression 240.Though do not illustrate, have low-resistance metal-based layer and hard mask layer and be formed on the polysilicon layer 242 and be patterned to form gate pattern.This metal-based layer and hard mask layer also can comprise tungsten and nitride based materials respectively.Because gate electrode 242 with four surfaces of similar ring-type around the active region 300 that exposes, therefore forms four raceway grooves.
Fig. 4 A illustrates the perspective view of semiconductor device according to another embodiment of the invention.Particularly, Fig. 4 A is presented at the structure construction between active region 300 and the gate electrode (for example polysilicon layer 242).Active region 300 comprises the surface of four exposures, i.e. top surface 301, both side surface 302 and basal surface 303.Gate electrode 242 forms around the tubular shape on four surfaces of active region 300.Fig. 4 A shows two gate electrodes, wherein is positioned at each side of column 237A separately.Single gate electrode is around four sides of active region 300.
In the central area of active region 300, have column 237A, and gate electrode 242 is around the exposed surface of the active region 300 of column 237A both sides.Because gate electrode 242 with four exposed surfaces of similar ring-type around active region 300, therefore forms four raceway grooves.
Fig. 4 B illustrates the sketch map of the contact area between gate electrode 242 and active region 300 according to another embodiment of the invention.Fig. 4 C is the sketch map that the different directions that is formed on four raceway grooves in the active region according to another embodiment of the invention is shown.With reference to figure 4B, because gate electrode 242 with top surface 301, both side surface 302 and the basal surface 303 of annular around active region 300, therefore forms four raceway grooves shown in Fig. 4 A.In more detail, shown in Fig. 4 C, the first raceway groove CH1 is formed on the top surface 301 of active region 300.Second and triple channel CH2 and CH3 be formed on the side of both side surface 302 of active region 300.The 4th raceway groove CH4 is formed on the basal surface 303 of active region 300.
According to different embodiments of the present invention, owing to use the given surface (for example four surfaces) of active region, so channel length can be by maximization extremely than traditional RCAT and the bigger degree of FinFET with area.As a result, extensive when integrated when semiconductor device, can reduce short-channel effect.Therefore, can improve transistor characteristic.
Though the present invention is described with respect to particular, it will be apparent to one skilled in the art that the essence of the present invention and the scope that can not break away from accompanying claims and limited carry out various variations and modification.
Description of reference numerals
11 substrates
The 11A active region
12 isolation structures
13 gate oxide level
14 gate electrodes
The hard mask of 15 grids
21 substrates
26 septs
The 27A column
28 isolation structures
31 gate insulators
32 annular grating electrode
100 active regions
101 top surfaces
102 both side surface
103 basal surfaces
231 substrates
232 pad oxide skin(coating)s
233 pad nitride layers
234 shallow trench isolation masks
235 grooves
236 septs
237 first depressions
The 237A column
238 isolation structures
239 photoresist patterns
The 239A open area
240 second depressions
241 gate insulators
242 polysilicon layers
242 gate electrodes
300 active regions
301 top surfaces
302 both side surface
303 basal surfaces
304 annulus
PG plane grid
The S source region
The D drain region
CH1 first raceway groove
CH2 second raceway groove
The CH3 triple channel
CH4 the 4th raceway groove
Claims (6)
1. semiconductor device comprises:
Active region, it limits at least four surfaces, and these four surfaces comprise the first, second, third and the 4th surface;
Gate insulator, it surrounds four surfaces of said active region and forms; With
Gate electrode, it forms the annular on four surfaces that surround said gate insulator and said active region,
Wherein said active region is supported by the column that between said gate electrode, supports said active region.
2. semiconductor device according to claim 1, wherein:
Said gate electrode comprises two levels parts and is limited to two vertical parts between said two levels part.
3. semiconductor device according to claim 2, wherein:
Said active region has major axis and minor axis; And
Said gate electrode on short-axis direction around the some of said active region.
4. method of making semiconductor device, this method comprises:
On substrate, be formed with source region, this active region has the first, second, third and the 4th surface that limits the first, second, third and the 4th raceway groove;
Surround said active region and form gate insulator, to isolate the said first, second, third and the 4th surface; With
The first, second, third and the 4th surface that surrounds said gate insulator and said active region forms annular grating electrode,
Wherein said active region is supported by the column that between said gate electrode, supports said active region.
5. method according to claim 4, wherein said gate electrode are used to be controlled at the electric current that flows in the first, second, third and the 4th raceway groove.
6. method according to claim 4 wherein connects the first, second, third and the 4th surface of said active region, to be defined as polygonal structure.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060029870 | 2006-03-31 | ||
| KR10-2006-0029870 | 2006-03-31 | ||
| KR20060029870 | 2006-03-31 | ||
| KR1020060124736A KR100832017B1 (en) | 2006-03-31 | 2006-12-08 | Semiconductor device increased channel area and method for manufacturing the same |
| KR1020060124736 | 2006-12-08 | ||
| KR10-2006-0124736 | 2006-12-08 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100869765A Division CN101047206B (en) | 2006-03-31 | 2007-03-27 | Semiconductor device with increased channel area and fabrication method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN101673767A CN101673767A (en) | 2010-03-17 |
| CN101673767B true CN101673767B (en) | 2012-05-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009101785836A Expired - Fee Related CN101673767B (en) | 2006-03-31 | 2007-03-27 | Semiconductor device with increased channel area and method for manufacturing the same |
| CN2007100869765A Expired - Fee Related CN101047206B (en) | 2006-03-31 | 2007-03-27 | Semiconductor device with increased channel area and fabrication method thereof |
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| CN2007100869765A Expired - Fee Related CN101047206B (en) | 2006-03-31 | 2007-03-27 | Semiconductor device with increased channel area and fabrication method thereof |
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| Country | Link |
|---|---|
| KR (1) | KR100832017B1 (en) |
| CN (2) | CN101673767B (en) |
| TW (1) | TWI360220B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102361011B (en) | 2008-06-11 | 2016-06-22 | 美格纳半导体有限会社 | The method forming the grid of semiconductor device |
| KR101016351B1 (en) * | 2008-06-11 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method for forming recess gate of semiconductor device |
| KR101016349B1 (en) * | 2008-06-11 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method for forming triple gate of semiconductor device and triple gate of semiconductor for the same |
| US10790155B2 (en) * | 2018-06-27 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5804848A (en) * | 1995-01-20 | 1998-09-08 | Sony Corporation | Field effect transistor having multiple gate electrodes surrounding the channel region |
| US5965914A (en) * | 1997-06-18 | 1999-10-12 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor having a branched gate and channel |
| CN1503368A (en) * | 2002-11-26 | 2004-06-09 | ̨������·����ɷ�����˾ | SRAM unit with multi-grid transistor and mfg method thereof |
| CN1577850A (en) * | 2003-06-27 | 2005-02-09 | 英特尔公司 | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05218415A (en) * | 1992-01-31 | 1993-08-27 | Kawasaki Steel Corp | Semiconductor device |
| JPH05218416A (en) * | 1992-01-31 | 1993-08-27 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| US6794699B2 (en) * | 2002-08-29 | 2004-09-21 | Micron Technology Inc | Annular gate and technique for fabricating an annular gate |
-
2006
- 2006-12-08 KR KR1020060124736A patent/KR100832017B1/en not_active IP Right Cessation
- 2006-12-28 TW TW095149459A patent/TWI360220B/en not_active IP Right Cessation
-
2007
- 2007-03-27 CN CN2009101785836A patent/CN101673767B/en not_active Expired - Fee Related
- 2007-03-27 CN CN2007100869765A patent/CN101047206B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5804848A (en) * | 1995-01-20 | 1998-09-08 | Sony Corporation | Field effect transistor having multiple gate electrodes surrounding the channel region |
| US5965914A (en) * | 1997-06-18 | 1999-10-12 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor having a branched gate and channel |
| CN1503368A (en) * | 2002-11-26 | 2004-06-09 | ̨������·����ɷ�����˾ | SRAM unit with multi-grid transistor and mfg method thereof |
| CN1577850A (en) * | 2003-06-27 | 2005-02-09 | 英特尔公司 | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070098452A (en) | 2007-10-05 |
| CN101047206B (en) | 2010-04-07 |
| CN101047206A (en) | 2007-10-03 |
| KR100832017B1 (en) | 2008-05-26 |
| CN101673767A (en) | 2010-03-17 |
| TWI360220B (en) | 2012-03-11 |
| TW200737499A (en) | 2007-10-01 |
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