CN101667578B - Novel integrated circuit resisting NMOS element total dose radiation - Google Patents
Novel integrated circuit resisting NMOS element total dose radiation Download PDFInfo
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- CN101667578B CN101667578B CN2009100934157A CN200910093415A CN101667578B CN 101667578 B CN101667578 B CN 101667578B CN 2009100934157 A CN2009100934157 A CN 2009100934157A CN 200910093415 A CN200910093415 A CN 200910093415A CN 101667578 B CN101667578 B CN 101667578B
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Abstract
The invention discloses a novel integrated circuit resisting total dose radiation of N-Metal-Oxide-Semiconductor (NMOS), belonging to the technical field of electronics. The novel integrated circuit resisting total dose radiation of the NMOS comprises an NMOS element and can also comprises a PMOS element, wherein the elements are insulated by a groove on a substrate. The novel integrated circuit resisting total dose radiation of NMOS is characterized in that: in the groove adjacent to the NMOS element, an air interface layer exists between a groove filling material and a substrate material arranged at one side of the groove filling material, and another air interface layer also exists between the groove filling material and a substrate material arranged at the other side of the groove filling material. The air interface layers are formed through etching contact parts among the groove filling material and the substrate materials. The invention can be applied to spaceflight, military area, nuclear power, high energy physics and other industries relevant to total dose radiation.
Description
Technical field
The present invention relates to integrated circuit, relate in particular to a kind of new type integrated circuit, belong to electronic technology field with nmos device preventing total dose radiation.
Background technology
Integrated circuit technique being applied in the industry relevant such as space flight, military affairs, nuclear power and high-energy physics just more and more widely with total dose irradiation.And along with the improving constantly of integrated circuit integrated level, size of semiconductor device reduces day by day, and the shallow-trench isolation technology just becomes in the integrated circuit mainstream technology of electric isolation between the device with its good device isolation performance.But because the total dose irradiation particle for the damage of silicon dioxide oxide layer in the device, can produce a large amount of fixed positive charges in the oxide layer of shallow groove isolation structure.In nmos device, the existence of these a large amount of fixed positive charges can cause near the substrate transoid the shallow-trench isolation oxide layer, and formation phost line electric leakage under certain source drain bias, the size of electrical leakage quantity is closely related apart from the distance of silicon substrate with these positive charges, be that the shallow groove isolation structure material is near more apart from silicon substrate, the positive charge that produces behind the total dose irradiation is just strong more to the transoid effect of substrate, and the conducting electronics of generation is just many more, and electric leakage is just big more.Before device was responsible for unlatching, the person in charge was in OFF state, but phost line conducting at this moment forms bigger off-state leakage current.This off-state leakage current can increase power consumption of integrated circuit greatly, and the reliability of integrated circuit is produced bigger negative effect, becomes the total dose irradiation integrity problem that present stage needs to be resolved hurrily.
Therefore, if can propose under the main flow preparation technology's who does not change the shallow-trench isolation technology the prerequisite a kind of can reduce total dose irradiation after shallow-trench isolation material electropositive, and the distance between increase positive charge and the silicon substrate, suppress these electropositivies to reach, the novel isolation technology of CMOS integrated circuit and device off-state leakage current behind the final minimizing nmos device total dose irradiation will be significant to the anti-irradiation reinforcing of whole integrated circuit.
Summary of the invention
The purpose of this invention is to provide a kind of novel integrated circuit preventing total dose radiation that can reduce off-state leakage current behind the nmos device total dose irradiation.
The present invention is on the basis of existing conventional nmos device, design air layer between groove and substrate, by the insulation effect of utilizing air layer and the characteristics that not influenced by total dose irradiation, between groove and substrate, introduce an effective insulating barrier, suppress the mirror image transoid effect of fixed positive charge that total dose irradiation produces largely to the substrate charge carrier in trench fill material, the transoid charge carrier quantity of parasitic transistor raceway groove is reduced significantly, reach and reduce the parasitic transistor leakage current, reduce the effect of off-state leakage current.
Specifically, in order to reach above-mentioned technical purpose, the present invention adopts following technical scheme:
A kind of have a nmos device integrated circuit preventing total dose radiation, described integrated circuit comprises nmos device, also can comprise the PMOS device, between the described device by the trench isolations on the substrate, it is characterized in that, with described nmos device adjacent grooves in, have an air interface layer between the backing material of trench fill material and one side, also can have an air interface layer between the backing material of trench fill material and its opposite side.That is to say that in two grooves of each nmos device both sides, it still is that the PMOS device is adjacent irrelevant that this air interface layer and this nmos device and nmos device are set in the one or both sides of each groove, shown in Fig. 1 b.
Described air interface layer can form by the contact portion between described trench fill material of etching and the described backing material.
The thickness of described air interface layer is preferably in the scope of 10 to 20 nanometers.
Described trench fill material can be the conventional silicon dioxide that uses, and described backing material can be the conventional silicon that uses.
Fig. 1 a, b have shown conventional shallow-trench isolation technology and the difference of integrated circuit of the present invention one instantiation on groove structure respectively.Fig. 2 has shown that conventional shallow grooved-isolation technique structure and novel anti total dose irradiation process structure of the present invention are through producing the contrast of transoid carrier concentration behind the total dose irradiation in silicon substrate, can see in the shallow-trench isolation device architecture of routine, a large amount of fixed positive charges that total dose irradiation produces in trench fill material mirror image of can inducting in the silicon substrate that closes on goes out a large amount of transoid charge carriers, it is a large amount of electronics, these electronics leak in the source under the situation be added with bias voltage can conducting, causes just having bigger leakage current at nmos pass transistor in OFF state.Novel anti total dose irradiation process structure of the present invention mainly utilizes the insulation effect of air layer and the characteristics that not influenced by total dose irradiation, between groove and silicon substrate, introduce an effective insulating barrier, suppressed the mirror image transoid effect of fixed positive charge that irradiation produces largely to the silicon substrate charge carrier in STI district oxide layer, the transoid charge carrier quantity of parasitic transistor raceway groove is reduced significantly, reach and reduce the parasitic transistor leakage current, reduce the effect of off-state leakage current, make the anti-radiation performance of integrated circuit obtain by a relatively large margin lifting.
Compare with prior art, the novel isolation technology that can reduce off-state leakage current behind the integrated circuit nmos device total dose irradiation significantly proposed by the invention, can strengthen the preventing total dose radiation performance of integrated circuit greatly, power consumption of integrated circuit is significant with the reliability that strengthens integrated circuit under the total dose irradiation for reducing, in integrated circuit preventing total dose radiation reinforcement technique is used, remarkable advantages and application prospects are arranged.
Description of drawings
Fig. 1 shows conventional shallow-trench isolation technology and the difference of the present invention's one instantiation on groove structure, and Fig. 1 a represents routine techniques, and Fig. 1 b represents the technology of the present invention;
Fig. 2 shows that conventional shallow grooved-isolation technique structure and novel anti total dose irradiation process structure of the present invention are through producing the contrast of transoid carrier concentration behind the total dose irradiation in substrate;
Fig. 3-7 shows that embodiment prepares each step of integrated circuit.
Embodiment
In conjunction with the accompanying drawings the present invention is further described below by a concrete preparation embodiment.
Present embodiment preparation according to of the present invention based on the High-K material have a nmos device integrated circuit preventing total dose radiation, mainly comprise the steps:
1) formation of silicon dioxide and silicon nitride.As shown in Figure 3, be approximately the silicon dioxide of 100 Ethylmercurichlorendimide to 200 Ethylmercurichlorendimides as the stress-buffer layer between silicon nitride and the silicon substrate 2 at thermal oxide growth one layer thickness on the silicon substrate 1, and then with low-pressure chemical vapor phase deposition (LPCVD) method deposit one deck 1000 Ethylmercurichlorendimide to 1500 Ethylmercurichlorendimide silicon nitrides, as barrier layer 3.
2) gully photoetching for the first time and etching.As shown in Figure 4, behind figure shown in going out with first reticle lithographic definition, with reactive ion etching (RIE) method etching trapezoidal groove 4 between the MOS device, etching gas can be Cl
2, HBr, and O
2Deng, groove width is about 100 to 250 nanometers, and groove depth is about 300 nanometer to 500 nanometers, and the angle of inclination on the trapezoid limit of dovetail groove is about 75 °～89 °.
3) deposit trench fill material 5.As shown in Figure 5, use high-density plasma CVD (HDPCVD) method deposit earth silicon material to the groove 4 of step 2 etching.The ratio of etching and deposit is so-called Etch/Depo ratio, remains between 0.14～0.33 usually.
4) remove stress-buffer layer.As shown in Figure 6, with chemico-mechanical polishing (CMP), SPA boils, and methods such as rinsing are removed the stress buffer layer material.
5) gully photoetching for the second time and etching.As shown in Figure 7, behind figure shown in defining with second reticle, with reactive ion etching (RIE) method etching trapezoidal groove, etching gas can be Cl
2, HBr, and O
2Deng.At the less trapezoidal groove 8 of the both sides of the formed groove of step 4 etching, the groove depth of groove 8 is about 300 nanometer to 500 nanometers, and groove width is about 10 to 20 nanometers, and the angle of inclination on the trapezoid limit of dovetail groove is about 80 °～90 °, obtains final isolation structure.
Claims (6)
1. one kind has the nmos device integrated circuit preventing total dose radiation, described integrated circuit comprises nmos device, also can comprise the PMOS device, between the described device by the trench isolations on the substrate, it is characterized in that, with described nmos device adjacent grooves in, have an air interface layer between the backing material of trench fill material and one side.
2. integrated circuit as claimed in claim 1 is characterized in that, also has an air interface layer between the backing material of described trench fill material and its opposite side.
3. integrated circuit as claimed in claim 1 or 2 is characterized in that, described air interface layer forms by the contact portion between described trench fill material of etching and the described backing material.
4. integrated circuit as claimed in claim 1 or 2 is characterized in that the thickness of described air interface layer is in the scope of 10 to 20 nanometers.
5. integrated circuit as claimed in claim 1 or 2 is characterized in that described trench fill material is a silicon dioxide.
6. integrated circuit as claimed in claim 1 or 2 is characterized in that described backing material is a silicon.
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| CN2009100934157A CN101667578B (en) | 2009-09-30 | 2009-09-30 | Novel integrated circuit resisting NMOS element total dose radiation |
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| CN2009100934157A CN101667578B (en) | 2009-09-30 | 2009-09-30 | Novel integrated circuit resisting NMOS element total dose radiation |
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| CN101667578B true CN101667578B (en) | 2011-05-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006058210A1 (en) * | 2004-11-23 | 2006-06-01 | Alpha & Omega Semiconductor, Ltd. | Improved trenched mosfets with part of the device formed on a (110) crystal plane |
| CN101419942A (en) * | 2007-10-24 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | Groove isolation construction manufacturing method capable of enhancing performance of semiconductor device |
| US20090174008A1 (en) * | 2008-01-08 | 2009-07-09 | International Business Machines Corporation | METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING |
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2009
- 2009-09-30 CN CN2009100934157A patent/CN101667578B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006058210A1 (en) * | 2004-11-23 | 2006-06-01 | Alpha & Omega Semiconductor, Ltd. | Improved trenched mosfets with part of the device formed on a (110) crystal plane |
| CN101419942A (en) * | 2007-10-24 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | Groove isolation construction manufacturing method capable of enhancing performance of semiconductor device |
| US20090174008A1 (en) * | 2008-01-08 | 2009-07-09 | International Business Machines Corporation | METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING |
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