CN101667568B - Preparation method of refrigeration structure for three-dimensional encapsulation of micro-electronics - Google Patents
Preparation method of refrigeration structure for three-dimensional encapsulation of micro-electronics Download PDFInfo
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- CN101667568B CN101667568B CN2009103083043A CN200910308304A CN101667568B CN 101667568 B CN101667568 B CN 101667568B CN 2009103083043 A CN2009103083043 A CN 2009103083043A CN 200910308304 A CN200910308304 A CN 200910308304A CN 101667568 B CN101667568 B CN 101667568B
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- heat dissipation
- metal heat
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Abstract
The invention relates to a refrigeration structure for three-dimensional encapsulation of micro-electronics in the micro-electronic encapsulation field and a preparation method thereof. The refrigeration structure comprises two laminated chips, two longitudinal metal heat dissipation passage arrays and a transverse metal heat dissipation passage array, wherein the lower surface of an upper laminated chip and the upper surface of a lower laminated chip are respectively provided with one longitudinal metal heat dissipation passage array; the two longitudinal metal heat dissipation passage arrays are connected by the transverse metal heat dissipation passage array. The preparation method of the invention aiming at heat dissipation passages of local hot spots can selectively adopt metal material with high thermal conductivity as heat dissipation passages on one hand, and can adopt a feasible shortest heat dissipation route aiming at the local hot spots on the other hand, thus increasing the heat dissipation efficiency of the laminated high integration level chip to the largest extent. The invention has high technology integration level and is easy to realize.
Description
Technical field
What the present invention relates to is the device in a kind of microelectronics Packaging field and preparation method thereof, specifically is a kind of refrigeration structure that is used for the three-dimensional encapsulation of microelectronics and preparation method thereof.
Background technology
Follow the electronic product densification development of Moore's Law, encapsulation technology also develops towards directions such as high density, microminiaturization, multicore sheet and three dimension scales, in order to reduce package area more efficiently, developed three-dimensional stack encapsulation structure with multiple chip.Three-dimensional stacked package is made of through electrical interconnects in individual devices two or more Chip Packaging, can reduce device volume effectively, but has also brought the heat dissipation problem of high-power component simultaneously.
Existing document is retrieved discovery (Fabrication of Silicon Carriers with TSVElectrical Interconnections and Embedded Thermal Solutions for High Power 3-DPackage, adopt the high power 3-D silicon wafer-based encapsulation preparation of electrical connection of silicon through hole and embedded heat pipe reason scheme, Aibin Yu, Electronic Components and Technology Conference, (2008) 24-28), adopt the water-cooling project of chip-scale Embedded A u/Sn bonding airtight passage, realize the heat radiation of high power tridimensional electronic encapsulation.Although above-mentioned technology can solve the heat dissipation problem of high power tridimensional electronic encapsulation, still there is following problem:
Carry out the structure of water-cooling channel structure by embedded mode, make water-cooling channel directly act on the work chip, reduced the functional reliability of chip, complicated channel design has increased the probability that cold-producing medium exposes; Adopt water-cooling structure must in heat-radiation loop, consider feed mechanism, certainly will increase integrated device volume; This runs counter to the original intention that highly integrated chip reduces its device volume, therefore has the high-power component of strict demand integrated for the volume size, and embedded water-cooling pattern is also inapplicable.
Summary of the invention
The present invention is directed to the prior art above shortcomings, a kind of refrigeration structure that is used for the three-dimensional encapsulation of microelectronics and preparation method thereof is provided, for the hot localised points district provides efficiently heat dissipation channel fast, be the available heat Managed Solution of tridimensional electronic encapsulation, can improve its functional reliability.
The present invention is achieved by the following technical solutions:
The present invention relates to be used for the three-dimensional refrigeration structure that encapsulates of microelectronics comprises: two laminated chips, two longitudinal metal heat dissipation channel arrays and a transverse metal heat dissipation channel array, wherein: the upper surface of the lower surface of superimposed layer chip and following laminated chips respectively is provided with a longitudinal metal heat dissipation channel array respectively, and transverse metal heat dissipation channel array is communicated between two longitudinal metal heat dissipation channel arrays.
Described longitudinal metal heat dissipation channel array is made up of a plurality of longitudinal metal heat dissipation channels, specifically be positioned at the nonclient area top of below, described superimposed layer chip hot localised points district and described laminated chips down, the minimum spacing of a plurality of longitudinal metal heat dissipation channels is in 10 ~ 100000 mu m ranges.
Described longitudinal metal heat dissipation channel is rectangular column structure or column structure, wherein: the Diagonal Dimension of rectangular column or cylinder be diameter in 10 ~ 200 mu m ranges, rectangular column or cylinder height are in 10 ~ 1000 mu m ranges.
Described transverse metal heat dissipation channel is made up of several transverse metal heat dissipation channels, and its thickness is in 1 ~ 500 mu m range, and laterally the maximum cross-section width is in 10 ~ 100000 mu m ranges, and laterally maximum cross-section length is in 100 ~ 100000 mu m ranges.
A kind of or its combination that described transverse metal heat dissipation channel and longitudinal metal heat dissipation channel are among Cu, Au, Zn, Ag or the Ni is made.
The present invention relates to the above-mentioned preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics, may further comprise the steps:
The first step: confirm superimposed layer die hot spots district, adopt the litho pattern metallization processes to form in its corresponding region, back side and stated the hole array pattern, the back adopts dried wet-etching technology to be processed into deep hole, at hole inwall and surface sputtering metallic film as the Seed Layer of electroplating, and portion adopts the electrochemistry electroplating method to fill metal within it, can form longitudinal metal heat dissipation channel array;
Described hot zone is meant that power is output as the above chip area of 5W in the superimposed layer chip.
Described filling metal is meant a kind of or its combination among Cu, Au, Zn, Ag or the Ni.
Second step: in the bottom of longitudinal metal heat dissipation channel, be on the lower surface of superimposed layer chip, adopt sputtering seed layer, photolithography patterning and electrochemistry electroplating method to prepare the transverse metal heat dissipation channel, make heat under the prerequisite that gets around the chip operation district, arrive the cooling system of outermost with the shortest heat dissipation path;
The 3rd step, repetition second go on foot the method that adopts following laminated chips hot localised points district are carried out the preparation of transverse metal heat dissipation channel, realize that laminated chips was to the heat dissipation path of cooling system under the superimposed layer chip extremely.
In the described heat dissipation path in the longitudinal metal heat dissipation channel array each longitudinal metal heat dissipation channel its bottom or top, directly link to each other with transverse metal heat dissipation channel surface, form the solid heat dissipation channel, heat arrives longitudinal metal heat dissipation channel array from chip hot localised points district, the back arrives the transverse metal heat dissipation channel by longitudinal metal heat dissipation channel array and being connected of transverse metal heat dissipation channel, the back arrives the other end of transverse metal heat dissipation channel, arrive peripheral cooling system via the heat dissipation channel that is attached thereto (can continue is the longitudinal metal heat dissipation channel), or directly arrive peripheral cooling system, finally finish heat dissipation; The heat heat dissipation path of forming by longitudinal metal heat dissipation channel and transverse metal heat dissipation channel at chip hot localised points district, represented from chip hot localised points district and arrived peripheral cooling system, and guaranteed in diabatic process, to avoid through causing the shortest path in the zone that chip can't operate as normal.
The invention has the beneficial effects as follows, preparation method at the heat dissipation channel in hot localised points district, can selectively adopt the high heat conductivity metal material as heat dissipation channel on the one hand, adopt the shortest feasible heat dissipation path at the hot localised points district on the other hand, farthest improved the radiating efficiency of lamination highly integrated chip.And technology integrated level height is easy to realize.
Description of drawings
Fig. 1 is a perspective view of the present invention.
Fig. 2 is the sectional view of A-A face among Fig. 1 of the present invention.
Embodiment
Below embodiments of the invention are elaborated, present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
As depicted in figs. 1 and 2, the refrigeration structure that is used for the three-dimensional encapsulation of microelectronics comprises: superimposed layer chip 1 and following laminated chips 2, the first longitudinal metal heat dissipation channel array 5, the second longitudinal metal heat dissipation channel array 9 and transverse metal heat dissipation channel array 6, wherein: the upper surface of the lower surface of superimposed layer chip 1 and following laminated chips 2 is respectively equipped with the first longitudinal metal heat dissipation channel array 5 and the second longitudinal metal heat dissipation channel array 9, and transverse metal heat dissipation channel array 6 is communicated between the first longitudinal metal heat dissipation channel array 5 and the second longitudinal metal heat dissipation channel array 9.
The described first longitudinal metal heat dissipation channel array 5 and the second longitudinal metal heat dissipation channel array 9 are made up of 10 parallel longitudinal metal heat dissipation channels 4, specifically be positioned at described superimposed layer chip 3 belows, 1 hot localised points district and described nonclient area 7 tops of laminated chips 2 down, the minimum spacing of a plurality of longitudinal metal heat dissipation channels 4 is at 2000 μ m.
Described longitudinal metal heat dissipation channel 4 is the rectangular column structure, and wherein: the Diagonal Dimension of rectangular column is at 100 μ m, and the rectangular column height is at 200 μ m.
Described transverse metal heat dissipation channel array 6 is made up of 5 transverse metal heat dissipation channels 10, and its thickness is at 100 μ m, and laterally the maximum cross-section width is at 20000 μ m, and laterally maximum cross-section length is at 20000 μ m.
Described transverse metal heat dissipation channel 10 and longitudinal metal heat dissipation channel 4 are Cu-Ni and make.
The present invention relates to the above-mentioned preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics, may further comprise the steps:
The first step: confirm superimposed layer chip 1 hot zone, adopt the litho pattern metallization processes to form in its corresponding region, back side and stated the hole array pattern, the back adopts dried wet-etching technology to be processed into deep hole, at hole inwall and surface sputtering metallic film as the Seed Layer of electroplating, and portion adopts the electrochemistry electroplating method to fill metal within it, can form longitudinal metal heat dissipation channel array 5;
Described hot zone is meant that power is output as the above chip area of 5W in the superimposed layer chip 1.
Described filling metal is meant Cu and Ni.
Second step: in the bottom of longitudinal metal heat dissipation channel 4, be on the lower surface of superimposed layer chip 1, adopt sputtering seed layer, photolithography patterning and electrochemistry electroplating method to prepare transverse metal heat dissipation channel 6, make heat under the prerequisite that gets around the chip operation district, arrive the cooling system of outermost with the shortest heat dissipation path;
The method that the 3rd step, second step of repetition adopt is carried out the preparation of transverse metal heat dissipation channel 6 to following laminated chips 2 nonclient areas 7, realizes the heat dissipation path of superimposed layer chip 1 to following laminated chips 2 to cooling system.
Each longitudinal metal heat dissipation channel 7 its bottom or top in the longitudinal metal heat dissipation channel array 5 in the described heat dissipation path, directly link to each other with transverse metal heat dissipation channel 6 surfaces, form the solid heat dissipation channel, heat is 3 arrival longitudinal metal heat dissipation channel arrays 5 from chip hot localised points district, the back arrives transverse metal heat dissipation channel 6 by longitudinal metal heat dissipation channel array 5 and being connected of transverse metal heat dissipation channel 6, the back arrives the other end of transverse metal heat dissipation channel 6, arrive the transverse metal heat dissipation channel of time one-level via the heat dissipation channel that is attached thereto (can continue is longitudinal metal heat dissipation channel 8), or directly arrive peripheral cooling system 11, finally finish heat dissipation; The heat heat dissipation path of forming by longitudinal metal heat dissipation channel array 5 and transverse metal heat dissipation channel 6 at chip hot localised points district 3, represented from chip hot localised points district 3 to arrive peripheral cooling system 11, and guaranteed in diabatic process, to avoid through causing the shortest path in the zone that chip can't operate as normal.
Claims (7)
1. preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics, this refrigeration structure comprises two laminated chips, two longitudinal metal heat dissipation channel arrays and a transverse metal heat dissipation channel array, in the tool: the upper surface of the lower surface of superimposed layer chip and following laminated chips respectively is provided with a longitudinal metal heat dissipation channel array respectively, transverse metal heat dissipation channel array is communicated between two longitudinal metal heat dissipation channel arrays, tool is characterised in that, described preparation method may further comprise the steps:
The first step: confirm superimposed layer die hot spots district, adopt the litho pattern metallization processes to form the hole array pattern in corresponding region, the tool back side, the back adopts dried wet-etching technology to be processed into deep hole, at hole inwall and surface sputtering metallic film as the Seed Layer of electroplating, and, promptly form longitudinal metal heat dissipation channel array at the inner electrochemistry electroplating method filling metal that adopts of tool;
Second step: in the bottom of longitudinal metal heat dissipation channel, be on the lower surface of superimposed layer chip, adopt sputtering seed layer, photolithography patterning and electrochemistry electroplating method to prepare the transverse metal heat dissipation channel, make heat under the prerequisite that gets around the chip operation district, arrive the cooling system of outermost with the shortest heat dissipation path;
The 3rd step, repetition second go on foot the method that adopts following laminated chips hot localised points district are carried out the preparation of transverse metal heat dissipation channel, realize that laminated chips was to the heat dissipation path of cooling system under the superimposed layer chip extremely.
2. the preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics according to claim 1, the tool feature is, described longitudinal metal heat dissipation channel array is made up of a plurality of longitudinal metal heat dissipation channels, be positioned at the nonclient area top of below, described superimposed layer chip hot localised points district and described laminated chips down, the minimum spacing of a plurality of longitudinal metal heat dissipation channels is in 10～100000 mu m ranges.
3. the preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics according to claim 1 and 2, the tool feature is, described longitudinal metal heat dissipation channel is rectangular column structure or column structure, in the tool: the Diagonal Dimension of rectangular column or body diameter are in 10～200 mu m ranges, and rectangular column or cylinder height are in 10～1000 mu m ranges.
4. the preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics according to claim 1, the tool feature is, described transverse metal heat dissipation channel array is made up of several transverse metal heat dissipation channels, tool thickness is in 1～500 mu m range, laterally the maximum cross-section width is in 10～100000 mu m ranges, and laterally maximum cross-section length is in 100～100000 mu m ranges.
5. according to claim 1 or the 2 or 4 described preparation methods that are used for the refrigeration structure of the three-dimensional encapsulation of microelectronics, the tool feature is that a kind of or its combination that described transverse metal heat dissipation channel and longitudinal metal heat dissipation channel are among Cu, Au, Zn, Ag or the Ni is made.
6. the preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics according to claim 1, tool feature are that described hot zone is meant that power is output as the above chip area of 5W in the superimposed layer chip.
7. the preparation method who is used for the refrigeration structure of the three-dimensional encapsulation of microelectronics according to claim 1, the tool feature is that described filling metal is meant a kind of or its combination among Cu, Au, Zn, Ag or the Ni.
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| CN2009103083043A CN101667568B (en) | 2009-10-15 | 2009-10-15 | Preparation method of refrigeration structure for three-dimensional encapsulation of micro-electronics |
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| CN101667568B true CN101667568B (en) | 2011-01-19 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| RU2011143856A (en) | 2009-05-18 | 2013-06-27 | БиЭсЭсТи ЭлЭлСи | BATTERY THERMAL CONTROL SYSTEM |
| JP2012253107A (en) * | 2011-05-31 | 2012-12-20 | Zycube:Kk | Laminated module and interposer used for the same |
| US9189037B2 (en) * | 2012-06-12 | 2015-11-17 | Globalfoundries Inc. | Optimizing heat transfer in 3-D chip-stacks |
| CN103633039B (en) * | 2012-08-29 | 2017-02-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor heat radiation structure and formation method thereof and semiconductor chip |
| WO2015066079A1 (en) * | 2013-10-29 | 2015-05-07 | Gentherm Incorporated | Battery thermal management with thermoelectrics |
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